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revision history - first edition: march 1999 - second edition: february 2000 ? library name change STD111 ? all characteristic values are updated with mass product line characteristics. ? add high density compiled memories to second edition. (chapter 5) ? the name of previous compiled memories are changed for example: spsram into spsram_lp ? power equations are changed. (chapter 1) ? updated pll information ? updated wire-load model
STD111 for pure logic products 0.25 m 2.5v cmos standard cell library
STD111 0.25 m 2.5v cmos standard cell library for pure logic products data book ? 1999-2000 samsung electronics co., ltd. all rights reserved. no part of this document may be reproduced, in any form or by any means, without the prior written consent of the publisher. samsung assumes no responsibility for any errors resulting from the use of the information contained herein, nor does it convey any license under the patent rights of samsung or others. samsung reserves the right to make changes in its products or product specification to improve function or design at any time, without notice. sec and STD111 are trademarks of samsung electronics co., ltd. verilog is a registered trademark of cadence design systems, inc. viewlogic is a registered trademark of viewlogic systems, inc. mentor is a registered trademark or mentor graphics co. synopsys is a registered trademark of synopsys, inc. head office samsung electronics co., ltd system lsi business, asic division, soc design technology san #24, nongseo-ri, kiheung-eup, yongin-city, kyunggi-do, korea tel 82-2-760-6500, 6501 (hot line) fax 82-331-209-4920 http://www.intl.samsungsemi.com printed in the republic of korea marketing team samsung electronics co., ltd system lsi business, asic division, asic marketing team san #24, nongseo-ri, kiheung-eup, yongin-city, kyunggi-do, korea tel 82-2-331-209-1930 fax 82-2-331-209-1919
samsung asic iv STD111 introduction this databook contains information about STD111 0.25 m 2.5v standard cell library for pure logic products developed by sec (samsung electronics corporation). the ?ibrary?basically contains various kinds of internal and i/o cells and soft-macros which are used for developing asic (application specific integrated circuit). it also includes a design kit helping designers to work in a workstation platform, and all sorts of design environments needed for an automatic chip design. there are six chapters in this databook: chapter 1 introduction chapter 2 electrical characteristics chapter 3 internal macrocells chapter 4 input/output cells chapter 5 compiled macrocells chapter 6 pll in this databook each cell is followed by its ac electrical characteristics, and these characteristic values are almost equal when the corresponding cell is operated in a real chip. the purpose of this databook is to prevent any misuse or misapplication of STD111 cell library by providing precise information about the cell list, electrical data, directions for use, and matters demanding special attention. if you want to get more information about digital cores and analog cores that are not included in this databook, access the samsung asic web site(http://www.intl.samsungsemi.com) or contact head office.
samsung asic v STD111 contents 1 introduction 1.1 library description ...................................................................................................... ..........1-1 1.2 features ................................................................................................................. ...............1-2 1.3 eda support .............................................................................................................. ...........1-4 1.4 product family ........................................................................................................... ...........1-4 1.4.1 analog core cell.................................................................................................1-4 1.4.2 internal macrocells..............................................................................................1-12 1.4.3 compiled macrocells...........................................................................................1-12 1.4.4 input/output cells ...............................................................................................1-14 1.5 timings.................................................................................................................... ................1-16 1.6 delay model ................................................................................................................ ............1-22 1.7 testability design methodology............................................................................................. ..1-24 1.8 maximum fanouts ............................................................................................................ .......1-27 1.9 packages capability by lead count .......................................................................................1-3 4 1.10 power dissipation......................................................................................................... .........1-36 1.11 v dd /v ss rules and guidelines..............................................................................................1-39 1.12 crystal oscillator considerations ......................................................................................... .1-45 2 electrical characteristics dc electrical characteristics.................................................................................................. .......2-1 3 internal macrocells overview ....................................................................................................................... ................3-1 summary tables ................................................................................................................. ..........3-2 logic cells ad2dh/ad2/ad2d2/ad2d4 .........................................................................................................3 -17 ad3dh/ad3/ad3d2/ad3d4 .........................................................................................................3 -19 ad4dh/ad4/ad4d2/ad4d4 .........................................................................................................3 -21 ad5/ad5d2/ad5d4 ................................................................................................................ ......3-24 nd2dh/nd2/nd2d2/nd2d4 ........................................................................................................3- 27 nd3dh/nd3/nd3d2/nd3d4 ........................................................................................................3- 29 nd4dh/nd4/nd4d2/nd4d2b/nd4d4 .........................................................................................3-32 nd5/nd5d2/nd5d4................................................................................................................ ......3-35 nd6/nd6d2/nd6d4................................................................................................................ ......3-38
STD111 vi samsung asic contents nd8/nd8d2/nd8d4 ................................................................................................................ .....3-42 nr2dh/nr2/nr2d2/nr2d2b/nr2d4/nr2a ..............................................................................3-46 nr3dh/nr3/nr3d2/nr3d2b/nr3d4/nr3a ..............................................................................3-49 nr4dh/nr4/nr4d2/nr4d2b/nr4d4 .........................................................................................3-53 nr5/nr5d2/nr5d4 ................................................................................................................ .....3-56 nr6/nr6d2/nr6d4 ................................................................................................................ .....3-60 nr8/nr8d2/nr8d4 ................................................................................................................ .....3-64 or2dh/or2/or2d2/or2d4 .......................................................................................................3-6 8 or3dh/or3/or3d3/or3d4 .......................................................................................................3-7 0 or4dh/or4/or4d2/or4d4 .......................................................................................................3-7 3 or5/or5d2/or5d4 ................................................................................................................ .....3-76 xn2/xn2d2/xn2d4 ................................................................................................................ ......3-80 xn3/xn3d2/xn3d4 ................................................................................................................ ......3-82 xo2/xo2d2/xo2d4 ................................................................................................................ .....3-84 xo3/xo3d2/xo3d4 ................................................................................................................ .....3-86 ao21dh/ao21/ao21d2/ao21d2b/ao21d4 ...............................................................................3-88 ao211dh/ao211/ao211d2/ao211d2b/ao211d4 .....................................................................3-91 ao2111/ao2111d2 ................................................................................................................ ......3-94 ao22dh/ao22/ao22d2/ao22d2b/ao22d4 ...............................................................................3-97 ao22dha/ao22a/ao22d2a/ao22d4a .......................................................................................3-100 ao221/ao221d2/ao221d4.......................................................................................................... 3-103 ao222/ao222d2/ao222d2b/ao222d4.......................................................................................3-107 ao222a/ao222d2a/ao222d4a...................................................................................................3-11 2 ao2222/ao2222d2/ao2222d4....................................................................................................3-1 14 ao31dh/ao31/ao31d2/ao31d4.................................................................................................3-118 ao311/ao311d2/ao311d4.......................................................................................................... 3-121 ao3111/ao3111d2 ................................................................................................................ ......3-125 ao32/ao32d2/ao32d4............................................................................................................. ...3-128 ao321/ao321d2/ao321d4.......................................................................................................... 3-132 ao322/ao322d2/ao322d4.......................................................................................................... 3-136 ao33/ao33d2/ao33d4............................................................................................................. ...3-140 ao331/ao331d2/ao331d4.......................................................................................................... 3-144 ao332/ao332d2/ao332d4.......................................................................................................... 3-148 ao4111/ao4111d2 ................................................................................................................ ......3-152 oa21dh/oa21/oa21d2/oa21d2b/oa21d4 ...............................................................................3-155 oa211dh/oa211/oa211d2/oa211d2b/oa211d4 .....................................................................3-158 oa2111/oa2111d2 ................................................................................................................ ......3-161 oa22dh/oa22/oa22d2/oa22d2b/oa22d4 ...............................................................................3-164 oa22dha/oa22aoa22d2a/oa22d4a ........................................................................................3-167 oa221/oa221d2/oa221d4.......................................................................................................... 3-170 oa222/oa222d2/oa222d2b/oa222d4.......................................................................................3-174 oa2222/oa2222d2/oa2222d4....................................................................................................3-1 79 oa31/oa31d2/oa31d4............................................................................................................. ...3-183
samsung asic vii STD111 contents oa311/oa311d2/oa311d4.......................................................................................................... 3-186 oa3111/oa3111d2 ................................................................................................................ ......3-190 oa32/oa32d2/oa32d4............................................................................................................. ...3-193 oa321/oa321d2/oa321d........................................................................................................... .3-197 oa322/oa322d2/oa322d4.......................................................................................................... 3-201 oa33/oa33d2/oa33d4............................................................................................................. ...3-205 oa331/oa331d2/oa331d4.......................................................................................................... 3-209 oa332/oa332d2/oa332d4.......................................................................................................... 3-213 oa4111/oa4111d2 ................................................................................................................ ......3-217 scg1/scg1d2 .................................................................................................................... .........3-220 scg2//scg2d2 ................................................................................................................... .........3-223 scg3/scg3d2 .................................................................................................................... .........3-225 scg4/scg4d2 .................................................................................................................... .........3-228 scg5/scg5d2 .................................................................................................................... .........3-231 scg6/scg6d2 .................................................................................................................... .........3-234 scg7/scg7d2 .................................................................................................................... .........3-236 scg8/scg8d2 .................................................................................................................... .........3-239 scg9/scg9d2 .................................................................................................................... .........3-241 scg10/scg10d2 .................................................................................................................. .......3-243 scg11/scg11d2 .................................................................................................................. .......3-246 scg12/scg12d2 .................................................................................................................. .......3-248 scg13/scg13d2 .................................................................................................................. .......3-250 scg14/scg14d2 .................................................................................................................. .......3-252 scg15/scg15d2 .................................................................................................................. .......3-254 scg16/scg16d2 .................................................................................................................. .......3-256 scg17/scg17d2 .................................................................................................................. .......3-258 scg18/scg18d2 .................................................................................................................. .......3-260 scg19/scg19d2 .................................................................................................................. .......3-263 scg20/scg20d2 .................................................................................................................. .......3-265 scg21/scg21d2 .................................................................................................................. .......3-267 scg22/scg22d2 .................................................................................................................. .......3-269 dl1d2/dl1d4 .................................................................................................................... ...........3-271 dl2d2/dl2d4 .................................................................................................................... ...........3-272 dl3d2/dl3d4 .................................................................................................................... ...........3-273 dl4d2/dl4d4 .................................................................................................................... ...........3-274 dl5d2/dl5d4 .................................................................................................................... ...........3-275 dl10d2/dl10d4 .................................................................................................................. .........3-276 ivdh/iv/ivd2/ivd3/ivd4/ivd6/ivd8/ivd16 .................................................................................3-277 ivcd(11/13)/ivcd(22/26)/ivcd44................................................................................................3 -280 ivt/ivtd2/ivtd4/ivtd8/ivtd16 ..................................................................................................3 -282 ivtn/ivtnd2/ivtnd4/ivtnd8/ivtnd16 .....................................................................................3-284 nidh/nid/nid2/nid3/nid4/nid6/nid8/nid16 .............................................................................3-286 oak_nid10p/oak_nid20p .........................................................................................................3 -289
STD111 viii samsung asic contents nit/nitd2/nitd4/nitd8/nitd16 .................................................................................................3- 290 nitn/nitnd2/nitnd4/nitnd8/nitnd16 ....................................................................................3-293 oak_duclk10/oak_duclk16..................................................................................................3-296 ctsb/ctsbd2/ctsbd3/ctsbd4/ctsbd6/ctsbd8/ctsbd16................................................3-298 flip-flops fd1/fd1d2 ...................................................................................................................... .............3-303 fd1cs/fd1csd2 .................................................................................................................. .......3-305 fd1s/fd1sd2 .................................................................................................................... ..........3-307 fd1sq/fd1sqd2.................................................................................................................. .......3-309 fd1q/fd1qd2 .................................................................................................................... .........3-311 fd2/fd2d2 ...................................................................................................................... .............3-313 fd2cs/fd2csd2 .................................................................................................................. .......3-315 fd2s/fd2sd2 .................................................................................................................... ..........3-319 fd2sq/fd2sqd2.................................................................................................................. .......3-321 fd2q/fd2qd2 .................................................................................................................... .........3-323 fd3/fd3d2 ...................................................................................................................... .............3-325 fd3cs/fd3csd2 .................................................................................................................. .......3-327 fd3s/fd3sd2 .................................................................................................................... ..........3-331 fd3sq/fd3sqd2.................................................................................................................. .......3-333 fd3q/fd3qd2 .................................................................................................................... .........3-335 fd4/fd4d2 ...................................................................................................................... .............3-337 fd4cs/fd4csd2 .................................................................................................................. .......3-340 fd4s/fd4sd2 .................................................................................................................... ..........3-344 fd4sq/fd4sqd2.................................................................................................................. .......3-348 fd4q/fd4qd2 .................................................................................................................... .........3-351 fd5/fd5d2 ...................................................................................................................... .............3-353 fd5s/fd5sd2 .................................................................................................................... ..........3-355 fd6/fd6d2 ...................................................................................................................... .............3-357 fd6s/fd6sd2 .................................................................................................................... ..........3-359 fd7/fd7d2 ...................................................................................................................... .............3-361 fd7s/fd7sd2 .................................................................................................................... ..........3-363 fd8/fd8d2 ...................................................................................................................... .............3-365 fd8s/fd8sd2 .................................................................................................................... .........3-368 fds2/fds2d2 .................................................................................................................... ..........3-372 fds2cs/fds2csd2 ................................................................................................................ ....3-374 fds2s/fds2sd2 .................................................................................................................. .......3-376 fds3/fds3d2 .................................................................................................................... ..........3-378 fds3cs/fds3csd2 ................................................................................................................ ....3-380 fds3s/fds3sd2 .................................................................................................................. .......3-382 fj1/fj1d2...................................................................................................................... ...............3-384 fj1s/fj1sd2 .................................................................................................................... ............3-386 fj2/fj2d2...................................................................................................................... ...............3-388
samsung asic ix STD111 contents fj2s/fj2sd2 .................................................................................................................... ............3-390 fj4/fj4d2...................................................................................................................... ...............3-392 fj4s/fj4sd2 .................................................................................................................... ............3-395 ft2/ft2d2 ...................................................................................................................... ..............3-398 latches ld1/ld1d2 ...................................................................................................................... .............3-402 ld1a/ld1d2a.................................................................................................................... ...........3-404 ld1q/ld1qd2 .................................................................................................................... ..........3-406 ld2/ld2d2 ...................................................................................................................... .............3-408 ld2q/ld2qd2 .................................................................................................................... ..........3-411 ld3/ld3d2 ...................................................................................................................... .............3-413 ld4/ld4d2 ...................................................................................................................... .............3-416 ld5/ld5d2 ...................................................................................................................... .............3-419 ld5q/ld5qd2 .................................................................................................................... ..........3-421 ld6/ld6d2 ...................................................................................................................... .............3-423 ld6q/ld6qd2 .................................................................................................................... ..........3-426 ld7/ld7d2 ...................................................................................................................... .............3-428 ld8/ld8d2 ...................................................................................................................... .............3-431 oak_ldi2/oak_ldi2d2 ............................................................................................................ ..3-434 oak_ldi3/oak_ldi3d2 ............................................................................................................ ..3-437 ls0/ls0d2 ...................................................................................................................... ..............3-442 ls1/ls1d2 ...................................................................................................................... ..............3-444 bus holder busholder ...................................................................................................................... ..........3-448 internal clock drivers ck(2/4/6/8) .................................................................................................................... ................3-449 decoders dc4 ............................................................................................................................ ...................3-452 dc4i ........................................................................................................................... ...................3-454 dc8i ........................................................................................................................... ...................3-456 adders fadh/fa/fad2................................................................................................................... ...........3-461 hadh/ha/had2................................................................................................................... .........3-464 scg23/scg23d2 .................................................................................................................. .......3-467 multiplexers mx2dh/mx2/mx2d2/mx2d4 .......................................................................................................3-4 71 mx2x4 .......................................................................................................................... ................3-474 mx2idh/mx2i/mx2id2/mx2id4 ...................................................................................................3-4 77 mx2idha/mx2ia/mx2id2a/mx2id4a..........................................................................................3-480
STD111 x samsung asic contents mx2ix4 ......................................................................................................................... ................3-483 mx3i/mx3id2/mx3id4 ............................................................................................................. .....3-486 mx4/mx4d2/mx4d4 ................................................................................................................ .....3-490 mx8/mx8d2/mx8d4 ................................................................................................................ .....3-494 4 input/output cells overview ....................................................................................................................... ................4-1 summary tables ................................................................................................................. ..........4-2 input buffers pvic/pvicd/pvicu............................................................................................................... .........4-8 pvis/pvisd/pvisu ............................................................................................................... .........4-12 pvit/pvitd/pvitu ............................................................................................................... ..........4-16 output buffers pvobyz ......................................................................................................................... ................4-20 pvodyz ......................................................................................................................... ................4-29 pvotyz ......................................................................................................................... .................4-39 bi-directional buffers pvbadyz/pvbaudyz ............................................................................................................... ......4-59 pvbatyz/pvbadtyz/pvbautyz .....................................................................................................4 -59 input clock drivers psckdcaby...................................................................................................................... ............4-61 psckdsaby...................................................................................................................... ............4-65 oscillators phsosc(k1/k2/m1/m2/m3) ......................................................................................................... 4-70 phsosc(k17/k27/m16/m26/m36) ...............................................................................................4-76 psosc(k1/k2/m1/m2) ............................................................................................................. ....4-82 pci buffers ptipci......................................................................................................................... ..................4-89 ptopci ......................................................................................................................... ................4-90 ptbpci ......................................................................................................................... ................4-91 usb i/o buffers pbusb/pbusb1 ................................................................................................................... ........4-94 pbusb_ls....................................................................................................................... .............4-95 pbusb_fs....................................................................................................................... .............4-96
samsung asic xi STD111 contents power pads vdd2(i/p/o/ip/op/t/r)/vdd3(p/o/op) .......................................................................................4-103 vss2(i/p/o/ip/op/t/r)/vss3(p/o/op) ........................................................................................4-103 analog interface pic_abb ........................................................................................................................ ...............4-105 picc_abb ....................................................................................................................... .............4-106 picen_abb ...................................................................................................................... ............4-107 pot1/2/3/4_abb................................................................................................................. ..........4-108 esd slot cells ev2i/ev2p/ev2o/ev2ip/ev2op/ev2t/ev2p/ev2o/ev2op......................................................4-111 ev2i_abb/ev2op_abb/ev2t_abb ............................................................................................4-111 common slot cells ec0c0/ec0c0d/ec0ca0/ec0ca0d/ec0c0_bb/ec0c0d_bb/ec0c0_vbb/ec0c0d_vbb ............................................................................................................................... .......................4-112 5 compiled macrocells overview to compiled memory .................................................................................................... .5-1 compiled memory naming convention.........................................................................................5-1 characteristics for timing and power........................................................................................... .5-2 built-in self test for compiled memory ......................................................................................... 5-3 selection guide for compiled memory..........................................................................................5- 4 high-density compiled memory spsram_hd ...................................................................................................................... .........5-7 spsrambw_hd .................................................................................................................... .....5-17 dpsram_hd ...................................................................................................................... .........5-27 sparam_hd ...................................................................................................................... ..........5-37 drom_hd ........................................................................................................................ ............5-48 mrom_hd........................................................................................................................ ............5-56 arfram_hd ...................................................................................................................... .........5-64 fifo_hd ........................................................................................................................ ...............5-83 low-power compiled memory spsram_lp ...................................................................................................................... ..........5-95 dpsram_lp ...................................................................................................................... .........5-105 sparam_lp ...................................................................................................................... ...........5-115 drom_lp ........................................................................................................................ .............5-125 mrom_lp........................................................................................................................ .............5-133
STD111 xii samsung asic contents overview to compiled datapath overview to compiled datapath .................................................................................................. .5-141 compiled macrocell selection guide ............................................................................................5 -142 adder.......................................................................................................................... ................5-143 bs ............................................................................................................................. ....................5-148 mpy ............................................................................................................................ ..................5-153 6 pll pll2013x ....................................................................................................................... ..............6-1
note
1 introduction
table of contents 1.1 library description .............................................................................................. 1-1 1.2 features .............................................................................................................. 1-2 1.3 eda support ....................................................................................................... 1-4 1.4 product family..................................................................................................... 1-4 1.4.1 analog core cells...................................................................................... 1-4 1.4.2 internal macrocells .................................................................................... 1-12 1.4.3 compiled macrocells ................................................................................. 1-12 1.4.4 input/output cells ...................................................................................... 1-14 1.5 timings................................................................................................................ 1-16 1.6 delay model ........................................................................................................ 1-22 1.7 testability design methodology........................................................................... 1-24 1.8 maximum fanouts............................................................................................... 1-27 1.9 packages capability by lead count ................................................................... 1-34 1.10 power dissipation ............................................................................................. 1-36 1.11 v dd /v ss rules and guidelines .......................................................................... 1-39 1.12 crystal oscillator considerations...................................................................... 1-45
introduction 1.1 library description samsung asic 1-1 STD111 1.1 library description samsung asic offers STD111 as 0.25um cmos standard cell library. samsung's 0.25um cell-based logic process providing up to 5 layers of interconnect metal with various i/o pad-pitch options such as 70um pitch pad and 80um pitch pad. STD111 which reduced power dissipation and system cost by merging the logic and ips as a whole and connecting internally from logic to memory data bus is ideal for high-performance products such as graphics controller, projector, portable cd and so on. STD111 can support up to six million gate counts of logic providing 75% of usable gate. STD111 is 25% faster than 0.35um library std90. logic density is 1.7 times greater than that of std90. the power consumption of compiled memory is 90% smaller than std90. STD111 also supports fully user-configurable compiled memory and datapath elements. each element is provided as a compiler. two different types of compiled memories in STD111 are available to support memories suitable to high-density and low-power applications. to support mixed voltage environments, 2.5v, 3.3v drive and 5v-tolerant io cells are available. lvttl, lvcmos, pci, osc, agp, pecl, hstl, lvds and usb buffers are supported. to better support a system-on-chip design style, various core cells are available including processor cores like arm7tdmi/arm9tdmi/ arm920t/arm940t from arm, teaklite from dspg. the STD111 supports data transmission and communication core such as usb, ieee1284 and uart. the list of analog core cells includes adc, dac, codec, lvds, ramdac and pll with various bits and frequency ranges. samsung design methodology offers an comprehensive timing driven design flow including automated time budgeting, tight floorplan synthesis intergration, powerful timing analysis and timing driven layout. its advanced characterization flow provides accurate timing data and robust delay models for a 0.25um very deep-submicron technology. advanced verification methods like static timing analysis and formal verification provide an effective verification methodology with a variety of simulators and cycle based simulation. samsung dft methodology supports scan design, bist and jtag boundary scan. samsung provides a full set of test-ready ips with an efficient core test integration methodology.
1.2 features introduction STD111 1-2 samsung asic 1.2 features ? 2.5v standard cell library including processor and analog cores ? 0.25um ?ve layer metal(from four layer metal option) cmos technology - logic, processor and analog ? high basic cell usages - up to 6 million gates - maximum usage: 75% for ?ve layer metal ? high speed - typical 2-input nand gate delay (nd2d4): 68ps (f/o=2 + wl (0.02pf)) ? operation temperature (t a ) - commercial range: 0 c to +70 c - industrial range: - 40 c to +85 c ? digital cores usages - hard-macro: arm7tdmi, arm9tdmi, arm920t, arm940t, teaklite - soft-macro: amba, dma controller, sdram controller, interrupt controller, iic, wdt, rtc, usb, irda, uart (16c450, 16c550), fast ethernet mac, p1394a link, rs decoder, viterbi decoder ? analog cores usages - ultra low voltage analog core (2.5v and 1.8v) available - analog core supply voltage: 2.5v analog core: 2.5v 5% 1.8v analog core: 1.8v 5% - adc: 8bit (30m, 2.5v), 10bit ((30m, 100m, 2.5v), (250k, 20m, 1.8v)), 12bit (200k, 20m, 2.5v) - dac: 8bit (2m, 2.5v), 10bit ((300m, 2.5v), (2m, 1.8v)), 12bit ((2m, 2.5v), (80m, 1.8v)) - codec: 8bit (8k~11k), 16bit (44.1k) - pll: 25m ~ 300m (fspll, 2.5v), 1g (pll, 2.5v), 20m ~ 170m (fspll, 1.8v) - others: 300m (ramdac+pll) ? fully user-con?gurable static rams and roms - high-density and low-power memory available - duty-free cycle in synchronous memory available - 2-bank architecture available - flexible aspect ratio available - up to 256k-bit single-port sram available. - up to 128k-bit dual-port sram available. - up to 512k-bit diffusion and metal-2 rom available. - up to 16k-bit multi-port register ?le available. - up to 32k-bit fifo available. ? fully con?gurable datapath macrocells - 4 ~ 64 bit adder available - 4 ~ 64 bit barrel shifter available - 6 ~ 64 bit multiplier with 1-stage pipeline available - various output driver strength available - a tightly integrate apollo, avant!, design environment ? i/o cells - 2.5v/3.3v and 5v tolerant io - 3-level (high, medium, no) slew rate control - 1/2/4/6/8/10/12ma available for 3.3v and 2.5v output buffers - 1/2/3ma available for 5v-tolerant output buffers
introduction 1.2 features samsung asic 1-3 STD111 ? io ip available - pci ((33mhz, 66mhz, 3.3v), (33mhz, 3.3/5v tolerant)) - usb (full speed/low speed) - sstl2 (ddr sdram interface, up to 200mhz) - agp (agp2.0 compliant, 66mhz@1x,133mhz@2x, 266mhz@4x) - pecl (2.5v interface, up to 400mhz) - hstl (class1, class2, 30mhz) - lvds (3.3v(2.5v optional) interface, 300mhz) ? various package options - qfp, thin qfp, power qfp, plastic bga, super bga, plastic leaded chip carrier, etc. ? fully integrated cad software and eda support - logic synthesis: synopsys design compiler - logic simulation: cadence verilog-xl, cadence nc-verilog, viewlogic viewsim, mentor modelsim-vhdl, mentor modelsim-verilog, synopsys vss, synopsys vcs - scan insertion and atpg: synopsys testgen, synopsys test compiler, mentor fastscan - static timing analysis: synopsys primetime, synopsys motive - rc analysis: avant! star-rc - power analysis: synopsys designpower, cubicpower (ln-house tool) - formal veri?cation: synopsys formality, chrysalis design verifyer, verplex tuxedo-lec - fault simulation: cadence verifault, supertest (in-house tool) - delay calculator: cubicdelay (in-house tool) ? STD111 contains 12 user selectable clock tree cells(ctc). at the pre-layout design stage, these will be used as the cells which represent actual clock tree informatin of p&r. the key features of new samsung asic cts ?ow are as follows: - 12 user selectable clock tree cells (ctc) for STD111 - good pre-layout and post-layout correlation - no customer netlist modi?cation - accurate post-layout back-annotation mechanism - insertion delay, skew, transition time management - clock tree information ?le generation - cover 100 to 30,000 fanouts and up to 1m gate count for cts spanning block (gccsb) - tightly coupled with samsung in-house delay calculator, cubicdelay gated cts support - hierarchical/flatten verilog, edif interface for p&r for more detail information for ctc flow, refer to ctc flow guideline for cubicdelay included in samsung asic design kit.
1.3 eda support introduction STD111 1-4 samsung asic 1.3 eda support samsung asic provides an efficient solution for multi-million gate asics in very deep submicron (vdsm) technology. for large system-on-chip (soc) type designs, static verification methodology (static timing analysis and formal verification) will shorten your design cycle time, which in turn will lessen today's ever-increasing time-to-market pressure. our design-for-test (dft) methodology and service take you through all phases of test insertion, test pattern generation and fault grading to get high test coverage. STD111 supports a rich collection of industry-standard eda tools from cadence, synopsys, mentor graphics, and avant! on multiple design platforms such as solaris and hp. customers are allowed to choose among the industry-leading eda tools from design capture, synthesis, simulation, and dft to layout. several powerful proprietary software tools are seamlessly integrated in our design kits to improve your product quality. for high simulation accuracy, STD111 uses a proprietary delay calculator. cell delay is calculated based on a matrix of delay parameters for each macrocell, and signal interconnect delay is calculated based on the rc tree analysis. 1.4 product family STD111 library include the following design elements: n analog core cells n digital core cells n internal macrocells n compiled macrocells n input/output cells. 1.4.1 analog core cells introduction to analog cores samsung asic is one of the leading suppliers of cell based mixed analog and digital designs. as a leading supplier of mixed analog and digital designs, samsung asic has more analog design experience than any other vendors. analog has been and will continue to be a part of the strategic focus at samsung asic. analog design is a part of the total samsung asic integrated design system. workstation symbols are supplied for analog cells and are entered as part of the design by the customer or design center. samsung asic uses basically the same automatic layout and verification tools for analog cells as for digital cells. analog designs are processed on the same production line as digital designs. samsung's analog core family comprises adc,dac,pll and sigma-delta adc/ dac, and their brief functional descriptions are introduced below. [data sheets for all analog cores available] analog-to-digital converters analog-to-digital converters provide the link between the analog world and digital systems. due to their extensive use of analog and mixed analog-digital operations, a/d converters often appear as the bottleneck in data processing applications, limiting the overall speed or precision. an a/d converter produces a digital output, d, as a function of the analog input, a: d = f(a) while the input can assume an infinite number of values, the output can be selected from only a finite set of codes given by the converter's output word length(i.e, resolution). thus, the adc must approximate each input level with one of these codes, this process is so called 'quantization'.
introduction 1.4 product family samsung asic 1-5 STD111 in a digital system the amplitude is quantized into discrete steps, and at the same time the signal is sampled at discrete time intervals. this time interval is called sampling time or sampling frequency. after sampling and quantization process, the analog signal(a) becomes digital output (d). digital-to-analog converters the d/a converters are the digital-to-analog conversion circuits, which are also called dacs. they can be considered as decoding devices that accept digitally coded signals and provide analog output in the form of currents or voltages. in this manner, they provide an interface between the digital signal of the computer systems and continuous signals of analog world. they are employed in a variety of applications, from crt display systems and voice sythesizers to automatic test systems, digital controlled attenuators, and process control actuators. in addition, they are key components inside most a/d converters. figure 1 shows the functional block diagram of a basic d/a converter system. the input to the d/a converter is a digital word, made up a stream of binary bits comprised of 1's and 0's. the output analog quantity a, which can be a voltage or current, is related to the input as where k is a scale factor, v ref is a reference voltage, n is the total number of bits, and b1,b2,...,bn are the bit coefficients, which are quntized to be a 1 or a 0. as a function of the input binary word which determines the bit coefficients, the output exhibits 2 n discrete voltage level ranging from zero to a maximum value of with a minimum step change d vo given as \ figure 1-1. functional block diagram of basic d/a converter akv ref b 1 2 1 ------ b 2 2 2 ------ ? bn 2 n ----- - +++ = vo(max) v ref 2 n 1 C 2 n ------------- = d vo v ref 2 n ------------- = d/a converter b1 b2 b3 bn analog output digital data input
1.4 product family introduction STD111 1-6 samsung asic sigma-delta adc/dac vlsi offers high speed and high density, but reduced accuracy for analog components and reduced signal range (reduced dynamic range). hence, an exchange of digital complexity and of resolution in time for resolution in signal amplitude is needed. so good solution is over-sampling data converter. oversampling sigma-delta converter is used in slow speed (audio band) application because of process limit. it's noise shaping (sigma-delta) feature make high resolution about max. snd=90~100db in adc path, analog single input is converted to differential signal with anti- aliasing filtering through anti-aliasing filter block. and sigma-delta modulator con- verts the signal into oversampled noise-shaping 1bit pdm (pulse density modu- lation). following digital decimation filter reject the out of band noise and outputs 16bits high resolution digital data with down sampled to fs rate. in dac path, dig- ital input data is oversampled by interpolation filter and it is converted to noise- shaped 1bit pdm through digital sigma-delta modulator. analog sc-post-filter re- jects the out of band noise. and anti-image filter rejects sampling images and out- puts single analog signal with high resolution. phase locked loop samsungs pll cores implemented as an analog function provide frequency multiplication capabilities and enable system designers to synchronize asic chip-level clock networks with a common reference signal. in the past, designers wishing to incorporate a pll into a digital design environment had only two options: (1) a special mixed-signal process to incorporate analog functions onto the chip (2) an all digital pll that can be incorporated into a standard digital process. however, a mixed-signal process is too expensive to be a feasible solution. on the other hand digital plls typically require huge silicon area and exhibits poor locking time despite their high accuracy. differing from the previous solutions, samsung's pll cores can be implemented on standard digital cmos process while functioning as an analog pll. samsung's pll cores: * require only a few off-chip passive components for the whole function * remove the need for an expensive mixed-signal process * provide faster locking time than all digital plls * present low jitter characteristics glossary by core families 1. digital-to-analog converter 1. resolution - an n-bit binary converter should be able to provide 2 n distinct and different analog output values corresponding to the set of n-bit binary words. a converter that satisfies this criterion is said to have resolution of n bits. the smallest output change that can be resolved by a linear dac is 2 -n of the full-scale span. 2. accuracy - error of a d/a converter is the difference between the actual analog output and the output that is expected when a given digital code is applied to the converter. source of error include gain error, offset error, linearity errors and noise. error is usually commensurate with resolution, less than 2 -(n+1) , or 1/2 lsb of full scale.
introduction 1.4 product family samsung asic 1-7 STD111 figure 1-2. error of d/a converter 3. lsb (least-significant bit) - in a system in which a numerical magnitude is represented by a series of binary digits, the lsb is that bit that carries the smallest value or weight. it represents the smallest analog change that can be resolved by an n-bit converter. lsb (analog value) = fsr/2 n fsr = full-scale range, n = number of bits 4. msb (most-significant bit) - the binary digit with the largest numerical weighting. normally, the msb of a digital word has a weighting of 1/2 the full range. 5. compliance-voltage range - for a current output dac, the maximum range of(output) terminal voltage for which the device will provide the specified current- output characteristics. 6. glitch - a glitch is a switching transient appearing in the output during a code transition. its value is expressed as a product of voltage (v*ns) or current (ma*ns) and time duration or charge transferred. 7. harmonic distortion (and total harmonic distortion) - the dac is driven by the digitized representation of sine wave. the ratio of the rms sum of the harmonics of the dac output to the fundamental value is the thd. usually only the lower order harmonics are included, such as second through fifth. v1: rms amplitude of the fundamental 8. signal-to-noise ratio (snr) - this signal to noise ratio depends on the resolution of the converter and automatically includes specifications of linearity, distortion, sampling time uncertainty, glitches, noise, and settling time. over half the sampling frequency, this signal to noise ratio must be specified and should ideally follows the theoretical formula; s/n max = 6.02n + 1.76db 9. slew rate - slew rate of a device or circuit is a limitation in the rate of change of output voltage, usually imposed by some basic circuit consideration such as limited current to charge of capacitor. amplifiers with slew rate of a few v/ m s are common and moderate in cost. slew rates greater than about 75 v/ m s are usually seen only in more sophisticated (and expensive) devices the output slewing speed of a voltage-output d/a converter is usually limited by the slew rate of the amplifier used at its output (if one is used). offset error ideal actual analog output digital input analog output digital input ideal actual gain error thd 20 v 2 2 v 3 2 v 4 2 v 5 2 +++ () 12 v 1 -------------------------------------------------------------- - log =
1.4 product family introduction STD111 1-8 samsung asic 10. settling time - the time required, following a prescribed data change from the 50% point of the login input change, for the output of a dac to reach and to remain within a given fraction (usually 1/2lsb) of the final value. typical pre- scribed changes are full scale, 1msb and 1lsb at a major carry. settling time of current-output dacs is quite fast. the major share of settling time of a voltage- output dac is usually contributed by the settling time of the output op-amp circuit. figure 1-3. setting time 11. power-supply sensitivity -the sensitivity of a converter to changes in the power-supply voltages is normally expressed in terms of percent-of-full-scale change in analog output value (of fractions of 1lsb) for a 1% dc change in the power supply. power supply sensitivity may also expressed in relation to a specified dc shift of supply voltage. a converter may be considered "good" if the change in reading at full scale does not exceed 1/2lsb for 3% change in power supply. even better specs are necessary for converters designed for battery operation. 12. ile (integral linearity error) - linearity error of a converter, expressed in %, ppm of full-scale range or multiples of 1lsb, is a deviation of the analog values in a plot of the measured conversion relationship from a straight line. the straight line can be either a "best straight line" determined empirically by manipulation of the gain and/or offset to equalize maximum positive and negative deviation of the actual transfer characteristics from this straight line; or it can be a straight line passing through the endpoints of the transfer characteristic endpoints of the transfer characteristic after they have been calibrated (sometimes referred to as "endpoint" linearity). endpoint linearity error is similar to relative accuracy error. for multiplying d/a converters, the analog linearity error, at a specified digital code, is defined in the same way as for multipliers, by deviation from a "best straight line" through the plot of the analog output-input response. 13. dle (differential linearity error) - any two adjacent digital codes should re- sult in measured output values that are exactly 1lsb apart (2-n of full scale for an n-bit converter). any deviation of the measured "step" from the ideal difference is called differential linearity error expressed in multiplies of 1lsb. it is an important specification because a differential linearity error greater than 1lsb can lead to non-monotonic response in a d/a converter and missed codes in an a/d convert- er. 14. monotonic - a dac is said to be monotonic if the output either increases or remains constant as the digital input increases with the result that the output will always be a single-valued function of the input. the specification "monotonic" final setting v 0 +d v 0 1 slewing setting time to d v 0 -d v 0 slew rate
introduction 1.4 product family samsung asic 1-9 STD111 (over a given temperature range) is sometimes substituted for a differential nonlinearity specification since differential nonlinearity less than 1lsb is a suffi- cient condition for monotonic behaviour. 2. analog-to-digital converter 1. ile (integral linearity error: inl) - integral nonlinearity refers to the deviation of each individual code from a line drawn from "zero" through "full scale". the point used as "zero" occurs 1 / 2 lsb before the first code transition. "full scale" is defined as a level 1 1 / 2 lsb beyond the last code transition. the deviation is measured from the center of each particular code to the true straight line. 2. dle (differential linearity error: dnl) - an ideal adc exhibits code transitions that are exactly 1lsb apart. dnl is the deviation from this ideal value. it is often specified in terms of the resolution for which no missing codes are guaranteed. 3. offset error - the first transition should occur at a level 1/2lsb above "zero". offset is defined as the deviation of the actual first code transition from that point. 4. gain error - the first code transition should occur for an analog value 1/2lsb above nominal negative full scale. the last transition should occur for an analog value 1 1 / 2 lsb below the nominal positive full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions. 5. pipeline delay (latency) - the number of clock cycles between conversion initiation and the associated output data being made available. new output data is provided every clock cycle. 6. effective number of bits (enob) - this is a measure of a device's dynamic performance and may be obtained from the sndr or from a sine wave curve test fit according to the following expression: enob = sndr - 1.76/6.02 enob = n-log2[rms error (actual) / rms error (ideal)] 7. analog bandwidth - the analog input frequency at which the spectral power of the fundamental frequency, as determined by fft analysis is reduced by 3db. 8. aperture delay - the delay between the sampling clock and the instant the analog input signal is sampled. 9. aperture jitter - the sample to sample variation in aperture delay. 10. bit error rate (ber) - the number of spurious code errors produced for any given input sine wave frequency at a given clock frequency. in this case it is the number of codes occurring outside the histogram cusp for a 1/2 fs sine wave. 11. signal to noise ratio - this signal to noise ratio depends on the resolution of the converter and automatically includes specifications of linearity, distortion, sampling time uncertainty, glitches, noise, and settling time. over half the sampling frequency, this signal to noise ratio must be specified and should ideally follow the theoretical formula; s/n max = 6.02n + 1.76db
1.4 product family introduction STD111 1-10 samsung asic 3. phase locked loop 1. lock time - the time it takes the pll to lock onto the system clock. fast or slow lock time may be controlled by the loop filter characteristics. the loop filter characteristics are controlled by varying the r and c components. (remember that r and c define the damping-factor as well) 2. phase error - the phase difference between the feedback clock signal and the system signal clock. 3. clock jitter - the deviations in a clock's output transitions from their ideal positions define the clock jitter. jitter is sometimes specified as an absolute value in nanoseconds. all jitter measurement are made at a specified voltage. 1) cycle-to-cycle jitter: the change in a clock's output transition from its corresponding position in the previous cycle. this kind of jitter is the most difficult to measure and usually requires a time-interval analyzer figure 1-4. cycle-to-cycle jitter : the maximum of such values over multiple cycles (j1,j2...) is the max. cycle-to- cycle jitter. 2) period jitter: period jitter measures the maximum change in a clock's output transition from its ideal position. you can use period-jitter measurements to calculate timing margins in systems. figure 1-5. period jitter 3) long-term jitter: long-term jitter measures the maximum change in a clock's output transition from its ideal position over many cycles. how many cycles depends on the application and the frequency. a classic example of system affected by long-term jitter is a graphics card driving a crt 4) power down mode: pll state in which the quiescent current is lowered to a very low level to conserve power. 5) synthesize clock: a system clock may run at a relatively low rate compared to system components. a cpu, for example, may require an internal clock that is several times faster than the system i/o bus clock. designers can use pll technology to synthesize a higher frequency on-chip clock using the system clock as a reference. clock t1 t2 t3 noise: jitter j1 = t2 - t1 jitter j2 = t3 - t2 clock ideal cycle: t1 jitter
introduction 1.4 product family samsung asic 1-11 STD111 6) deskew clock: multiple chips on a printed circuit board or cores of different sizes within a single system on a chip experience clock skew. by using pll or dll technology to shift the phase of the reference clock within each chip or core, designers can minimize skew tune a system to perform up its potential. 7) duty ratio: the percentage of the period that the output is in a high state. 8) output frequency range: the maximum output frequency range minus the minimum output frequency that is produced with an input signal for which the cell specifications still apply. customer service samsung provides a full custom support for our customers need of analog cores. samsung's worldwide sales offices and representatives give our customers a first-hand support for analog cores. and if needed, samsung engineers are pre- pared to provide a fully customized total solution to satisfy our customers. technical support if our customers want to develop mixed-signal products, samsung provides all technical support to meet customers needs. mixed-signal design is quite different from pure logic design in terms of circuit design, techniques, layout and test meth- odology. thus samsung provides a successful technical guide and firmly support for all development steps. de?nition of analog core data sheet types each product developed by samsung will be supported by technical literature where the data sheets progress through the following levels of refinement 1. core preview describes the main features and specifications for core that is under development. some specifications such as exact pin-outs may not be finalized at time of publication.the purpose of this document is to provide customers with advance product planning information. 2. preliminary datasheet this is the first document completely describing a new core. it contains an features, application, timing diagram, theory of operation, core pin information, test guide, layout guide and ac/dc electrical information. this data sheet are based on prototype silicon performance and on worst case simulation models.the purpose of this data sheet is to provide asic customer with technical information sufficiently detailed to guarantee that they can safely begin active development. 3.final data sheet this is an updated version of preliminary data sheet reflecting actual performance of the final silicon. updates include tighter specifications, more min. and max. values. the purpose of this data sheet is to communicate the confirmed performance of cores which have passed qualification, been fully characterized.
1.4 product family introduction STD111 1-12 samsung asic 1.4.2 internal macrocells internal macrocells are the lowest level of logic functions such as nand, nor and ?ip-?op used for logic designs. there are about 471 different types of internal macrocells. they usually come in four levels of drive strength (0.5x, 1x, 2x and 4x). these macrocells have many levels of representationslogic symbol, logic model, timing model, transistor schematic, hspice netlist, physical layout, and placement and routing model. 1.4.3 compiled macrocells compiled macrocells of STD111 consist of compiled memory and compiled datapath macrocells. 1.4.3.1 compiled memory macrocells memories in STD111 are fully user-configurable and are provided as a compiler. two different types of memories are available in STD111. one is suitable for high- density application with high-performance, called STD111-hd compiled memory. the other is suitable for low-power application, called STD111-lp compiled memory. in STD111-hd compiled memory, eight types of memories are available such as single-port synchronous/asynchronous static ram, dual-port synchronous static ram, synchronous diffusion/metal-programmable rom, multi-port asynchronous register file and synchronous first-in first-out memory. synchronous memories have a fully synchronous operation at the rising-edge of clock and the duty-free cycle is available. also, the bit-write capability is available. asynchronous memories have a synchronous operation for a write enable signal during write mode and have an asynchronous operation for address signal during read mode. multi-port asynchronous register file supports four kinds of configurations such as 2 port(1-read/1-write), 3 port(1-read/2-write and 2-read/1- write) and 4 port (2-read/2-write). the first-in first-out memory which is widely used in communication buffering types of applications has also fully synchronous operation at the rising- edge of clock. on the other hand, in STD111-lp compiled memory, five types of memories are available such as single-port synchronous/asynchronous static ram, dual-port synchronous static ram and synchronous diffusion/metal-programmable rom. synchronous memories are almost same as that of STD111-hd except that the duty-free cycle is not available. asynchronous memory is same as that of STD111-hd. to dramatically reduce the power consumption in STD111-lp, some of low- power techniques such as a partial activation architecture in cell array and a divided word-line structure was adopted, rather than STD111-hd. basically in STD111-hd and STD111-lp, the power-down mode which significantly reduces the power dissipated during a read or write mode is provided. also compiled memories have a standby mode except multi-port asynchronous register file and first-in first-out memory. while in standby mode, the data stored in the memory is retained, data outputs remain stable and the power is greatly reduced because memory operation is internally blocked while the memory contents and the data outputs are unaffected.
introduction 1.4 product family samsung asic 1-13 STD111 to improve the memory performance and to reduce the power consumption, 2- bank architecture is provided except some memories such as dual-port synchronous static ram, multi- port asynchronous register file and first-in first-out memory. in 2-bank architecture, only one bank is activated and the other bank is in standby mode. to support various memory shapes which are determined by the floorplan of a chip design, flexible memory aspect ratios are provided. for certain specific memory configuration, all types of timing, power and area values are provided by an automatic datasheet generator. to easily do interface to layout, the physical abstract data for silicon ensemble and apollo, called phantom cell or black box, is provided. bist(built-in self-test) circuitry is currently available for most of STD111 compiled memories. bist circuits are designed to detect a set of fault types that impact the functionality of memory and is generated by a softmacro-based bist generator. the softmacro-based bist generator generates both an individual bist netlist for each memory and a shared bist netlist for all memories used in a design. however, when several memories of the same or the different type area used in the design, if you generate the individual bist netlist for each memory, there are some redundant blocks because the individual bist netlist has same function. in this case, it would better use the shared bist netlist to eliminate such redundancy and reduce area. 1.4.3.2 compiled datapath macrocells compiled datapath macro cells include adder, barrel shifter and multiplier. adder performs the adding or adding/subtracting operation on the control of a mode selection signal. barrel shifter makes input data shift or rotate in the left/right direction. in the shift operation, the vacant bit can be padded with zero, msb value, or external data. multiplier performs the 2's compliment multiplication. one pipeline stage insertion is available to get a high operating frequency. they have two output drive strengths, which are equal to the 1x and 2x-drive in the primitive cell library. the hard macro cells are built through the apollo, placement and routing tool from avant!. all the leaf cells have the same physical configuration compatible with the primitive cell library. it allows that any primitive cell can be used as a bit slice cell in the datapath module design. we provide two kinds of engineering design services. one is to support additional compiled datapath macrocells such as alus, comparators, priority encoders, incrementers and decrementers, and so on. another is to make hardwired datapath module design which provides a regular structured layout.
1.4 product family introduction STD111 1-14 samsung asic 1.4.4 input/output cells there are about seven hundreds different i/o buffers. each i/o cell is implemented solely on the basic i/o cell architecture which forms the periphery of a chip. a test logic is provided to enable the efficient parametric (threshold voltage) testing on input buffers including lvcmos and ttl level converters, schmitt trigger input buffers, clock drivers and oscillator buffers. pull-up and pull-down resistors are optional features. three basic types of output buffers (non-inverting, tri-state and open drain) are available in a range of driving capabilities from 1ma to 12ma for 2.5v, 3.3v drive and from 1ma to 3ma for 5.0v tolerant drive. one or two levels of slew rate controls are provided for each buffer type (except 1ma, 2ma and 3ma buffers) to reduce output power/ground noise and signal ringing, especially in simultaneous switching outputs. bi-directional buffers are combinations of input buffers and output buffers (tri- state and open drain) in a single unit. the i/o structure has been fully characterized for esd protection and latch-up resistance. for user's convenience, STD111 library provides 100k w pull-down and pull-up resistance respectively. 1.4.4.1 i/o applications to support mixed voltage environments, lvttl, lvcmos and schmitt trigger i/ o cells are available at 2.5v, 3.3v interface and 5v tolerant interface. the i/o application diagram is as follows. figure 1-6. i/o applications 1.4.4.2 i/o cell drives options to provide designers with the greater flexibility, each i/o buffer can be selected among various current levels (e.g., 1ma, 2ma,..., 12ma). the choice of current- level for i/o buffers affects their propagation delay and current noise. the slew rate control helps decrease the system noise and output signal overshoot/undershoot caused by the switching of output buffers. the output edge rate can be slowed down by selecting the high slew rate control cells. 2.5v b t d 3.3v b t d 2.5 3.3 2.5v c s 3.3v c s t internal circuit operating voltage: 2.5v 2.5 3.3/ input buffer output buffer 5v tolerant
introduction 1.4 product family samsung asic 1-15 STD111 STD111 provides three different sets of output slew rate controls. only one i/o slot is required for any slew rate control options. 1.4.4.3 5v tolerant i/o buffers STD111 i/o library is based on a process which has the most optimum performance in 2.5v. in this process, voltage more than 3.6v are not allowed at the gate oxide because of a reliability problem. and a special circuit is adopted in order to make pin voltage tolerable up to 5.25v and to offer ttl interface driving up to 3ma. obviously, this circuit is constructed not to permit more than 3.6v at the gate oxide. the external circuit diagram is as follows. the maximum external tolerance of this buffer is 5.25v. it can be used as a 3.3v normal buffer. figure 1-7. 5v tolerant i/o buffers 1.4.4.4 pci buffers pci buffers are designed for pci local bus application which is an industry- standard, high-performance 32bit or 64bit bus architecture. samsung asic offers input, output, bi-directional pci buffers for 33mhz and 66mhz operation. these buffers are compliant with pci local bus speci?cation 2.1. 1.4.4.5 usb (universal serial bus) buffers various kinds of peripheral equipment such as mouse, joy stick, keyboard, modem, scanner and printer improve the power of a computer. however, it is not easy to connect and use them properly in the computer. usb speci?cation established late in 1995 is a good solution for this problem, providing facile method of an expansion. samsung asic offers full speed and low speed usb buffers that complies with universal serial bus speci?cation 1.0, 1.1. 1.4.4.6 other buffers samsung asic can support various kinds of buffers such as hstl, sstl, agp, pecl, lvds, and so on. for more information please contact us. 3.3v 3.3v 5.0v output voltage open drain output 5v tolerant input tri-state output bi-directional i/o 0.25 m m 2.5v process normal 5v process 3.3v ttl input ttl input
1.5 timings introduction STD111 1-16 samsung asic 1.5 timings 1.5.1 wire length load table 1-1. shows the equivalent standard load matrix for 4-layer and 5-layer metal interconnect. the equivalent standard load values are function of gate count and fanout. these values are based on capacitive loading and are used in wire length estimates which affect propagation delay. table 1-1. equivalent standard loads for 4-layer and 5-layer metal interconnect gates count fanouts 1 2 3 4 5 6 7 8 16 32 64 4lm 5000 0.701 1.357 2.312 3.093 3.609 4.247 4.755 6.622 17.348 27.615 48.295 10000 0.926 1.774 3.365 4.660 5.423 6.353 7.327 9.203 18.092 28.876 50.533 50000 2.536 4.990 7.526 9.980 10.165 10.879 12.722 13.798 21.501 29.252 51.190 100000 2.780 5.643 8.425 11.207 11.429 12.247 14.168 16.355 24.808 32.825 57.446 150000 7.770 10.361 12.952 13.724 14.279 14.700 15.732 17.988 24.098 38.524 77.049 200000 8.180 10.907 13.633 14.451 15.035 15.478 16.561 18.937 25.330 40.496 80.963 300000 8.998 11.998 14.997 16.087 16.697 17.161 18.343 20.955 27.994 44.696 89.297 400000 9.816 13.088 16.247 17.360 18.057 18.586 19.887 22.677 30.262 48.227 96.358 500000 10.951 14.601 18.252 19.468 20.229 20.807 22.252 25.431 32.210 51.345 102.531 600000 11.723 15.632 19.650 20.930 21.730 22.338 23.880 27.339 33.134 52.828 105.472 800000 13.507 18.010 22.834 24.270 25.165 25.847 27.615 31.704 35.807 57.110 113.982 1000000 15.174 20.232 25.809 27.392 28.376 29.127 31.104 35.779 38.289 61.088 121.885 1500000 19.743 26.325 33.911 35.904 37.138 38.085 40.643 46.899 45.765 73.055 145.688 2000000 24.024 32.032 41.504 43.880 45.352 46.480 49.581 57.320 52.758 84.249 167.954 2500000 28.030 37.374 48.611 51.347 53.036 54.338 57.946 67.072 59.291 94.706 188.751 3000000 31.775 42.367 55.254 58.326 60.221 61.682 65.764 76.187 65.385 104.459 208.150 4000000 36.455 48.606 63.391 66.915 69.090 70.765 75.450 87.407 75.013 119.844 238.804 4500000 38.642 51.522 67.194 70.930 73.235 75.011 79.978 92.651 79.513 127.034 253.132 5lm 5000 0.666 1.289 2.197 2.938 3.429 4.035 4.517 6.291 16.480 26.235 45.880 10000 0.880 1.686 3.196 4.427 5.152 6.036 6.961 8.743 17.188 27.432 48.007 50000 2.409 4.740 7.150 9.481 9.657 10.335 12.086 13.109 20.426 27.789 48.630 100000 2.642 5.361 8.004 10.647 10.857 11.634 13.555 15.537 23.568 31.184 54.574 150000 7.382 9.843 12.304 13.038 13.565 13.965 14.945 17.089 22.893 36.598 73.197 200000 7.770 10.361 12.952 13.729 14.283 14.705 15.733 17.990 24.064 38.471 76.915 300000 8.548 11.398 14.247 15.283 15.862 16.302 17.426 19.908 26.595 42.461 84.832 400000 9.326 12.433 15.434 16.492 17.155 17.656 18.892 21.543 28.749 45.816 91.512 500000 10.403 13.871 17.339 18.495 19.218 19767 21.139 24.160 30.599 48.778 97.404 600000 11.137 14.850 18.667 19.883 20.643 21.220 22.686 25.972 31.477 50.187 100.199 800000 12.832 17.110 21.692 23.056 23.908 24.555 26.235 30.119 34.016 54.255 108.284 1000000 14.415 19.220 24.519 26.022 26.957 27.670 29.549 33.990 36.375 58.034 115.790 1500000 18.756 25.009 32.216 34.109 35.282 36.181 38.611 44.554 43.477 69.403 138.404 2000000 22.823 30.431 39.429 41.687 43.084 44.156 47.102 54.454 50.120 80.036 159.556 2500000 26.629 35.505 46.180 48.779 50.385 51.621 55.049 63.718 56.326 89.971 179.313 3000000 30.186 40.249 52.491 55.410 57.211 58.598 62.476 72.377 62.115 99.237 197.743 4000000 34.633 46.176 60.221 63.569 65.635 67.227 71.678 83.036 71.262 113.852 226.863 5000000 38.832 51.777 67.527 71.279 73.597 75.382 80.372 93.108 79.907 127.662 254.382 6000000 43.542 58.057 75.716 79.926 82.525 84.525 90.121 104.403 89.598 143.146 285.238
introduction 1.5 timings samsung asic 1-17 STD111 1.5.2 timing parameters this section discusses issues involving timing parameters. 1.5.2.1 transition time figure 1-8. shows the definition of rise transition time (t r ) and fall transition time (t f ). transition time is de?ned as the delay between the time when the input (out- put) signal voltage level is 10% of supply voltage (v dd ) and the time of the input (output) signal voltage level is 90% of v dd . figure 1-8. rise and fall transition times 1.5.2.2 propagation delays figure 1-9. shows the definition of propagation delays. propagation delay is de- fined as the delay between the time when the input signal voltage level is 50% of supply voltage (v dd ) and the time when the output signal voltage level is 50% of v dd . figure 1-9. propagation delay t r t f 10% 90% 90% 10% v dd 50% 50% t plh 50% 50% t plh 50% 50% t phl 50% 50% t phl v dd in out in in out out in out
1.5 timings introduction STD111 1-18 samsung asic 1.5.2.3 setup / hold time figure 1-10. shows the definition of setup time and hold time. the setup timing check is defined as the minimum interval which a data signal must remain stable before active transition of a clock. any change to the data signal within this inter- val results in a timing violation. the hold timing check is defined as the minimum interval which a data signal must remain stable after active transition of a clock. any change to the data signal with- in this interval results in a timing violation. figure 1-10. setup and hold times 1.5.2.4 recovery times figure 1-11. shows the definition of recovery time. a recovery timing check meas- ures the time between the release of an asynchronous control signal from the ac- tive state to the next active clock edge. for example, the time between rn and the ck of fd2 cell. if the active edge of the ck occurs too soon after the release of the rn, the state of the fd2 becomes uncertain. the state can be the value set by the rn or the value clocked into the fd2 from the data input. figure 1-11. recovery time d ck t su t hd 50% 50% 50% rn ck t rc 50% 50%
introduction 1.5 timings samsung asic 1-19 STD111 1.5.2.5 removal times figure 1-12. shows the definition of removal time. a removal timing check meas- ures the time between the active clock edge and the release of an asynchronous control signal from the active state. for example, the time between rn and the ck of fd2 cell. if the release of the rn occurs too soon after the active edge of the clock, the state of the fd2 be- comes uncertain. the uncertainty can be caused by the value set by the rn or the value clocked into the fd2 from the data input. figure 1-12. removal time 1.5.2.6 minimum pulse widths figure 1-13. shows the definition of minimum pulse width. the minimum pulse width timing check is the minimum allowable time for the positive (high) or nega- tive (low) phase of each cycle. figure 1-13. minimum pulse width 1.5.2.7 minimum period figure 1-14. shows the definition of minimum period. the minimum period timing check is the minimum allowable time for one complete cycle of the signal. figure 1-14. minimum period rn ck t rm 50% 50% ck t pwh 50% t pwl ck 50% t prd
1.5 timings introduction STD111 1-20 samsung asic 1.5.3 temperature and supply voltage the next ?gure describes propagation delay derating factors (k t , k v ) as a function of on-chip junction temperature (t j ) and supply voltage (v dd ). as a result of power dissipation, the junction temperature is generally higher than the ambient temperature. the temperature of the die inside the package (junction temperature, t j ) is calculated using chip power dissipation and the thermal resistance to the ambient temperature ( q ja ) of the package. information on package thermal performance can be obtained from samsung application engineers. figure 1-15. effect of temperature and supply voltage on propagation delay temperature (t j ) k t 1.087 1.065 1.000 0.964 0.906 C40 0 70 25 85 1.144 125 ( c) supply voltage (v dd ) 1.074 0.941 2.3 2.5 (volt) k v 1.000 2.7
introduction 1.5 timings samsung asic 1-21 STD111 1.5.4 best and worst case conditions a circuit should be designed to operate properly within a given speci?cation level, either commercial or industrial. it is recommended that circuits be simulated for best case, normal case, and worst case conditions at each speci?cation level. the following expressions also allow for the effect of process variation on circuit performance. best case (worst case): t bc (t wc ) = k p x k t x k v x t nom where t bc = best case propagation delay t wc = worst case propagation delay t nom = normal propagation delay ( t j = 25 o c, v dd = 2.5v and typical process) k p , k t , k v = refer totable 1-2., table 1-3., and table 1-4. 1.5.5 derating factors of STD111 the multipliers can be applied to nominal delay data in order to estimate the effects of supply voltage, temperature and process. nominal data are provided for conditions of v dd = 2.5v, t j = 25 c and typical process. the derating factors of STD111 is as follows. table 1-2. STD111 cell process derating factor (k p ) table 1-3. STD111 cell temperature derating factor (k t ) table 1-4. STD111 cell voltage derating factor (k v ) process factor (k p ) slow typ fast 1.200 1.0 0.849 temp. ( o c) 125 85 70 25 0 C40 k t 1.144 1.087 1.065 1.000 0.964 0.906 voltage (v) 2.3 2.5 2.7 k v 1.074 1.000 0.941
1.6 delay model introduction STD111 1-22 samsung asic 1.6 delay model the asic timing characteristics consist of the following components: ? cell propagation delay from input to output transitions based on input waveform slope, fanout loads and distributed interconnection wire resistance and capacitance. ? interconnection wire delay across the metal lines. ? timing requirement parameters such as setup time, hold time, recovery time, skew time, minimum pulse width, etc. ? derating factors for junction temperature, power supply voltage, and process variations. timing model for STD111 focuses on how to characterize cell propagation delay time accurately. to accomplish this goal, 2-dimensional table look-up delay model has been adopted. the index variables of this table are input waveform slope and output load capacitance. see the ?gure below. samsung asic design automation system supports an n-dimensional table model even though we adopted 2-dimensional model for our 0.25 m m cell-based products. figure 1-16. 2-dimensional table delay model propagation delay [ns] input waveform slope [ns] load cap [pf] 1.5 1.0 0.5 1.0 2.0 3.0 0.4 0.8 1.2
introduction 1.6 delay model samsung asic 1-23 STD111 the table 1-5. shows an example of this model for 2-input nand cell. the data in this table are high-to-low transition delay times from one of the two input pins to output pin. the number of points and values of the index variables can differ for each cell. table 1-5. table delay model example notice that 5-by-6 table is used. delay values between grid points and beyond this table are determined by linear interpolation and extrapolation methods. this general table delay model provides great ?exibility as well as high accuracy since extensive software revisions are not required when a cell library is updated. the other timing components such as interconnection wire delay, timing requirement parameters and derating factors are characterized in a commonly-accepted way in industry. the ?gure below summarizes the features of samsung asics delay model. 2-dimensional table delay model for output loading and input waveform slope effects is used.the slopes (t r , t f ) and delay times (t plh , t phl ) of all cell instances are calculated recursively. the input waveform slope of each primary input pad and the loading capacitance of each primary output pad can be assigned individually or by default. a pin to pin delays of cells and interconnection wires are supported. ? the effect of distributed interconnection wire resistance and capacitance on cell delay is analysed using the effective capacitance concept. figure 1-17. features of delay model slope \ cap 0.010 0.042 0.106 0.233 0.424 0.678 0.020 0.04146 0.08814 0.18023 0.36303 0.63784 1.00330 0.198 0.06338 0.11782 0.20862 0.39030 0.66461 1.02980 0.415 0.07617 0.14488 0.24869 0.42763 0.70005 1.06410 0.849 0.08747 0.17724 0.30697 0.50902 0.77668 1.13720 1.500 0.09268 0.20337 0.36332 0.60379 0.90022 1.25490 s1 s3 s2 co1 co2 co3 ck q d a_y b_y ? ? a
1.7 testability design methodology introduction STD111 1-24 samsung asic 1.7 testability design methodology 1.7.1 scan design ? multiplexed scan ?ip-?op that minimizes the area or delay overhead needed to implement scan design. ? automated design rules checking, scan insertion, and test pattern generation ? high fault coverage on synchronous designs 1.7.2 boundary-scan ? ieee std 1149.1 ? jtag boundary-scan registers with primitive cells ? boundary-scan description language (bsdl) description for board testing ? combination with internal scan design and core testing boundary scan architecture a boundary scan architecture contains tap (test access port), tap controller, instruction register and a group of test data registers. the instruction and test data registers are separate shift-register-based paths connected in parallel with a common serial data input and a common serial data output which are connected to tap, tdi and tdo signals. tap controller selects the alternative instruction and test data register paths between tdi and tdo. the schematic view of the top level design of the test logic architecture is shown in the figure 1- 18. figure 1-18. jtag test access port (tap) block diagram multiplexer scannable register device identity register bypass register instruction register ta p controller system logic boundary scan path tdi tms tck tdo test access port (tap) mux
introduction 1.7 testability design methodology samsung asic 1-25 STD111 boundary scan functional block descriptions tap (test access port) tap is a general-purpose port that can provide with an access to many test support functions built into a component, including the test logic. it includes three inputs (tck; test clock signal, tms; test mode signal and tdi; test data input) and one output (tdo; test data output) required by the test logic. an optional fourth input (trstn; test reset) is provided for the asynchronous initialization of the test logic. the values applied at tms and tdi pins are sampled on the rising edge of tck, and the value placed on tdo pin changes on the falling edge of tck. tap controller tap controller receives tck, interprets the signals on tms, and generates clock and control signals for both instruction and test data registers and for other parts of the test circuitries as required. instruction register/instruction decoder test instructions are shifted into and held by the instruction register. test instructions include a selection of tests to be performed or the test data register to be accessed. a basic 3-bit instruction register and its instruction decoder are provided as macrofunctions in the library. test data registers data registers include a bypass register, a boundary scan register, a device identi?cation register and other design speci?c registers. only the bypass- and boundary scan registers are mandatory; the rest are optional. bypass register: the bypass register provides a single-bit serial connection through the circuit when none of the other test data registers is selected. it can be used to allow test data to ?ow through a given device to the other components in a product without affecting a normal operation. boundary scan register: the boundary scan register detects typical production defects in board interconnects, such as opens, shorts, etc. it also allows an access to component inputs and outputs when you test their logic or sample ?ow-through signals. special boundary scan register macrocells are provided for this purpose. these special registers is discussed in the next section of next pages. design-speci?c test data register: these optional registers may be provided to allow an access to design-speci?c test support features in the integrated circuit, such as self-test, scan test. device identi?cation register: this is an optional test data register that allows the manufacturer part number and variant of a components to be identi?ed. the 32-bit identi?cation register is partitioned into four ?elds: device version identi?er1st ?eld the ?rst four bits beginning from msb device part number 2nd ?eld 16 bits manufacturers jedec number 3rd ?eld 11 bits lsb 4th ?eld 1 bit tied in high
1.7 testability design methodology introduction STD111 1-26 samsung asic the asic designer is free to ?ll the version and part number in any manner as long as the total twenty bits are used. samsungs jedec code: 78 decimal = 1001110 continuation ?eld (4 bits) = 0000 contents of device identi?cation register: xxxx xxxxxxxxxxxxxxxx 0000 1001110 1 users can de?ne these two ?elds. 1.7.3 bist (built-in self-test) ? ef?cient test solution for compiled memory macrocells ? at speed and parallel testing of multiple memories ? less routing overhead and test pin requirements instruction register tap controller bypass register mux circuit prior to boundary scan (core logic) boundary scan register (connection of all boundary scan cells) boundary scan path i/o pad tdi tms tck tdo test access port (tap) test data register
introduction 1.8 maximum fanouts samsung asic 1-27 STD111 1.8 maximum fanouts 1.8.1 internal macrocells the maximum fanouts for STD111 primitive cells are as follows. note that these fanout limitation values are calculated when the rise and fall times of the input signal is 0.198ns. depending on the rise and fall times, the maximum fanout limitations can be varied case by case. in the following table the maximum fanout values for all pins of STD111 internal macrocells are listed. table 1-6. maximum fanouts of internal macrocells (when input t r /t f = 0.198ns, one fanout (sl) = 0.01109pf ) cell name output pin maximum fanouts ad2 y 51 ad2d2 y 104 ad2d4 y 206 ad2dh y 24 ad3 y 52 ad3d2 y 103 ad3d4 y 207 ad3dh y 24 ad4 y 51 ad4d2 y 103 ad4d4 y 201 ad4dh y 24 ad5 y 25 ad5d2 y 51 ad5d4 y 207 ao21 y 24 ao211 y 15 ao2111 y 10 ao2111d2 y 103 ao211d2 y 30 ao211d2b y 103 ao211d4 y 207 ao211dh y 7 ao21d2 y 48 ao21d2b y 102 ao21d4 y 206 ao21dh y 11 ao22 y 23 ao221 y 14 ao221d2 y 103 ao221d4 y 207 ao222 y 13 ao2222 y 8 ao2222d2 y 103 ao2222d4 y 208 ao222a y 22 ao222d2 y 28 ao222d2a y 102 ao222d2b y 102 ao222d4 y 206 ao222d4a y 206 ao22a y 23 ao22d2 y 47 ao22d2a y 47 ao22d2b y 102 ao22d4 y 206 ao22d4a y 206 ao22dh y 11 ao22dha y 11 ao31 y 22 ao311 y 14 ao3111 y 9 ao3111d2 y 103 ao311d2 y 103 ao311d4 y 207 ao31d2 y 46 ao31d4 y 206 ao31dh y 10 ao32 y 17 ao321 y 13 ao321d2 y 103 ao321d4 y 207 ao322 y 12 ao322d2 y 103 ao322d4 y 207 ao32d2 y 102 ao32d4 y 206 ao33 y 16 ao331 y 12 ao331d2 y 103 ao331d4 y 207 ao332 y 11 ao332d2 y 102 ao332d4 y 207 ao33d2 y 102 ao33d4 y 206 ao4111 y 8 ao4111d2 y 103 busholder y 10000 dc4 y0 51 y1 51 y2 51 y3 51 dc4i yn0 41 yn1 41 yn2 41 yn3 41 dc8i yn0 29 yn1 29 yn2 29 yn3 29 yn4 29 yn5 29 yn6 29 yn7 29 dl1d2 y 104 dl1d4 y 210 dl2d2 y 104 dl2d4 y 211 dl3d2 y 104 dl3d4 y 211 dl4d2 y 104 dl4d4 y 211 dl5d2 y 103 dl5d4 y 209 dl10d2 y 103 dl10d4 y 209 cell name output pin maximum fanouts
1.8 maximum fanouts introduction STD111 1-28 samsung asic oak_duclk 10 ck 222 ckb 222 oak_duclk 16 ck 223 ckb 223 fa s 52 co 51 fad2 s 103 co 103 fadh s 24 co 23 fd1 q 51 qn 51 fd1d2 q 102 qn 102 fd1cs q 51 qn 51 fd1csd2 q 102 qn 102 fd1q q 51 fd1qd2 q 102 fd1s q 51 qn 51 fd1sd2 q 102 qn 102 fd1sq q 51 fd1sqd2 q 103 fd2 q 51 qn 51 fd2d2 q 104 qn 103 fd2cs q 51 qn 49 fd2csd2 q 103 qn 100 fd2q q 51 fd2qd2 q 103 fd2s q 51 qn 51 fd2sd2 q 104 qn 103 fd2sq q 51 fd2sqd2 q 103 fd3 q 51 qn 51 fd3d2 q 103 qn 103 fd3cs q 51 qn 51 fd3csd2 q 102 qn 102 fd3q q 51 fd3qd2 q 102 fd3s q 51 qn 51 fd3sd2 q 103 qn 102 fd3sq q 51 fd3sqd2 q 103 fd4 q 51 qn 50 fd4d2 q 103 qn 102 fd4cs q 51 qn 49 cell name output pin maximum fanouts fd4csd2 q 103 qn 99 fd4q q 51 fd4qd2 q 103 fd4s q 51 qn 50 fd4sd2 q 103 qn 102 fd4sq q 51 fd4sqd2 q 103 fd5 q 51 qn 51 fd5d2 q 102 qn 102 fd5s q 51 qn 51 fd5sd2 q 102 qn 102 fd6 q 51 qn 51 fd6d2 q 104 qn 103 fd6s q 51 qn 51 fd6sd2 q 104 qn 103 fd7 q 51 qn 51 fd7d2 q 103 qn 103 fd7s q 51 qn 51 fd7sd2 q 103 qn 102 fd8 q 51 qn 50 fd8d2 q 103 qn 102 fd8s q 51 qn 50 fd8sd2 q 103 qn 102 fds2 q 51 qn 51 fds2d2 q 102 qn 102 fds2cs q 51 qn 51 fds2csd2 q 103 qn 102 fds2s q 51 qn 51 fds2sd2 q 102 qn 102 fds3 q 51 qn 51 fds3d2 q 102 qn 102 fds3cs q 51 qn 51 fds3csd2 q 102 qn 102 fds3s q 51 qn 51 cell name output pin maximum fanouts
introduction 1.8 maximum fanouts samsung asic 1-29 STD111 fds3sd2 q 102 qn 102 fj1 q 51 qn 51 fj1d2 q 103 qn 103 fj1s q 51 qn 51 fj1sd2 q 103 qn 102 fj2 q 51 qn 51 fj2d2 q 103 qn 103 fj2s q 51 qn 51 fj2sd2 q 103 qn 102 fj4 q 51 qn 51 fj4d2 q 102 qn 103 fj4s q 51 qn 50 fj4sd2 q 103 qn 102 ft2 q 51 qn 51 ft2d2 q 103 qn 103 ha s 51 co 51 had2 s 104 co 103 hadh s 24 co 23 iv y 52 ivcd11 y 48 yn 49 ivcd13 y 45 yn 147 ivcd22 y 97 yn 99 ivcd26 y 90 yn 295 ivcd44 y 194 yn 199 ivd2 y 105 ivd3 y 156 ivd4 y 211 ivd6 y 308 ivd8 y 414 ivd16 y 853 ivdh y 23 ivt y 48 ivtd2 y 101 ivtd4 y 203 ivtd8 y 407 ivtd16 y 824 ivtn y 48 ivtnd2 y 101 ivtnd4 y 203 ivtnd8 y 407 ivtnd16 y 824 cell name output pin maximum fanouts ld1 q 51 qn 51 ld1d2 q 102 qn 102 ld1a q 40 ld1d2a q 84 ld1q q 51 ld1qd2 q 102 ld2 q 51 qn 51 ld2d2 q 103 qn 103 ld2q q 51 ld2qd2 q 102 ld3 q 51 qn 51 ld3d2 q 103 qn 103 ld4 q 51 qn 51 ld4d2 q 104 qn 103 ld5 q 51 qn 51 ld5d2 q 102 qn 102 ld5q q 51 ld5qd2 q 102 ld6 q 51 qn 51 ld6d2 q 103 qn 103 ld6q q 51 ld6qd2 q 102 ld7 q 51 qn 51 ld7d2 q 103 qn 103 ld8 q 51 qn 51 ld8d2 q 104 qn 103 oak_ldi2 q 51 qn 51 oak_ldi2d2 q 102 qn 102 oak_ldi3 q 51 qn 51 oak_ldi3d2 q 104 qn 103 ls0 q 42 qn 42 ls0d2 q 83 qn 83 ls1 q 26 qn 26 ls1d2 q 102 qn 103 mx2 y 51 mx2d2 y 103 mx2d4 y 204 mx2dh y 24 mx2i yn 24 mx2ia yn 23 mx2id2 yn 103 cell name output pin maximum fanouts
1.8 maximum fanouts introduction STD111 1-30 samsung asic mx2id2a yn 103 mx2id4 yn 206 mx2id4a yn 207 mx2idh yn 11 mx2idha yn 11 mx2ix4 yn0 24 yn1 24 yn2 24 yn3 24 mx2x4 y0 51 y1 51 y2 51 y3 51 mx3i yn 51 mx3id2 yn 103 mx3id4 yn 207 mx4 y 51 mx4d2 y 102 mx4d4 y 197 mx8 y 50 mx8d2 y 99 mx8d4 y 186 nd2 y 41 nd2d2 y 83 nd2d4 y 168 nd2dh y 19 nd3 y 29 nd3d2 y 60 nd3d4 y 120 nd3dh y 13 nd4 y 22 nd4d2 y 45 nd4d2b y 103 nd4d4 y 206 nd4dh y 10 nd5 y 51 nd5d2 y 102 nd5d4 y 206 nd6 y 51 nd6d2 y 102 nd6d4 y 206 nd8 y 51 nd8d2 y 102 nd8d4 y 206 nid y 50 oak_nid10p y 1451 nid16 y 790 nid2 y 97 oak_nid20p y 2883 nid3 y 146 nid4 y 196 nid6 y 290 nid8 y 387 nidh y 24 nit y 48 nitd16 y 825 nitd2 y 101 nitd4 y 202 nitd8 y 407 nitn y 48 nitnd16 y 825 nitnd2 y 101 nitnd4 y 202 nitnd8 y 407 nr2 y 25 cell name output pin maximum fanouts nr2a y 52 nr2d2 y 51 nr2d2b y 102 nr2d4 y 206 nr2dh y 12 nr3 y 16 nr3a y 33 nr3d2 y 33 nr3d2b y 102 nr3d4 y 206 nr3dh y 7 nr4 y 51 nr4d2 y 103 nr4d4 y 206 nr4dh y 23 nr5 y 51 nr5d2 y 103 nr5d4 y 208 nr6 y 51 nr6d2 y 103 nr6d4 y 208 nr8 y 51 nr8d2 y 102 nr8d4 y 204 oa21 y 25 oa211 y 24 oa2111 y 20 oa2111d2 y 102 oa211d2 y 49 oa211d2b y 103 oa211d4 y 206 oa211dh y 11 oa21d2 y 51 oa21d2b y 102 oa21d4 y 206 oa21dh y 11 oa22 y 23 oa221 y 22 oa221d2 y 103 oa221d4 y 206 oa222 y 17 oa2222 y 13 oa2222d2 y 102 oa2222d4 y 207 oa222d2 y 34 oa222d2b y 103 oa222d4 y 207 oa22a y 25 oa22d2 y 47 oa22d2a y 50 oa22d2b y 103 oa22d4 y 206 oa22d4a y 207 oa22dh y 11 oa22dha y 11 oa31 y 16 oa311 y 15 oa3111 y 15 oa3111d2 y 102 oa311d2 y 102 oa311d4 y 206 oa31d2 y 32 oa31d4 y 206 oa31dh y 7 oa32 y 15 cell name output pin maximum fanouts
introduction 1.8 maximum fanouts samsung asic 1-31 STD111 1.8.2 i/o cells the maximum fanouts for i/o cells are as follows. table 1-7. maximum fanouts of i/o cells (t r /t f = 0.198ns, one fanout (sl) = 0.01109pf) oa321 y 14 oa321d2 y 103 oa321d4 y 206 oa322 y 12 oa322d2 y 103 oa322d4 y 207 oa32d2 y 103 oa32d4 y 206 oa33 y 13 oa331 y 13 oa331d2 y 102 oa331d4 y 206 oa332 y 9 oa332d2 y 102 oa332d4 y 207 oa33d2 y 103 oa33d4 y 207 oa4111 y 10 oa4111d2 y 102 or2 y 51 or2d2 y 103 or2d4 y 208 or2dh y 23 or3 y 51 or3d2 y 103 or3d4 y 206 or3dh y 23 or4 y 41 or4d2 y 83 or4d4 y 206 or4dh y 19 or5 y 41 or5d2 y 83 or5d4 y 206 scg1 y 29 scg1d2 y 59 scg2 y 51 scg2d2 y 104 scg3 y 29 scg3d2 y 59 scg4 y 41 scg4d2 y 83 scg5 y 51 scg5d2 y 102 scg6 y 51 scg6d2 y 102 scg7 y 41 scg7d2 y 83 scg8 y 51 scg8d2 y 103 scg9 y 51 scg9d2 y 102 scg10 y 51 scg10d2 y 102 scg11 y 16 scg11d2 y 32 scg12 y 25 scg12d2 y 51 scg13 y 42 scg13d2 y 84 scg14 y 41 scg14d2 y 83 scg15 y 29 scg15d2 y 59 scg16 y 24 cell name output pin maximum fanouts scg16d2 y 49 scg17 y 41 scg17d2 y 83 scg18 y 29 scg18d2 y 59 scg19 y 24 scg19d2 y 48 scg20 y 25 scg20d2 y 51 scg21 y 16 scg21d2 y 33 scg22 y 24 scg22d2 y 49 scg23 s 51 co 51 scg23d2 s 103 co 103 xn2 y 52 xn2d2 y 103 xn2d4 y 205 xn3 y 50 xn3d2 y 100 xn3d4 y 194 xo2 y 52 xo2d2 y 103 xo2d4 y 205 xo3 y 50 xo3d2 y 100 xo3d4 y 194 cell name output pin maximum fanouts phic y 163 phicd y 163 phicu y 163 phis y 163 phisd y 163 phisu y 163 phit y 163 phitd y 163 phitu y 163 phsosck1 yn 115 phsosck17 yn 116 phsosck2 yn 117 phsosck27 yn 117 phsoscm1 yn 117 phsoscm16 yn 117 phsoscm2 yn 124 phsoscm26 yn 124 phsoscm3 yn 243 phsoscm36 yn 243 pic y 79 pic_abb y 79 picc_abb y 81 picd y 79 cell name output pin maximum fanouts
1.8 maximum fanouts introduction STD111 1-32 samsung asic picen_abb y 78 picu y 79 pis y 78 pisd y 78 pisu y 78 psosck1 yn 117 psosck2 yn 117 psoscm1 yn 43 psoscm2 yn 152 ptic y 163 pticd y 163 pticu y 163 ptis y 163 ptisd y 163 ptisu y 163 ptit y 163 ptitd y 163 ptitu y 163 cell name output pin maximum fanouts
introduction 1.8 maximum fanouts samsung asic 1-33 STD111 1.8.3 ck cell max fanout STD111 maximum fanout for ck cells ? vdd = 2.5v ? fanout = 0.00813pf (= input cap for ck pin of fd1) ? standard load (sl) = 0.01109pf ? input slope = 0.198ns ? max output transition time (mott) = 1.5ns ? maximum frequency 200mhz ? net length ( m m/fanout): branch net length for each fanout except trunk table 1-8. maximum fanout for ck cells table 1-9. maximum fanout for nid cells for high fanout nets including clock net, samsung strongly recommends using clock tree synthesis. trunk width ( m m) 8 in case that interconnection is not considered net length ( m m/fanout) 20 200 trunk length ( m m) 5000 10000 5000 10000 ck2 87 1 27 237 ck4 251 151 79 48 472 ck6 408 286 128 90 709 ck8 555 403 175 127 944 trunk width ( m m) 0.44 8 in case that interconnection is not considered net length ( m m/fanout) 20 200 trunk length ( m m) 5000 10000 5000 10000 nid 50 nid2 15 97 nid3 34 6 146 nid4 48 17 196 nid6 67 38 10 290 nid8 79 59 29 387 nid16 102 137 97 790 oak_nid10p 114 246 172 1451 oak_nid20p 123 420 267 2883
1.9 package capability by lead count introduction STD111 1-34 samsung asic 1.9 package capability by lead count package lead inductance lead count sop/ssop (small outline package) 8 16 20 2428445670 3.9 x 8.7mm < 2nh n 3.9 x 9.9 mm < 4nh n 4.0 x 5.1mm < 2nh n 4.4 x 6.9 mm < 3nh n 4.4 x 6.9 mm < 3nh n 5.3 x 3.0 mm < 3nh n 5.3 x 7.2 mm < 3nh n 5.3 x 10.2 mm < 4nh n 5.3 x 15.6 mm < 5nh n 5.4 x 14.1 mm < 5nh n 7.5 x 18.4 mm < 8nh n 12.6 x 29.0mm < 20nh n 12.7 x 29.0 mm < 16nh n tsop/tssop (thin sop) 8 28 32 4448545666 4.4 x 3.0mm < 3nh n 4.4 x 9.7 mm < 3nh n 6.1 x 9.7mm < 3nh n 6.1 x 14.0 mm < 6nh n 10.2 x 18.9 mm < 8nh n 10.2 x 21.4 mm < 7nh n 10.2 x 22.6 mm < 7nh nn n 12.0 x 20.0mm < 6nh n 12.4 x 16.4 mm < 7nh n psop/pssop (power sop) 81620 3.9 x 9.9 mm < 3nh n 6.1 x 7.64 mm < 3nh n 7.6 x 12.8 mm < 3nh n 11.0 x 15.9 mm < 6nh n
introduction 1.9 package capability by lead count samsung asic 1-35 STD111 package lead inductance lead count qfp (quad flat package) 44 48 64 80 100 128 160 208 240 256 7 x 7 mm < 3nh n 10 x 10 mm < 5nh nn 12 x 12 mm < 5nh n 14 x 14 mm < 6nh nn 14 x 20 mm < 12nh nnnn 24 x 24 mm < 11nh n 28 x 28 mm < 17nh nn n 32 x 32 mm < 15nh n tqfp (thin quad flat package) 32 48 80 100 144 160 176 208 7 x 7 mm < 4nh nn 12 x 12 mm < 5nh n 14 x 14 mm < 5nh n 14 x 20 mm < 10nh n 20 x 20 mm < 9nh n 24 x 24 mm < 11nh nn 28 x 28 mm < 13nh n plcc (plastic leaded chip carrier) 44 84 16.6 x 16.5mm <5nh n 29.3 x 29.3 mm < 13nh n package lead inductance lead count sbga (super bga) lp/g lsig 256 304 352 432 560 600 27 x 27 mm < 3nh < 7nh n 31 x 31 mm < 3nh < 8nh n 35 x 35 mm < 3nh < 8nh n 40 x 40 mm < 3nh < 9nh n 42.5 x 42.5 mm < 3nh < 9nh n 45 x 45 mm < 3nh < 9nh n pbga (plastic bga) lp/g lsig 119 121 169 204 208 217 225 249 256 272 300 14 x 22 mm < 4nh <9nh n 15 x 15 mm < 4nh < 13nh n 23 x 23 mm < 4nh < 18nh n nnn n 27 x 27 mm < 4nh < 21nh n nnn 31 x 31 mm < 4nh < 13nh 35 x 35 mm < 4nh < 14nh pbga (plastic bga) lp/g lsig 304 316 324 329 352 360 385 388 420 456 14 x 22 mm < 4nh <10nh 15 x 15 mm < 4nh < 13nh 23 x 23 mm < 4nh < 18nh 27 x 27 mm < 4nh < 21nh nn 31 x 31 mm < 4nh < 13nh nnnn 35 x 35 mm < 4nh < 14nh nnnn
1.10 power dissipation introduction STD111 1-36 samsung asic 1.10 power dissipation 1.10.1 estimation of power dissipation in cmos circuit cmos circuits have been traditionally considered to consume low power since they draw very small amount of current in a steady state. however, the recent revolution in a cmos technology that allows very high gate density has changed the way the power dissipation should be understood. the power dissipation in a cmos circuit is affected by various factors such as the number of gates, the switching frequency, the loading on the output of a gate, and so on. power dissipation is important when designers decide the amount of necessary power supply current for the device to operate in safety. propagation delays and reliability of the device also depend on power dissipation that determines the temperature at which the die operates. to obtain high speed and reliability, designers must estimate power dissipation of the device accurately and determine the appropriate environments including the package and system cooling methods. this section describes the concepts of two types of power dissipation (static and dynamic) in a cmos circuit, the method of calculating those in the samsung STD111 library. 1.10.2 static (dc) power dissipation there are two types of static or dc current contributing to the total static power dissipation in cmos circuits. one is the leakage current of the gates resulted by a reverse bias between a well and a substrate region. there is no dc current path from power to ground in a cmos because one of the transistor pair is always off, therefore, no static current except the leakage current ?ows through the internal gates of the device. the amount of this leakage current is, however, in the range of tens of nano amperes, which is negligible. the other is dc current that ?ows through the input and output buffers when the circuit is interfaced with other devices, especially ttl. the current of pull-up/ pull-down transistor in the input buffers is about 33 m a (at 3.3v) and 25 m a (at 2.5v) typically, which is also negligible. therefore, only dc current that the output buffers source or sink has to be counted to estimate the total static power dissipation. dc power dissipation of output and bi-directional buffers is determined by the following formula: where, n = number of output and bidirectional buffers t = total operation time in output mode t h = the sum of logic high state time t l = the sum of logic low state time t l + t h = t (supposed that all output and bidirectional buffers have just logic high or low state) sout is the output mode ratio of bidirectional buffers (typically 0.5) p dc_output [mw] v ol k () i ol k () t lk () () k1 = n ? v dd v oh k () C () i oh k () t hk () () k1 = n ? + ? ? ?? t = p dc_bi [mw] v ol k () i ol k () t lk () () k1 = n ? v dd v oh k () C () i oh k () t hk () () k1 = n ? + ? ? ?? s out t =
introduction 1.10 power dissipation samsung asic 1-37 STD111 1.10.3 dynamic (ac) power dissipation when a cmos gate changes its state, it draws switching current as a result of charging or discharging a load capacitance, c l . the energy associated with the switching current for a node capacitance, c l , is where v dd is the power supply voltage. in addition to the power dissipated by the load capacitance, cmos circuits consume power due to the short- circuit current ?owing through a temporary v dd -to-ground path during switching. the dynamic power dissipation for an entire chip is much more complicated to estimate since it depends on the degree of switching activity of the circuit. samsung has found that the degree of switching activity is 10% on the average and recommends this number to be used in estimating the total dynamic power dissipation. 1.10.4 power dissipation in STD111 this section describes the equations on how to estimate the power dissipation in STD111. as explained in the previous section, the total power dissipation (p total ) consists of static power dissipation (p dc ) and dynamic power dissipation (p ac ). p total = p ac + p dc p dc is negligible in case of cmos logic. the dynamic power dissipation is caused by three components: input buffers (p ac_input ), output buffers (p ac_output ), bidirectional buffers (p ac_bi ), and internal cells (p ac_internal ). p ac = p ac_ input + p ac_output + p ac_bi + p ac_internal each term mentioned above is characterized by the following equations: c l v dd 2 p ac_input [mw] 2.5 i j_eq_p f j 100 --------- - s j ? ?? 3.3 + j n_2.5v_input ? i k_eq_p f k 100 --------- - s k ? ?? 6.25 + k n_3.3v_input ? 0.001 s i f i c i_inload () i n_total_input ? = p ac_output [mw] 2.5 i i_eq_p f i 100 --------- - s i ? ?? 3.3 + i n_2.5v_output ? i j_eq_p f j 100 --------- - s j ? ?? j n_3.3v_output ? + = 6.25 0.001 s i f i c i_outload () 10.89 0.001 s j f j c j_outload () j n_3.3v_output ? + i n_2.5v_output ? p ac_bi [mw] p ac_bi_input 1s out C () p ac_bi_output s out + = p ac_bi_input [mw] 2.5 i j_eq_p f j 100 --------- - s j ? ?? j n_2.5v_bi ? 3.3 i k_eq_p f k 100 --------- - s k ? ?? 6.25 + k n_3.3v_bi ? 0.001 s i f i c i_inload () i n_total_bi ? + = p ac_bi_output [mw] 2.5 i i_eq_p f i 100 --------- - s i ? ?? i n_2.5v_bi ? 3.3 i j_eq_p f j 100 --------- - s j ? ?? + j n_3.3v_bi ? + = 6.25 0.001 s i f i c i_outload () i n_2.5v_bi ? 10.89 0.001 s i f i c i_outload () j n_3.3v_bi ? + p ac_internal [mw] 0.001 0.3018 s 0.0331 + () g f 0.001 p i f i () j n_macro ? + =
1.10 power dissipation introduction STD111 1-38 samsung asic where n_2.5v_input is the number of 2.5v interface input buffers used n_3.3v input is the number of 3.3v interface input buffers used, n_total_input = n_2.5v_input + n_3.3v input n_2.5v_output is the number of 2.5v interface output buffers used, n_3.3v_output is the number of 3.3v interface output buffers used, n_2.5v_bi is the number of 2.5v interface bidirectional buffers used, n_3.3v_bi is the number of 3.3v interface bidirectional buffer used, n_macro is the number of macro cells used, g is the size of the design in gate count, f is the operating frequency in mhz, s is the estimated degree of switching activity (typically 0.1 for internal and 0.5 for i/o), sout is the output mode ratio of bidirectional buffers (typically 0.5), c is the load capacitance in pf. p is the characterized power for the i-th hard macro block ( m w/mhz) 1.10.5 temperature and power dissipation the total power dissipation, p total can be used to ?nd out the device temperature by the following equation: q ja = (t j C t a ) / p total where q ja is the thermal impedance, t j is the junction temperature of the device, t a is the ambient temperature. thermal impedances of the samsung packages are given in the following table. the junction temperature, obtained by multiplying p total by the appropriate q ja and adding t a , determines the derating factor for the propagation delays and also indicates the reliability measures. hence, designers can achieve the desired derating factor and reliability targets by choosing appropriate packages and system cooling methods. table 1-10. thermal impedances of samsung plastic packages sop/tsop pin number 20 24 28 32 44 50 54 62 66 q ja [ c/w] 63 58 41-44 46-56 44-71 39-59 34-56 27-33 34-46 qfp pin number 44 48 80 100 120 128 160 208 240 256 q ja [ c/w] 51-62 43-56 43-74 27-61 33-47 43-51 29-51 22-43 28-47 29-42 tqfp/lqfp pin number 32 64 100 144 160 176 208 256 q ja [ c/w] 68-70 47 37-70 38 35-62 31-34 37-56 30-42 pbga pin number 272 388 356 (tepbga) 452 (tepbga) q ja [ c/w] 19-22 16-19 16 14 sbga pin number 256 304 352 432 600 q ja [ c/w] 14.1 13.1 11.7 10.2 8.3
introduction 1.11 vdd/vss rules and guidelines samsung asic 1-39 STD111 1.11 v dd /v ss rules and guidelines there are three kinds of vdd and vss in STD111, providing power to internal and i/o area. ? core logic C vdd2i, vss2i ? pre-driver (i/o area) C vdd2p, vdd3p, vss2p, vss3p ? output-drive (i/o area) C vdd2o, vdd3o, vss2o, vss3o the number of vdd and vss pads required for a speci?c design depends on the following factors: ? number of input and output buffers ? number of simultaneous switching outputs ? number of used gates and simultaneous switching gates ? operating frequency 1.11.1 basic placement guidelines the purpose of these guidelines is to minimize ir drop and noise for reliable device operations. ? core logic and pre-driver v dd /v ss pads should be evenly distributed on all sides of the chip. ? if you have core block demanding high power (compiled memory, analog), extra power pads should be placed on that side. ? power pads for sso group should be evenly distributed in the sso group. ? do not place the quiet signal (analog, reference) or analog power (vdda/ vssa) or bi-directional buffer next to a sso group. ? the opposite types of power pads (v dd /v ss ) should be placed as close as possible. ? if it is possible, do not place power pads (v dd /v ss ) at the corner of the chip. 1.11.2 vdd2i/vss2i allocation guidelines the purpose of these guidelines is to ensure that the minimum number of core logic power pad pairs meeting the electromigration current limit are used. the number of vdd2i/vss2i pads required for a speci?c design is determined by the function of the operating frequency of a chip. ? vdd2i bus width and the number of pads are equal to those of vss2i ? vdd2i/vss2i buses and pads should be distributed evenly in the core and on each side of the chip. ? the total number of core logic vdd2i pads is equal to that of vss2i pads.
1.11 vdd/vss rules and guidelines introduction STD111 1-40 samsung asic the number of vdd2i/vss2i pad pairs required for a design can be calculated from the following expression: the number of vdd2i/vss2i pad pairs = where, g = the core (excluding hard macro blocks) size in the gate counts s = the switching ratio (typically = 0.1) f = operating frequency (mhz) pi = characterized current for the i-th hard macro block (ma/mhz) fi = operating frequency for the i-th hard macro block (mhz) i em = current limit per vdd/vss pad pairs based on electromigration rule (80ma) for reliable device operation and minimize ir voltage drop, minimum number of vdd2i/vss2i power pad pairs is 4. extra power may be needed for the demanding high power macro blocks (sram, analog block...). 1.11.3 vdd2p/vss2p (vdd3p/vss3p) allocation guidelines. these guidelines ensure that an adequate input threshold voltage margin is maintained during a switching. the number of vdd2p/vss2p (vdd3p/vss3p) pads required for a design can be calculated from the following expression: in above expression, i eq_p = ? (average current of input/output buffers and bi-direction pre-drivers at maximum operational i/o frequency) [ma] (refer table 1-11) table 1-11. 2.5v interface input buffer type cmos cmos schmitt ieq_p (ma) 0.35 0.36 output pre-driver type driver tristate b1C4 b6C8 b10C12 t1C4 t6C8 t10C12 ieq_p (ma) normal 0.14 0.27 0.41 0.24 0.36 0.53 slew rate 0.14 0.25 0.35 0.25 0.35 0.45 0.001 0.1207 s 0.0133 + () gf pi fi () i n_macro ? + l em round up C number_ of_vdd2p/vss2p(vdd3p/vss3p) pairs l eq_p l em ---------- - round up C = where n_input is the number of input buffers used, n_output is the number of output buffers used, n_bi is the number of bi-directional buffers used, f is the operating frequency in mhz, s out is the output mode ratio of bi-directional buffers (typically 0.5), i em = current limit per vdd/vss pad pairs based on electromigration rule. (80ma) i eq_p i eq_p_in f i 100 --------- - ? ?? i n_input ? i j_eq_p_out f j 100 --------- - ? ?? j n_output ? i k_eq_p_in f k 100 --------- - ? ?? 1s out C () k n_bi ? i k_eq_p_out f k 100 --------- - ? ?? s out ++ + =
introduction 1.11 vdd/vss rules and guidelines samsung asic 1-41 STD111 table 1-12. 3.3v interface for reliable device operation and minimum ir voltage drop, at least 4 pairs of vdd2p/vss2p (vdd3p/vss3p) power pads are needed. 1.11.4 vdd2o/vss2o (vdd3o/vss3o) allocation guide sso (simultaneous switching output) current induced in power and ground inductance can cause system failure because of voltage fluctuations. for the calculation of output drive power pad numbers, we consider the sso noise as well as the current limit based on electromigration. we may define the sso as outputs switching simultaneously in 1ns windows, such as bus type buffers. note: in case of heavy load, high frequency and low package inductance, the number of power pads for sso block could be determined by electromigration rule rather than limit of sso noise. so the number of power pads for sso block should be determined as the worse one of the power pad number under the limit of sso noise and that under the limit of electromigration rule. 1) number of power pads for sso block - number of power pads for sso block under the limit of sso noise ? calculating the number of power pad for each sso group from the following expressions: in above formula, nvddo each_sso = number of vdd2o (vdd3o) pad required for each sso group nvsso each_sso = number of vss2o (vss3o) pad required for each sso group nbvdd = number of buffers per vdd2o (vdd3o) power pad with 1nh lead inductance (refer table 1-15.) nbvss = number of buffers per vss2o (vss3o) ground pas with 1nh lead inductance l pg = package lead frame inductance (refer to 1.9 package capability by lead count) d sso_mode = d l_mode d p_mode d v_mode d t_mode d c_mode (refer to table 1-13. and table 1-14.) d l_mode = lead inductance derating factor d p_mode = process derating factor d v_mode = voltage derating factor d t_mode = temperature derating factor d c_mode = cload derating factor (*mode is either vdd or vss.) input buffer type cmos ttl schmitt trigger ieq_p (ma) normal 0.52 0.54 0.54 tolerant 0.60 0.60 0.51 output pre-driver type cmos driver tristate b1C4 b6C8 b10C12 t1C4 t6C8 t10C12 ieq_p (ma) normal normal 0.25 0.46 0.55 0.34 0.51 0.60 slew rate 0.28 0.37 0.46 0.36 0.45 0.55 tolerant --- (t1,2,3) 0.50 -- nvddo each_sso number_of_sso nbvdd ---------------------------------------------- l pg 1 d sso_mode -------------------------- = nvsso each_sso number_of_sso nbvss ---------------------------------------------- l pg 1 d sso_mode -------------------------- =
1.11 vdd/vss rules and guidelines introduction STD111 1-42 samsung asic table 1-13. derating equation (external 2.5v interface) table 1-14. derating equation (external 3.3v interface) item mode equation range package lead d l_vdd 0.0417 x lpg + 0.9375 0.0417 x lpg + 0.9375 3nh lpg 10nh 10nh lpg 15nh d l_vss 0.0417 x lpg + 0.9375 0.0417 x lpg + 0.9375 3nh lpg 10nh 10nh < lpg 15nh process d p_vdd 1.0000 1.2549 1.7255 best typical worst d p_vss 1.0000 1.2549 1.7451 best typical worst voltage d v_vdd C 0.8824 x voltage + 3.3235 C 0.5882 x voltage + 2.5882 2.3 voltage 2.5 2.5 < voltage 2.7 d v_vss C 0.8824 x voltage + 3.3235 C 0.5882 x voltage + 2.5882 2.3 voltage 2.5 2.5 < voltage 2.7 temperature d t_vdd 0.0024 x temperature + 1.0000 0.0032 x temperature + 0.9786 -40 temperature 25 25 < temperature 125 d t_vss 0.0031 x temperature + 1.0000 0.0029 x temperature + 1.0071 -40 temperature 25 25 < temperature 125 cload d c_vdd 0.0347 x cload + 0.6525 0.0286 x cload + 0.8369 10pf cload 30pf 30pf < cload 50pf d c_vss 0.0354 x cload + 0.6456 0.0285 x cload + 0.8544 10pf cload 30pf 30pf < cload 50pf item mode equation range package lead d l_vdd 0.0462 x lpg + 1.1538 0.0231 x lpg + 1.3846 3nh lpg 10nh 10nh lpg 15nh d l_vss 0.0469 x lpg + 0.7813 0.0313 x lpg + 0.9375 3nh lpg 10nh 10nh < lpg 15nh process d p_vdd 1.0000 1.2537 2.2985 best typical worst d p_vss 1.0000 1.1563 1.4063 best typical worst voltage d v_vdd C 1.2936 x voltage + 5.4328 C 0.4478 x voltage + 2.6119 3.0 voltage 3.3 3.3 < voltage 3.6 d v_vss C 0.4166 x voltage + 2.5000 C 0.4166 x voltage + 2.5000 3.0 voltage 3.3 3.3 < voltage 3.6 temperature d t_vdd 0.0036 x temperature + 1.0000 0.0041 x temperature + 0.9878 -40 temperature 25 25 < temperature 125 d t_vss 0.0038 x temperature + 1.0000 0.0028 x temperature + 1.0227 -40 temperature 25 25 < temperature 125 cload d c_vdd 0.0338 x cload + 0.6618 0.0554 x cload + 0.0146 10pf cload 30pf 30pf < cload 50pf d c_vss 0.0444 x cload + 0.5556 0.0370 x cload + 0.7778 10pf cload 30pf 30pf < cload 50pf
introduction 1.11 vdd/vss rules and guidelines samsung asic 1-43 STD111 table 1-15. nbvdd/nbvss parameter (process = best, volt =2.7v/3.6v temp. = 0?c, llead = 1nh) note: pob1 means 1ma output driver cell, and pob12 means 12ma output driver cell. ? calculating the number of required power pad for total sso from the following expression: nvddo1sso = ? nvddoeach_sso nvsso1sso = ? nvssoeach_sso when there are sso blocks which are not switching simultaneously with the others, only maximum value of nvddo_each_sso/nvsso_each_sso among those sso block should be accounted. in the above formula, nvddosso = number of vdd2o (vdd3o) pad per total sso buffers nvssosso = number of vss2o (vss3o) pad per total sso buffers buffer type voltage type normal slew-rate medium (sm) slew-rate high (sh) nbvdd nbvss nbvdd nbvss nbvdd nbvss pob1 (pot1) 2.5v interface 176 178 C C C C pob2 (pot2) 140 142 C C C C pob4 (pot4) 102 102 160 160 C C pob6 (pot6) 84 84 142 142 C C pob8 (pot8) 72 72 116 116 C C pob12 (pot12) 60 60 96 96 236 236 phob1 (phot1) 3.3v interface 382 166 C C C C phob2 (phot2) 276 104 C C C C phob4 (phot4) 134 64 168 104 C C phob6 (phot6) 108 44 132 90 C C phob8 (phot8) 98 38 118 86 C C phob12 (phot12) 86 32 92 62 130 124 ptot1 5v tolerant 434 376 C ptot2 272 180 ptot3 203 116
1.11 vdd/vss rules and guidelines introduction STD111 1-44 samsung asic - number of power pads for sso block under the limit of electromigration rule ? calculating the following expression: 2) number of power pads for non-sso block ? calculating the following expression: 3) total number of power pads for vdd2o/vss2o (vdd3o/vss3o) ? calculating the following expressions: when open drain type buffers are used, you can consider using vss2o (vss3o) pads since they have current sink only. nvddo2 sso nvsso2 sso i eq_o i em ---------- - = where n_sso_output is the number of simultaneous switching output buffers used, n_sso_bi is the number of simultaneous switching bi-directional buffers used, c outload = output load capacitance [pf] v = operating voltage [v] f = maximum i/o operating frequency [mhz] s = switching ratio (typically 0.5) s out = output mode ratio of bidirectional buffers (typically 0.5) i em = current limit per vdd/vss pad paris based on electromigration rule. (80ma) i eq_o 0.001 c i_outload v i f i s i () i n_sso_output ? 0.001 c j_outload v j f j s j s j_out () j n_sso_bi ? + = nvddo non_sso nvsso non_sso i eq_o i em ---------- - = where n_non_sso_output is the number of non-simultaneous switching output buffers used, n_non_sso_bi is the number of non-simultaneous switching bi-directional buffers used, c outload = output load capacitance [pf] v = operating voltage [v] f = maximum i/o operating frequency [mhz] s = switching ratio (typically 0.5) s out = output mode ratio of bidirectional buffers (typically 0.5) i em = current limit per vdd/vss pad paris based on electromigration rule. (80ma) i eq_o 0.001 c i_outload v i f i s i () i n_non_sso_output ? 0.001 c j_outload v j f j s j s j_out () j n_non_sso_bi ? + = number of vdd2o (vdd3o) max nvddo1 sso nvddo2 sso , () nvddo non_sso + round-up = number of vss2o (vss3o) max n vsso1 sso nvsso2 sso , () nvsso non_sso + round-up =
introduction 1.12 crystal oscillator consideration samsung asic 1-45 STD111 1.12 crystal oscillator consideration 1.12.1 overview STD111 contains a circuit commonly referred to as an on-chip oscillator. the on-chip circuit itself is not an oscillator but an ampli?er which is suitable for being used as the ampli?er part of a feedback oscillator. with proper selection of off- chip components, this oscillator circuit performs better than any other types of clock oscillators. it is very important to select suitable off-chip components to work with the on- chip oscillator circuitry. it should be noted, however, that samsung cannot assume the responsibility of writing speci?cations for the off-chip components of the complete oscillator circuit, nor of guaranteeing the performance of the ?nished design in production, any more than a transistor manufacturer, whose data sheets show a number of suggested ampli?er circuits, can assume responsibility for the operation, in production, of any of them. we are often asked why we dont publish a list of required crystal or ceramic resonator speci?cations, and recommend values for the other off-chip components. this has been done in the past, but sometimes with consequences that were not intended. suppose we suggest a maximum crystal resistance of 30ohms for some given frequency. then your crystal supplier tells you the 30ohm crystals are going to cost twice as much as 50ohm crystals. fearing that samsung will not guarantee operation with 50ohm crystals, you order the expensive ones. in fact, samsung guarantees only what is embodied within an samsung product. besides, there is no reason why 50ohm crystals couldnt be used, if the other off-chip components are suitably adjusted. should we recommend values for the other off-chip components? should we do for 50ohm crystals or 30ohm crystals? with respect to what should we optimize their selection? should we minimize start-up time or maximize frequency stability? in many applications, neither start-up time nor frequency stability is particularly critical, and our recommendations are only restricting your system to unnecessary tolerances. it all depends on the application. 1.12.2 oscillator design considerations asic designers have a number of options for clocking the system. the main decision is whether to use the on-chip oscillator or an external oscillator. if the choice is to use the on-chip oscillator, what kinds of external components are to use an external oscillator, what type of oscillator would it be? the decisions have to be based on both economic and technical requirements. in this section we will discuss some of the factors that should be considered.
1.12 crystal oscillator consideration introduction STD111 1-46 samsung asic 1.12.2.1 on-chip oscillator in most cases, the on-chip ampli?er with the appropriate external components provides the most economical solution to the clocking problem. exceptions may arise in server environments when frequency tolerances are tighter than about 0.01%. the external components that commonly used for cmos gate oscillator are a positive reactance (normal crystal oscillator), two capacitors, c1 and c2, and two resistor rf and rx as shown in the ?gure below. figure 1-19. cmos oscillator 1.12.2.2 crystal speci?cations speci?cations for an appropriate crystal are not very critical, unless the frequency is. any fundamental-mode crystal of medium or better quality can be used. we are often asked what maximum crystal resistance should be speci?ed. the best answer to that question is the lower the better, but use what is available. the crystal resistance will have some effect on start-up time and steady-state amplitude, but not so much that it cant be compensated for by appropriate selection of the capacitance, c1 and c2. similar questions are asked about speci?cations of load capacitance and shunt capacitance. the best advice we can give is to understand what these parameters mean and how they affect the operation of the circuit (that being the purpose of this application note), and then to decide for yourself if such speci?cations are meaningful in your frequency tolerances are tighter than about 0.1%. part of the problem is that crystal manufacturers are accustomed to talking ppm tolerances with radio engineers and simply wont take your order until youve ?lled out their list of frequency tolerance requirements, both for yourself and to the crystal manufacturer. dont pay for 0.003% crystals if your actual frequency tolerance is 1%. c1 c2 rx rf pada pady feedback inside of a chip amplifier
introduction 1.12 crystal oscillator consideration samsung asic 1-47 STD111 1.12.2.3 oscillation frequency the oscillation frequency is determined 99.5% by the crystal and up to about 0.5% by the circuit external to the crystal. the on-chip ampli?er has little effect on the frequency, which is as it should be, since the ampli?er parameterizes temperature and process dependent. the in?uence of the on-chip ampli?er on the frequency is by means of its input and output (pin-to-ground) capacitances, which parallel c1 and c2, and the pada-to-pady (pin-to-pin) capacitance, which parallels the crystal. the input and pin-to-pin capacitances are about 7pf each. internal phase deviations capacitance of 25 to 30pf. these deviations from the ideal have less effect in the positive reactance oscillator (with the inverting ampli?er) than in a comparable series resonant oscillator (with the non-inverting ampli?er) for two reasons: ?rst, the effect of the output capacitor; second, the positive reactance oscillator is less sensitive, frequency-wise, to such phase errors. 1.12.2.4 c1 / c2 selection optimal values for the capacitors c1 and c2 depend on whether a quartz crystal or ceramic resonator is being used, and also on application-speci?c requirements on start-up time and frequency tolerance. start-up time is sometimes more critical in microcontroller systems than frequency stability, because of various reset and initialization requirements. less commonly, accuracy of the oscillator frequency is also critical, for example, when the oscillator is being used as a time base. as a general rule, fast start-up and stable frequency tend to pull the oscillator design in opposite directions. considerations of both start-up time and frequency stability over temperature suggest that c1 and c2 should be about equal and at least 15pf. (but they dont have to be either.) increasing the value of these capacitances above some 40 or 50pf improves frequency stability. it also tends to increase the start-up time. these is a maximum value (several hundred ph, depending on the value of r1 of the quartz or ceramic resonator) above which the oscillator wont start up at all. if the on-chip ampli?er is a simple inverter, the user can select values for c1 and c2 between some 15 and 50pf, depending on whether start-up time or frequency stability is the more critical parameter in a speci?c application. 1.12.2.5 rf / rx selection a cmos inverter might work better in this application since a large rf (1mega- ohm) can be used to hold the inverter in its linear region. logic gates tend to have a fairly low output resistance, which testabilizes the oscillator. for that reason a resistor rx (several k-ohm) is often added to the feedback network, as shown in figure 1-19. at higher frequencies a 20 or 30pf capacitor is sometimes used in the rx position, to compensate for some of the internal propagation delay.
1.12 crystal oscillator consideration introduction STD111 1-48 samsung asic 1.12.2.6 pin capacitance rf / rx selection internal pin-to-ground and pin-to-pin capacitances, and pada and pady have some effect on the oscillator. these capacitances are normally taken to be in the range of 5 to 10pf, but they are extremely dif?cult to evaluate. any measurement of one such capacitance necessarily include effects from the others. one advantage of the positive reactance oscillator is that the pin-to ground cap. is paralleled by an external bulk capacitance, so a precise determination of their value is unnecessary. we would suggest that there is little justi?cation for more precision than to assign them a value of 7pf (pada-to-ground and pada-to-pady). this value is probably not in error by more than 3 or 4pf. the pady-to-ground cap. is not entirely a pin capacitance, but more like an equivalent output capacitance of some 25 to 30pf, having to include the effect of internal phase delays. this value varies to some extent with temperature, process, and frequency. 1.12.2.7 placement of components noise glitches arising at pada or pady pins at the wrong time can cause a miscount in the internal clock-generating circuitry. these kinds of glitches can be produced through capacitive coupling between the oscillator components and pcb traces carrying digital signals with fast rise and fall times. for this reason, the oscillator components should be mounted close to the chip and have short, direct traces to the pada, pady, and v ss pins. if possible, use dedicated v ss and v dd pin for only crystal feedback ampli?er. 1.12.3 troubleshooting oscillator problems the ?rst thing to consider in case of dif?culty is that there may be signi?cant differences in stray caps between the test jig and the actual application, particularly if the actual application is on a multi-layer board. noise glitches, that are not present in the test jig but are in the application board, are another possibility. capacitive coupling between the oscillator circuitry and other signal has already been mentioned as a source of miscounts in the internal clocking circuitry. inductive coupling is also doubtful, if there is strong current nearby. these problems are a function of the pcb layout. surrounding oscillator components with quit traces (for example, vcc and ground) will alleviate capacitive coupling to signals having fast transition time. to minimize inductive coupling, the pcb layout should minimize the areas of the loops formed by oscillator components. the loops demanding to be checked are as follows: pada through the resonator to pady; pada through c1 to the v ss pin; pady through c2 to the v ss pin. it is not unusual to ?nd that the ground ends of c1 and c2 eventually connect up to the v ss pin only after looping around the farthest ends of the board. not good. finally, it should not be overlooked that software problems sometimes imitate the symptoms of a slow-starting oscillator or incorrect frequency. never underestimate the perversity of a software problem.
2 electrical characteristics
contents dc electrical characteristics ......................................................................................... 2-1
electrical characteristics dc electrical characteristics samsung asic 2-1 STD111 dc electrical characteristics v dd = 3.3 0.3v, t a = -40 to 85 c, v ext = 5 0.25v (in case of 5v tolerant) symbol parameter condition min type max unit v ih high level input voltage v lvcmos interface 0.7v dd lvttl interface 2.0 v il low level input voltage v lvcmos interface 0.3v dd lvttl interface 0.8 vt switching threshold lvcmos 0.5vdd v lvttl 1.4 vt + schmitt trigger, positive-going threshold lvcmos/lvttl 2.0 vt - schmitt trigger, negative-going threshold lvcmos/lvttl 0.8 v h vt + - vt - schmitt-trigger 0.5 0.575 0.65 i ih high level input current m a input buffer v in = v dd C10 10 input buffer with pull-down 10 33 60 i il low level input current m a input buffer v in = v ss C10 10 input buffer with pull-up C60 C33 C10 v oh high level output voltage v type b1 to b12 note1 i oh = C1 m av dd C 0.05 type b1 i oh = C1ma 2.4 type b2 i oh = C2ma type b3 i oh = C3ma type b4 i oh = C4ma type b6 i oh = C6ma type b8 i oh = C8ma type b10 i oh = C10ma type b12 i oh = C12ma v ol low level output voltage v type b1 to b12 note1 i ol = 1 m a 0.05 type b1 i ol = 1ma 0.4 type b2 i ol = 2ma type b3 i ol = 3ma type b4 i ol = 4ma type b6 i ol = 6ma type b8 i ol = 8ma type b10 i ol = 10ma type b12 i ol = 12ma i oz tri-state output leakage current v out =v ss or v ext C10 10 m a i os output short circuit current v dd = 3.6v , v o =v dd 55 ma v dd = 3.6v , v o =v ss C55 i dd quiescent supply current v in =v ss or v dd 100 note2 m a c in input capacitance note3 any input and bidirectional buffers 4pf c out output capacitance note3 any output buffer 4 pf
dc electrical characteristics electrical characteristics STD111 2-2 samsung asic v dd = 2.5 0.2v, t a = -40 to 85 c (in case of general i/o) notes: 1. type b1 means 1ma output driver cells, and type b6/b12 means 6ma/12ma output driver cells. 2. this value depends on the customer design. 3. this value exclude package parasitics. symbol parameter condition min type max unit v ih high level input voltage v lvcmos interface 1.7 v il low level input voltage v lvcmos interface 0.7 vt switching threshold lvcmos 0.5v dd v vt + schmitt trigger, positive-going threshold lvcmos 1.9 vt- schmitt trigger, negative-going threshold lvcmos 0.6 v h vt + - vt - schmitt-trigger 0.5 0.65 0.8 i ih high level input current m a input buffer v in = v dd C10 10 input buffer with pull-down 10 25 50 i il low level input current m a input buffer v in = v ss C10 10 input buffer with pull-up C50 C25 C10 v oh high level output voltage v type b1 to b12 note1 i oh = C1 m av dd C 0.05 type b1 i oh = C1ma 1.9 type b2 i oh = C2ma type b4 i oh = C4ma type b6 i oh = C6ma type b8 i oh = C8ma type b10 i oh = C10ma type b12 i oh = C12ma v ol low level output voltage v type b1 to b12 note1 i ol = 1 m a 0.05 type b1 i ol = 1ma 0.5 type b2 i ol = 2ma type b4 i ol = 4ma type b6 i oh = 6ma type b8 i oh = 8ma type b10 i oh = 10ma type b12 i oh = 12ma i oz tri-state output leakage current v out =v ss or v ext C10 10 m a i os output short circuit current v dd = 3.6v , v o =v dd 55 ma v dd = 3.6v , v o =v ss C55 i dd quiescent supply current v in =v ss or v dd 100 note2 m a c in input capacitance note3 any input and bidirectional buffers 4pf c out output capacitance note3 any output buffer 4 pf
electrical characteristics dc electrical characteristics samsung asic 2-3 STD111 absolute maximum ratings recommended operating conditions symbol parameter rating unit v dd dc supply voltage 3.6 v v in dc input voltage 2.5v input buffer 3.6 3.3v input buffer 4.6 5v- tolerant input buffer 6.5 v out dc output voltage 2.5v buffer 3.6 3.3v buffer 4.6 i latch latch-up current 200 ma t stg storage temperature C 65 to 150 c symbol parameter rating unit v dd dc supply voltage 2.5v i/o 2.3 to 2.7 v 3.3v i/o 3.0 to 3.6 5v tolerant i/o 3.0 to 3.6 analog core dc supply voltage 2.5v core 2.5 5% 1.8v core 1.8 5% t a commercial temperature range 0 to 70 c industrial temperature range C 40 to 85
3 internal macrocells
contents overview ....................................................................................................................... ..... 3-1 summary tables................................................................................................................. 3-2 logic cells.................................................................................................................... ...... 3-7 flip-flops..................................................................................................................... ....... 3-300 latches........................................................................................................................ ....... 3-400 bus holder..................................................................................................................... ..... 3-448 internal clock drivers ......................................................................................................... 3-449 decoders ....................................................................................................................... ..... 3-451 adders ......................................................................................................................... ....... 3-460 multiplexers ................................................................................................................... ..... 3-470
internal macrocells overview samsung asic 3-1 STD111 overview the third chapter contains data sheets of logic cells, ?ip-?ops, latches, bus holder, internal clock drivers, decoders, adders and multiplexers. the electrical characteristics of each cell follow its basic cell data. summary tables in the following pages list the whole STD111 internal macrocells by the type and show their reference page numbers for your convenience. moreover, you can ?nd the more detailed description tables on the leading pages of each category.
summary tables internal macrocells STD111 3-2 samsung asic summary tables logic cells cell type cell name page and cells ad2dh/ad2/ad2d2/ad2d4 3-17 ad3dh/ad3/ad3d2/ad3d4 3-19 ad4dh/ad4/ad4d2/ad4d4 3-21 ad5/ad5d2/ad5d4 3-24 nand cells nd2dh/nd2/nd2d2/nd2d4 3-27 nd3dh/nd3/nd3d2/nd3d4 3-29 nd4dh/nd4/nd4d2/nd4d2b/nd4d4 3-32 nd5/nd5d2/nd5d4 3-35 nd6/nd6d2/nd6d4 3-38 nd8/nd8d2/nd8d4 3-42 nor cells nr2dh/nr2/nr2d2/nr2d2b/nr2d4/nr2a 3-46 nr3dh/nr3/nr3d2/nr3d2b/nr3d4/nr3a 3-49 nr4dh/nr4/nr4d2/nr4d4 3-53 nr5/nr5d2/nr5d4 3-56 nr6/nr6d2/nr6d4 3-60 nr8/nr8d2/nr8d4 3-64 or cells or2dh/or2/or2d2/or2d4 3-68 or3dh/or3/or3d3/or3d4 3-70 or4dh/or4/or4d2/or4d4 3-73 or5/or5d2/or5d4 3-76 exclusive-nor cells xn2/xn2d2/xn2d4 3-80 xn3/xn3d2/xn3d4 3-82 exclusive-or cells xo2/xo2d2/xo2d4 3-84 xo3/xo3d2/xo3d4 3-86 combinational cells of and and nor ao21dh/ao21/ao21d2/ao21d2b/ao21d4 3-88 ao211dh//ao211d2/ao211d2b/ao211d4 3-91 ao2111/ao2111d2 3-94 ao22dh/ao22/ao22d2/ao22d2b/ao22d4 3-97 ao22dha/ao22a/ao22d2a/ao22d4a 3-100 ao221/ao221d2/ao221d4 3-103 ao222/ao222d2/ao222d2b/ao222d4 3-107 ao222a/ao222d2a/ao222d4a 3-112 ao2222/ao2222d2/ao2222d4 3-114 ao31dh/ao31/ao31d2/ao31d4 3-118 ao311/ao311d2/ao311d4 3-121 ao3111/ao3111d2 3-125 ao32/ao32d2/ao32d4 3-128
internal macrocells summary tables samsung asic 3-3 STD111 ao321/ao321d2/ao321d4 3-132 ao322/ao322d2/ao322d4 3-136 ao33/ao33d2/ao33d4 3-140 ao331/ao331d2/ao331d4 3-144 ao332/ao332d2/ao332d4 3-148 ao4111/ao4111d2 3-152 combinational cells of or and nand oa21dh/oa21/oa21d2/oa21d2b/oa21d4 3-155 oa211dh/oa211/oa211d2/oa211d2b/oa211d4 3-158 oa2111/oa2111d2 3-161 oa22dh/oa22/oa22d2/oa22d2b/oa22d4 3-164 oa22dha/oa22a/oa22d2a/oa22d4a 3-167 oa221/oa221d2/oa221d4 3-170 oa222/oa222d2/oa222d2b/oa222d4 3-174 oa2222/oa2222d2/oa2222d4 3-179 oa31dh/oa31/oa31d2/oa31d4 3-183 oa311/oa311d2/oa311d4 3-186 oa3111/oa3111d2 3-190 oa32/oa32d2/oa32d4 3-193 oa321/oa321d2/oa321d4 3-197 oa322/oa322d2/oa322d4 3-201 oa33/oa33d2/oa33d4 3-205 oa331/oa331d2/oa331d4 3-209 oa332/oa332d2/oa332d4 3-213 oa4111/oa4111d2 3-217 complex cells scg1/scg1d2 3-220 scg2/scg2d2 3-223 scg3/scgd2 3-225 scg4/scg4d2 3-228 scg5/scg5d2 3-231 scg6/scg6d2 3-234 scg7/scg7d2 3-236 scg8/scg8d2 3-239 scg9/scg9d2 3-241 scg10/scg10d2 3-243 scg11/scg11d2 3-246 scg12/scg12d2 3-248 scg13/scg13d2 3-250 scg14/scg14d2 3-252 scg15/scg15d2 3-254 scg16/scg16d2 3-256 scg17/scg17d2 3-258 cell type cell name page
summary tables internal macrocells STD111 3-4 samsung asic flip-flops complex cells scg18/scg18d2 3-260 scg19/scg19d2 3-263 scg20/scg20d2 3-265 scg21/scg21d2 3-267 scg22/scg22d2 3-269 delay cells dl1d2/dl1d4 3-271 dl2d2/dl2d4 3-272 dl3d2/dl3d4 3-273 dl4d2/dl4d4 3-274 dl5d2/dl5d4 3-275 dl10d2/dl10d4 3-276 inverters ivdh/iv/ivd2/ivd3/ivd4/ivd6/ivd8/ivd16 3-277 ivcd(11/13)/ivcd(22/26)/ivcd44 3-280 inverting tri-state buffers ivt/ivtd2/ivtd4/ivtd8/ivtd16 3-282 ivtn/ivtnd2/ivtnd4/ivtnd8/ivtnd16 3-284 non-inverting buffers nidh/nid/nid2/nid3/nid4/nid6/nid8/nid16 3-286 clock buffers for oak core only oak_nid10p/oak_nid 20p 3-289 non-inverting tri-state buffers nit/nitd2/nitd4/nitd8/nitd16 3-290 nitn/nitnd2/nitnd4/nitnd8/nitnd16 3-293 2 phase clock generator buffers for oak core only oak_duclk10/oak_duclk16 3-296 clock tree synthesis buffers ctsb/ctsbd2/ctsbd3/ctsbd4/ctsbd6/ ctsbd8/ctsbd16 3-298 cell type cell name page d flip-flop fd1/fd1d2 3-303 fd1cs/fd1csd2 3-305 fd1s/fd1sd2 3-307 fd1sq/fd1sqd2 3-309 fd1q/fd1qd2 3-311 d flip-flop with reset fd2/fd2d2 3-313 fd2cs/fd2csd2 3-315 fd2s/fd2sd2 3-319 fd2sq/fd2sqd2 3-321 fd2q/fd2qd2 3-323 d flip-flop with set fd3/fd3d2 3-325 fd3cs/fd3csd2 3-327 fd3s/fd3sd2 3-331 fd3sq/fd3sqd2 3-333 fd3q/fd3qd2 3-335 cell type cell name page
internal macrocells summary tables samsung asic 3-5 STD111 latches d flip-flop with reset, set fd4/fd4d2 3-337 fd4cs/fd4csd2 3-340 fd4s/fd4sd2 3-344 fd4sq/fd4sqd2 3-348 fd4q/fd4qd2 3-351 d flip-flop with negative edge trigger fd5/fd5d2 3-353 fd5s/fd5sd2 3-355 fd6/fd6d2 3-357 fd6s/fd6sd2 3-359 fd7/fd7d2 3-361 fd7s/fd7sd2 3-363 fd8/fd8d2 3-365 fd8s/fd8sd2 3-368 d flip-flop with synchronous clear fds2/fds2d2 3-372 fds2cs/fds2csd2 3-374 fds2s/fds2sd2 3-376 fds3/fds3d2 3-378 fds3cs/fds3csd2 3-380 fds3s/fds3sd2 3-382 jk flip-flop fj1/fj1d2 3-384 fj1s/fj1sd2 3-386 fj2/fj2d2 3-388 fj2s/fj2sd2 3-390 fj4/fj4d2 3-392 fj4s/fj4sd2 3-395 toggle flip-flop ft2/ft2d2 3-398 cell type cell name page d latch with active high ld1/ld1d2 3-402 ld1a/ld1d2a 3-404 ld1q/ld1qd2 3-406 ld2/ld2d2 3-408 ld2q/ld2qd2 3-411 ld3/ld3d2 3-413 ld4/ld4d2 3-416 d latch with active low ld5/ld5d2 3-419 ld5q/ld5qd2 3-421 ld6/ld6d2 3-423 ld6q/ld6qd2 3-426 cell type cell name page
summary tables internal macrocells STD111 3-6 samsung asic bus holder internal clock drivers decoders adders multiplexers ld7/ld7d2 3-428 ld8/ld8d2 3-431 d latch with active low for oak core only oak_ldi2/oak_ldi2d2 3-434 oak_ldi3/oak_ldi3d2 3-437 sr latch ls0/ls0d2 3-442 ls1/ls1d2 3-444 cell type cell name page bus holder busholder 3-448 cell type cell name page internal clock drivers ck2/ck4/ck6/ck8 3-449 cell type cell name page non-inverting decoder dc4 3-452 inverting decoders dc4i 3-454 dc8i 3-456 cell type cell name page full adders fadh/fa/fad2 3-461 half adders hadh/ha/had2 3-464 complex cells scg23/scg23d2 3-467 cell type cell name page 2 > 1 non-inverting mux mx2dh/mx2/mx2d2/mx2d4 3-471 mx2x4 3-474 2 > 1 inverting mux mx2idh/mx2i/mx2id2/mx2id4 3-477 mx2idha/mx2ia/mx2id2a/mx2id4a 3-480 mx2ix4 3-483 3 > 1 inverting mux mx3i/mx3id2/mx3id4 3-486 4 > 1 non-inverting mux mx4/mx4d2/mx4d4 3-490 8 > 1 non-inverting mux mx8/mx8d2/mx8d4 3-494 cell type cell name page
samsung asic 3-7 STD111 logic cells cell names & function descriptions cell name function description ad2dh 2-input and with 0.5x drive ad2 2-input and with 1x drive ad2d2 2-input and with 2x drive ad2d4 2-input and with 4x drive ad3dh 3-input and with 0.5x drive ad3 3-input and with 1x drive ad3d2 3-input and with 2x drive ad3d4 3-input and with 4x drive ad4dh 4-input and with 0.5x drive ad4 4-input and with 1x drive ad4d2 4-input and with 2x drive ad4d4 4-input and with 4x drive ad5 5-input and with 1x drive ad5d2 5-input and with 2x drive ad5d4 5-input and with 4x drive nd2dh 2-input nand with 0.5x drive nd2 2-input nand with 1x drive nd2d2 2-input nand with 2x drive nd2d4 2-input nand with 4x drive nd3dh 3-input nand with 0.5x drive nd3 3-input nand with 1x drive nd3d2 3-input nand with 2x drive nd3d4 3-input nand with 4x drive nd4dh 4-input nand with 0.5x drive nd4 4-input nand with 1x drive nd4d2 4-input nand with 2x drive nd4d2b 4-input nand with 2x (buffered) drive nd4d4 4-input nand with 4x drive nd5 5-input nand with 1x drive nd5d2 5-input nand with 2x drive nd5d4 5-input nand with 4x drive nd6 6-input nand with 1x drive nd6d2 6-input nand with 2x drive nd6d4 6-input nand with 4x drive nd8 8-input nand with 1x drive nd8d2 8-input nand with 2x drive nd8d4 8-input nand with 4x drive
STD111 3-8 samsung asic nr2dh 2-input nor with 0.5x drive nr2 2-input nor with 1x drive nr2d2 2-input nor with 2x drive nr2d2b 2-input nor with 2x (buffered) drive nr2d4 2-input nor with 4x drive nr2a nr2 with 2x p-transistor, 1x n-transistor nr3dh 3-input nor with 0.5x drive nr3 3-input nor with 1x drive nr3d2 3-input nor with 2x drive nr3d2b 3-input nor with 2x (buffered) drive nr3d4 3-input nor with 4x drive nr3a nr3 with 2x p-transistor, 1x n-transistor nr4dh 4-input nor with 0.5x drive nr4 4-input nor with 1x drive nr4d2 4-input nor with 2x drive nr4d4 4-input nor with 4x drive nr5 5-input nor with 1x drive nr5d2 5-input nor with 2x drive nr5d4 5-input nor with 4x drive nr6 6-input nor with 1x drive nr6d2 6-input nor with 2x drive nr6d4 6-input nor with 4x drive nr8 8-input nor with 1x drive nr8d2 8-input nor with 2x drive nr8d4 8-input nor with 4x drive or2dh 2-input or with 0.5x drive or2 2-input or with 1x drive or2d2 2-input or with 2x drive or2d4 2-input or with 4x drive or3dh 3-input or with 0.5x drive or3 3-input or with 1x drive or3d2 3-input or with 2x drive or3d4 3-input or with 4x drive or4dh 4-input or with 0.5x drive or4 4-input or with 1x drive or4d2 4-input or with 2x drive or4d4 4-input or with 4x drive cell name function description logic cells cell names & function descriptions (continued)
samsung asic 3-9 STD111 or5 5-input or with 1x drive or5d2 5-input or with 2x drive or5d4 5-input or with 4x drive xn2 2-input exclusive-nor with 1x drive xn2d2 2-input exclusive-nor with 2x drive xn2d4 2-input exclusive-nor with 4x drive xn3 3-input exclusive-nor with 1x drive xn3d2 3-input exclusive-nor with 2x drive xn3d4 3-input exclusive-nor with 4x drive xo2 2-input exclusive-or with 1x drive xo2d2 2-input exclusive-or with 2x drive xo2d4 2-input exclusive-or with 4x drive xo3 3-input exclusive-or with 1x drive xo3d2 3-input exclusive-or with 2x drive xo3d4 3-input exclusive-or with 4x drive ao21dh 2-and into 2-nor with 0.5x drive ao21 2-and into 2-nor with 1x drive ao21d2 2-and into 2-nor with 2x drive ao21d2b 2-and into 2-nor with 2x(buffered) drive ao21d4 2-and into 2-nor with 4x drive ao211dh 2-and into 3-nor with 0.5x drive ao211 2-and into 3-nor with 1x drive ao211d2 2-and into 3-nor with 2x drive ao211d2b 2-and into 3-nor with 2x(buffered) drive ao211d4 2-and into 3-nor with 4x drive ao2111 2-and into 4-nor with 1x drive ao2111d2 2-and into 4-nor with 2x drive ao22dh two 2-ands into 2-nor with 0.5x drive ao22 two 2-ands into 2-nor with 1x drive ao22d2 two 2-ands into 2-nor with 2x drive ao22d2b two 2-ands into 2-nor with 2x(buffered) drive ao22d4 two 2-ands into 2-nor with 4x drive ao22dha 2-and and 2-nor into 2-nor with 0.5x drive ao22a 2-and and 2-nor into 2-nor with 1x drive ao22d2a 2-and and 2-nor into 2-nor with 2x drive ao22d4a 2-and and 2-nor into 2-nor with 4x drive cell name function description logic cells cell names & function descriptions (continued)
STD111 3-10 samsung asic logic cells cell names & function descriptions (continued) ao221 two 2-ands into 3-nor with 1x drive ao221d2 two 2-ands into 3-nor with 2x drive ao221d4 two 2-ands into 3-nor with 4x drive ao222 three 2-ands into 3-nor with 1x drive ao222d2 three 2-ands into 3-nor with 2x drive ao222d2b three 2-ands into 3-nor with 2x(buffered) drive ao222d4 three 2-ands into 3-nor with 4x drive ao222a inverting 2-of-3 majority with 1x drive ao222d2a inverting 2-of-3 majority with 2x drive ao222d4a inverting 2-of-3 majority with 4x drive ao2222 four 2-ands into 4-nor with 1x drive ao2222d2 four 2-ands into 4-nor with 2x drive ao2222d4 four 2-ands into 4-nor with 4x drive ao31dh 3-and into 2-nor with 0.5x drive ao31 3-and into 2-nor with 1x drive ao31d2 3-and into 2-nor with 2x drive ao31d4 3-and into 2-nor with 4x drive ao311 3-and into 3-nor with 1x drive ao311d2 3-and into 3-nor with 2x drive ao311d4 3-and into 3-nor with 4x drive ao3111 3-and into 4-nor with 1x drive ao3111d2 3-and into 4-nor with 2x drive ao32 3-and and 2-and into 2-nor with 1x drive ao32d2 3-and and 2-and into 2-nor with 2x drive ao32d4 3-and and 2-and into 2-nor with 4x drive ao321 3-and and 2-and into 3-nor with 1x drive ao321d2 3-and and 2-and into 3-nor with 2x drive ao321d4 3-and and 2-and into 3-nor with 4x drive ao322 3-and and two 2-ands into 3-nor with 1x drive ao322d2 3-and and two 2-ands into 3-nor with 2x drive ao322d4 3-and and two 2-ands into 3-nor with 4x drive ao33 two 3-ands into 2-nor with 1x drive ao33d2 two 3-ands into 2-nor with 2x drive ao33d4 two 3-ands into 2-nor with 4x drive ao331 two 3-ands into 3-nor with 1x drive ao331d2 two 3-ands into 3-nor with 2x drive ao331d4 two 3-ands into 3-nor with 4x drive cell name function description
samsung asic 3-11 STD111 logic cells cell names & function descriptions (continued) ao332 two 3-ands and 2-and into 3-nor ao332d2 two 3-ands and 2-and into 3-nor with 2x drive ao332d4 two 3-ands and 2-and into 3-nor with 4x drive ao4111 4-and into 4-nor with 1x drive ao4111d2 4-and into 4-nor with 2x drive oa21dh 2-or into 2-nand with 0.5x drive oa21 2-or into 2-nand with 1x drive oa21d2 2-or into 2-nand with 2x drive oa21d2b 2-or into 2-nand with 2x(buffered) drive oa21d4 2-or into 2-nand with 4x drive oa211dh 2-or into 3-nand with 0.5x drive oa211 2-or into 3-nand with 1x drive oa211d2 2-or into 3-nand with 2x drive oa211d2b 2-or into 3-nand with 2x(buffered) drive oa211d4 2-or into 3-nand with 4x drive oa2111 2-or into 4-nand with 1x drive oa2111d2 2-or into 4-nand with 2x drive oa22dh two 2-ors into 2-nand with 0.5x drive oa22 two 2-ors into 2-nand with 1x drive oa22d2 two 2-ors into 2-nand with 2x drive oa22d2b two 2-ors into 2-nand with 2x(buffered) drive oa22d4 two 2-ors into 2-nand with 4x drive oa22dha 2-or and 2-nand into 2-nand with 0.5x drive oa22a 2-or and 2-nand into 2-nand with 1x drive oa22d2a 2-or and 2-nand into 2-nand with 2x drive oa22d4a 2-or and 2-nand into 2-nand with 4x drive oa221 two 2-ors into 3-nand with 1x drive oa221d2 two 2-ors into 3-nand with 2x drive oa221d4 two 2-ors into 3-nand with 4x drive oa222 three 2-ors into 3-nand with 1x drive oa222d2 three 2-ors into 3-nand with 2x drive oa222d2b three 2-ors into 3-nand with 2x(buffered) drive oa222d4 three 2-ors into 3-nand with 4x drive oa2222 four 2-ors into 4-nand with 1x drive oa2222d2 four 2-ors into 4-nand with 2x drive oa2222d4 four 2-ors into 4-nand with 4x drive cell name function description
STD111 3-12 samsung asic logic cells cell names & function descriptions (continued) oa31dh 3-or into 2-nand with 0.5x drive oa31 3-or into 2-nand with 1x drive oa31d2 3-or into 2-nand with 2x drive oa31d4 3-or into 2-nand with 4x drive oa311 3-or into 3-nand with 1x drive oa311d2 3-or into 3-nand with 2x drive oa311d4 3-or into 3-nand with 4x drive oa3111 3-or into 4-nand with 1x drive oa3111d2 3-or into 4-nand with 2x drive oa32 3-or and 2-or into 2-nand with 1x drive oa32d2 3-or and 2-or into 2-nand with 2x drive oa32d4 3-or and 2-or into 2-nand with 4x drive oa321 3-or and 2-or into 3-nand with 1x drive oa321d2 3-or and 2-or into 3-nand with 2x drive oa321d4 3-or and 2-or into 3-nand with 4x drive oa322 3-or and two 2-ors into 3-nand with 1x drive oa322d2 3-or and two 2-ors into 3-nand with 2x drive oa322d4 3-or and two 2-ors into 3-nand with 4x drive oa33 two 3-ors into 2-nand with 1x drive oa33d2 two 3-ors into 2-nand with 2x drive oa33d4 two 3-ors into 2-nand with 4x drive oa331 two 3-ors into 3-nand with 1x drive oa331d2 two 3-ors into 3-nand with 2x drive oa331d4 two 3-ors into 3-nand with 4x drive oa332 two 3-ors and 2-or into 3-nand with 1x drive oa332d2 two 3-ors and 2-or into 3-nand with 2x drive oa332d4 two 3-ors and 2-or into 3-nand with 4x drive oa4111 4-or into 4-nand with 1x drive oa4111d2 4-or into 4-nand with 2x drive scg1 2-nand and two (2-and into 2-nor)s into 3-nand scg1d2 2-nand and two (2-and into 2-nor)s into 3-nand with 2x drive scg2 two 2-ands into 2-or scg2d2 two 2-ands into 2-or with 2x drive scg3 two 2-nands into 3-nand scg3d2 two 2-nands into 3-nand with 2x drive scg4 two (two 2-ands into 2-nor)s into 2-nand scg4d2 two (two 2-ands into 2-nor)s into 2-nand with 2x drive cell name function description
samsung asic 3-13 STD111 logic cells cell names & function descriptions (continued) scg5 three 2-ands into 3-or scg5d2 three 2-ands into 3-or with 2x drive scg6 2-and into 2-or scg6d2 2-and into 2-or with 2x drive scg7 2-nand and (2-and into 2-nor) into 2-nand scg7d2 2-nand and (2-and into 2-nor) into 2-nand with 2x drive scg8 2-and into 3-or scg8d2 2-and into 3-or with 2x drive scg9 2-or into 2-and scg9d2 2-or into 2-and with 2x drive scg10 two 2-ors into 2-and scg10d2 two 2-ors into 2-and with 2x drive scg11 two 2-nors into 3-nor scg11d2 two 2-nors into 3-nor with 2x drive scg12 2-nand into 2-nor scg12d2 2-nand into 2-nor with 2x drive scg13 2-nor into 2-nand scg13d2 2-nor into 2-nand with 2x drive scg14 2-nand into 2-nand scg14d2 2-nand into 2-nand with 2x drive scg15 2-nand into 3-nand scg15d2 2-nand into 3-nand with 2x drive scg16 2-or with one inverted input into 2-nand scg16d2 2-or with one inverted input into 2-nand with 2x drive scg17 2-and into 2-nor into 2-nand scg17d2 2-and into 2-nor into 2-nand with 2x drive scg18 2-and into 2-nor into 3-nand scg18d2 2-and into 2-nor into 3-nand with 2x drive scg19 2-and into 2-and into 2-nor scg19d2 2-and into 2-and into 2-nor with 2x drive scg20 2-nor into 2-nor scg20d2 2-nor into 2-nor with 2x drive scg21 2-nor into 3-nor scg21d2 2-nor into 3-nor with 2x drive scg22 2-nand into 2-or into 2-nand scg22d2 2-nand into 2-or into 2-nand with 2x drive scg23 full adder with one inverted input with 1x drive scg23d2 full adder with one inverted input with 2x drive cell name function description
STD111 3-14 samsung asic logic cells cell names & function descriptions (continued) dl1d2 1ns delay cell with 2x drive dl1d4 1ns delay cell with 4x drive dl2d2 2ns delay cell with 2x drive dl2d4 2ns delay cell with 4x drive dl3d2 3ns delay cell with 2x drive dl3d4 3ns delay cell with 4x drive dl4d2 4ns delay cell with 2x drive dl4d4 4ns delay cell with 4x drive dl5d2 5ns delay cell with 2x drive dl5d4 5ns delay cell with 4x drive dl10d2 10ns delay cell with 2x drive dl10d4 10ns delay cell with 4x drive ivdh inverter with 0.5x drive iv inverter with 1x drive ivd2 inverter with 2x drive ivd3 inverter with 3x drive ivd4 inverter with 4x drive ivd6 inverter with 6x drive ivd8 inverter with 8x drive ivd16 inverter with 16x drive ivcd11 1x inverter into 1x inverter ivcd13 1x inverter into 3x inverter ivcd22 2x inverter into 2x inverter ivcd26 2x inverter into 6x inverter ivcd44 4x inverter into 4x inverter ivt inverting tri-state buffer with enable high, 1x drive ivtd2 inverting tri-state buffer with enable high, 2x drive ivtd4 inverting tri-state buffer with enable high, 4x drive ivtd8 inverting tri-state buffer with enable high, 8x drive ivtd16 inverting tri-state buffer with enable high, 16x drive ivtn inverting tri-state buffer with enable low, 1x drive ivtnd2 inverting tri-state buffer with enable low, 2x drive ivtnd4 inverting tri-state buffer with enable low, 4x drive ivtnd8 inverting tri-state buffer with enable low, 8x drive ivtnd16 inverting tri-state buffer with enable low, 16x drive nidh non-inverting buffer with 0.5x drive nid non-inverting buffer with 1x drive nid2 non-inverting buffer with 2x drive cell name function description
samsung asic 3-15 STD111 logic cells cell names & function descriptions (continued) nid3 non-inverting buffer with 3x drive nid4 non-inverting buffer with 4x drive nid6 non-inverting buffer with 6x drive nid8 non-inverting buffer with 8x drive nid16 non-inverting buffer with 16x drive oak_nid10p clock buffer for 10pf drive (for oak core only) oak_nid20p clock buffer for 20pf drive (for oak core only) nit non-inverting tri-state buffer with enable high, 1x drive nitd2 non-inverting tri-state buffer with enable high, 2x drive nitd4 non-inverting tri-state buffer with enable high, 4x drive nitd8 non-inverting tri-state buffer with enable high, 8x drive nitd16 non-inverting tri-state buffer with enable high, 16x drive nitn non-inverting tri-state buffer with enable low, 1x drive nitnd2 non-inverting tri-state buffer with enable low, 2x drive nitnd4 non-inverting tri-state buffer with enable low, 4x drive nitnd8 non-inverting tri-state buffer with enable low, 8x drive nitnd16 non-inverting tri-state buffer with enable low, 16x drive oak_duclk10 2 phase clock generator (1ns non-overlapped, for oak core only) oak_duclk16 2 phase clock generator (1.6ns non-overlapped, for oak core only) ctsb clock tree synthesis buffer with 1x drive ctsbd2 clock tree synthesis buffer with 2x drive ctsbd3 clock tree synthesis buffer with 3x drive ctsbd4 clock tree synthesis buffer with 4x drive ctsbd6 clock tree synthesis buffer with 6x drive ctsbd8 clock tree synthesis buffer with 8x drive ctsbd16 clock tree synthesis buffer with 16x drive cell name function description
STD111 3-16 samsung asic note
samsung asic 3-17 STD111 ad2dh/ad2/ad2d2/ad2d4 2-input and with 0.5x/1x/2x/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ad2dh ad2 input load (sl) gate count ad2dh ad2 ad2d2 ad2d 4 ad2dh ad2 ad2d2 ad2d4 abababab 0.4 0.4 0.7 0.7 0.8 0.9 1.0 1.0 1.33 1.33 1.67 2.33 a b y path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.175 0.062 + 0.057*sl 0.054 + 0.059*sl 0.046 + 0.060*sl t f 0.149 0.056 + 0.047*sl 0.050 + 0.048*sl 0.040 + 0.049*sl t plh 0.181 0.126 + 0.028*sl 0.133 + 0.026*sl 0.134 + 0.026*sl t phl 0.194 0.138 + 0.028*sl 0.147 + 0.026*sl 0.149 + 0.026*sl b to y t r 0.176 0.062 + 0.057*sl 0.055 + 0.059*sl 0.046 + 0.060*sl t f 0.152 0.059 + 0.046*sl 0.053 + 0.048*sl 0.042 + 0.049*sl t plh 0.177 0.122 + 0.028*sl 0.129 + 0.026*sl 0.130 + 0.026*sl t phl 0.210 0.153 + 0.028*sl 0.162 + 0.026*sl 0.165 + 0.026*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.109 0.057 + 0.026*sl 0.053 + 0.027*sl 0.046 + 0.028*sl t f 0.099 0.059 + 0.020*sl 0.047 + 0.023*sl 0.042 + 0.024*sl t plh 0.139 0.110 + 0.014*sl 0.117 + 0.013*sl 0.120 + 0.012*sl t phl 0.152 0.123 + 0.015*sl 0.130 + 0.013*sl 0.134 + 0.012*sl b to y t r 0.108 0.055 + 0.027*sl 0.053 + 0.027*sl 0.045 + 0.028*sl t f 0.097 0.053 + 0.022*sl 0.051 + 0.023*sl 0.044 + 0.024*sl t plh 0.134 0.105 + 0.014*sl 0.112 + 0.013*sl 0.115 + 0.012*sl t phl 0.167 0.136 + 0.015*sl 0.145 + 0.013*sl 0.149 + 0.012*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table aby 000 010 100 111
STD111 3-18 samsung asic ad2dh/ad2/ad2d2/ad2d4 2-input and with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ad2d2 ad2d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.083 0.057 + 0.013*sl 0.056 + 0.014*sl 0.049 + 0.014*sl t f 0.073 0.051 + 0.011*sl 0.049 + 0.011*sl 0.045 + 0.012*sl t plh 0.142 0.125 + 0.008*sl 0.131 + 0.007*sl 0.140 + 0.006*sl t phl 0.148 0.131 + 0.009*sl 0.138 + 0.007*sl 0.148 + 0.006*sl b to y t r 0.083 0.056 + 0.013*sl 0.055 + 0.014*sl 0.049 + 0.014*sl t f 0.076 0.052 + 0.012*sl 0.054 + 0.011*sl 0.048 + 0.012*sl t plh 0.135 0.119 + 0.008*sl 0.125 + 0.007*sl 0.134 + 0.006*sl t phl 0.161 0.143 + 0.009*sl 0.150 + 0.007*sl 0.161 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.080 0.066 + 0.007*sl 0.066 + 0.007*sl 0.062 + 0.007*sl t f 0.071 0.057 + 0.007*sl 0.061 + 0.006*sl 0.060 + 0.006*sl t plh 0.161 0.150 + 0.005*sl 0.156 + 0.004*sl 0.172 + 0.003*sl t phl 0.167 0.157 + 0.005*sl 0.162 + 0.004*sl 0.180 + 0.003*sl b to y t r 0.083 0.073 + 0.005*sl 0.067 + 0.007*sl 0.062 + 0.007*sl t f 0.077 0.063 + 0.007*sl 0.067 + 0.006*sl 0.063 + 0.006*sl t plh 0.154 0.143 + 0.005*sl 0.149 + 0.004*sl 0.166 + 0.003*sl t phl 0.179 0.167 + 0.006*sl 0.174 + 0.004*sl 0.192 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-19 STD111 ad3dh/ad3/ad3d2/ad3d4 3-input and with 0.5x/1x/2x/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ad3dh ad3 input load (sl) gate count ad3dh ad3 ad3d2 ad3d4 ad3dh ad3 ad3d2 ad3d4 abcabcabcabc 0.3 0.3 0.3 0.6 0.6 0.7 0.7 0.8 0.8 0.8 0.9 0.9 1.67 1.67 2.00 2.33 a b c y path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.192 0.078 + 0.057*sl 0.076 + 0.058*sl 0.064 + 0.059*sl t f 0.162 0.069 + 0.047*sl 0.066 + 0.048*sl 0.053 + 0.049*sl t plh 0.221 0.161 + 0.030*sl 0.175 + 0.026*sl 0.181 + 0.026*sl t phl 0.231 0.172 + 0.030*sl 0.186 + 0.026*sl 0.191 + 0.026*sl b to y t r 0.194 0.080 + 0.057*sl 0.076 + 0.058*sl 0.064 + 0.059*sl t f 0.167 0.075 + 0.046*sl 0.070 + 0.047*sl 0.056 + 0.049*sl t plh 0.223 0.163 + 0.030*sl 0.177 + 0.026*sl 0.183 + 0.026*sl t phl 0.249 0.189 + 0.030*sl 0.203 + 0.026*sl 0.210 + 0.026*sl c to y t r 0.193 0.080 + 0.057*sl 0.076 + 0.058*sl 0.063 + 0.059*sl t f 0.173 0.081 + 0.046*sl 0.076 + 0.047*sl 0.062 + 0.049*sl t plh 0.224 0.164 + 0.030*sl 0.178 + 0.026*sl 0.183 + 0.026*sl t phl 0.266 0.205 + 0.031*sl 0.221 + 0.026*sl 0.228 + 0.026*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.123 0.069 + 0.027*sl 0.068 + 0.027*sl 0.064 + 0.028*sl t f 0.103 0.056 + 0.024*sl 0.060 + 0.023*sl 0.054 + 0.023*sl t plh 0.171 0.139 + 0.016*sl 0.149 + 0.013*sl 0.158 + 0.012*sl t phl 0.180 0.149 + 0.016*sl 0.158 + 0.013*sl 0.166 + 0.013*sl b to y t r 0.126 0.075 + 0.026*sl 0.070 + 0.027*sl 0.064 + 0.028*sl t f 0.107 0.061 + 0.023*sl 0.063 + 0.022*sl 0.056 + 0.023*sl t plh 0.173 0.140 + 0.016*sl 0.151 + 0.013*sl 0.160 + 0.012*sl t phl 0.194 0.162 + 0.016*sl 0.172 + 0.013*sl 0.180 + 0.013*sl c to y t r 0.123 0.070 + 0.027*sl 0.068 + 0.027*sl 0.063 + 0.028*sl t f 0.112 0.066 + 0.023*sl 0.068 + 0.022*sl 0.061 + 0.023*sl t plh 0.172 0.140 + 0.016*sl 0.150 + 0.013*sl 0.159 + 0.012*sl t phl 0.208 0.176 + 0.016*sl 0.186 + 0.014*sl 0.196 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table abcy 0xx0 x0x0 xx00 1111
STD111 3-20 samsung asic ad3dh/ad3/ad3d2/ad3d4 3-input and with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ad3d2 ad3d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.098 0.070 + 0.014*sl 0.071 + 0.014*sl 0.070 + 0.014*sl t f 0.083 0.057 + 0.013*sl 0.063 + 0.011*sl 0.059 + 0.012*sl t plh 0.175 0.156 + 0.010*sl 0.164 + 0.007*sl 0.180 + 0.006*sl t phl 0.178 0.159 + 0.010*sl 0.168 + 0.007*sl 0.183 + 0.006*sl b to y t r 0.100 0.072 + 0.014*sl 0.074 + 0.013*sl 0.070 + 0.014*sl t f 0.087 0.062 + 0.012*sl 0.066 + 0.011*sl 0.062 + 0.012*sl t plh 0.177 0.158 + 0.010*sl 0.166 + 0.007*sl 0.182 + 0.006*sl t phl 0.191 0.171 + 0.010*sl 0.180 + 0.007*sl 0.196 + 0.006*sl c to y t r 0.100 0.072 + 0.014*sl 0.073 + 0.014*sl 0.070 + 0.014*sl t f 0.094 0.069 + 0.012*sl 0.073 + 0.011*sl 0.068 + 0.011*sl t plh 0.175 0.156 + 0.010*sl 0.164 + 0.007*sl 0.180 + 0.006*sl t phl 0.204 0.183 + 0.010*sl 0.193 + 0.007*sl 0.210 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.105 0.092 + 0.006*sl 0.090 + 0.007*sl 0.090 + 0.007*sl t f 0.088 0.076 + 0.006*sl 0.077 + 0.006*sl 0.079 + 0.006*sl t plh 0.204 0.192 + 0.006*sl 0.199 + 0.004*sl 0.222 + 0.003*sl t phl 0.204 0.192 + 0.006*sl 0.199 + 0.004*sl 0.222 + 0.003*sl b to y t r 0.104 0.091 + 0.007*sl 0.091 + 0.007*sl 0.090 + 0.007*sl t f 0.094 0.080 + 0.007*sl 0.085 + 0.006*sl 0.085 + 0.006*sl t plh 0.206 0.194 + 0.006*sl 0.201 + 0.004*sl 0.224 + 0.003*sl t phl 0.218 0.205 + 0.006*sl 0.213 + 0.004*sl 0.238 + 0.003*sl c to y t r 0.105 0.092 + 0.006*sl 0.090 + 0.007*sl 0.090 + 0.007*sl t f 0.099 0.087 + 0.006*sl 0.089 + 0.006*sl 0.090 + 0.006*sl t plh 0.205 0.193 + 0.006*sl 0.200 + 0.004*sl 0.223 + 0.003*sl t phl 0.228 0.215 + 0.006*sl 0.223 + 0.004*sl 0.249 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-21 STD111 ad4dh/ad4/ad4d2/ad4d4 4-input and with 0.5x/1x/2x/4x drive logic symbol cell data input load (sl) ad4dh ad4 ad4d2 ad4d 4 abcdabcdabcdabcd 0.3 0.3 0.3 0.3 0.6 0.6 0.6 0.6 0.7 0.7 0.7 0.7 0.8 0.8 0.8 0.8 gate counts ad4dh ad4 ad4d2 ad4d 4 2.00 2.00 2.00 2.67 a b c y d truth table abcdy 0xxx0 x0xx0 xx0x0 xxx00 11111
STD111 3-22 samsung asic ad4dh/ad4/ad4d2/ad4d4 4-input and with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ad4dh ad4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.210 0.095 + 0.058*sl 0.095 + 0.057*sl 0.084 + 0.059*sl t f 0.169 0.075 + 0.047*sl 0.072 + 0.047*sl 0.060 + 0.049*sl t plh 0.252 0.187 + 0.032*sl 0.205 + 0.027*sl 0.219 + 0.026*sl t phl 0.248 0.187 + 0.031*sl 0.202 + 0.026*sl 0.210 + 0.026*sl b to y t r 0.210 0.095 + 0.058*sl 0.096 + 0.057*sl 0.084 + 0.059*sl t f 0.174 0.081 + 0.047*sl 0.079 + 0.047*sl 0.064 + 0.049*sl t plh 0.262 0.198 + 0.032*sl 0.216 + 0.027*sl 0.229 + 0.026*sl t phl 0.268 0.206 + 0.031*sl 0.223 + 0.027*sl 0.231 + 0.026*sl c to y t r 0.211 0.096 + 0.057*sl 0.096 + 0.057*sl 0.084 + 0.059*sl t f 0.181 0.089 + 0.046*sl 0.085 + 0.047*sl 0.070 + 0.048*sl t plh 0.268 0.204 + 0.032*sl 0.222 + 0.027*sl 0.236 + 0.026*sl t phl 0.285 0.222 + 0.031*sl 0.240 + 0.027*sl 0.250 + 0.026*sl d to y t r 0.210 0.095 + 0.058*sl 0.095 + 0.057*sl 0.084 + 0.059*sl t f 0.187 0.095 + 0.046*sl 0.093 + 0.047*sl 0.077 + 0.048*sl t plh 0.273 0.209 + 0.032*sl 0.227 + 0.027*sl 0.241 + 0.026*sl t phl 0.302 0.237 + 0.032*sl 0.257 + 0.027*sl 0.269 + 0.026*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.135 0.079 + 0.028*sl 0.082 + 0.027*sl 0.079 + 0.027*sl t f 0.108 0.061 + 0.024*sl 0.065 + 0.022*sl 0.058 + 0.023*sl t plh 0.190 0.156 + 0.017*sl 0.167 + 0.014*sl 0.181 + 0.013*sl t phl 0.193 0.161 + 0.016*sl 0.171 + 0.014*sl 0.180 + 0.013*sl b to y t r 0.136 0.081 + 0.028*sl 0.083 + 0.027*sl 0.080 + 0.027*sl t f 0.113 0.067 + 0.023*sl 0.071 + 0.022*sl 0.063 + 0.023*sl t plh 0.199 0.166 + 0.017*sl 0.177 + 0.014*sl 0.190 + 0.013*sl t phl 0.212 0.179 + 0.016*sl 0.190 + 0.014*sl 0.200 + 0.013*sl c to y t r 0.136 0.081 + 0.027*sl 0.082 + 0.027*sl 0.080 + 0.027*sl t f 0.120 0.074 + 0.023*sl 0.076 + 0.022*sl 0.069 + 0.023*sl t plh 0.205 0.171 + 0.017*sl 0.182 + 0.014*sl 0.195 + 0.013*sl t phl 0.228 0.195 + 0.017*sl 0.206 + 0.014*sl 0.218 + 0.013*sl d to y t r 0.136 0.080 + 0.028*sl 0.084 + 0.027*sl 0.079 + 0.027*sl t f 0.127 0.082 + 0.023*sl 0.084 + 0.022*sl 0.076 + 0.023*sl t plh 0.208 0.174 + 0.017*sl 0.185 + 0.014*sl 0.199 + 0.013*sl t phl 0.243 0.208 + 0.017*sl 0.220 + 0.014*sl 0.234 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-23 STD111 ad4dh/ad4/ad4d2/ad4d4 4-input and with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ad4d2 ad4d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.112 0.084 + 0.014*sl 0.084 + 0.014*sl 0.086 + 0.014*sl t f 0.089 0.063 + 0.013*sl 0.069 + 0.011*sl 0.066 + 0.012*sl t plh 0.194 0.173 + 0.011*sl 0.184 + 0.008*sl 0.204 + 0.007*sl t phl 0.195 0.174 + 0.010*sl 0.184 + 0.008*sl 0.202 + 0.006*sl b to y t r 0.113 0.086 + 0.014*sl 0.086 + 0.014*sl 0.086 + 0.014*sl t f 0.097 0.072 + 0.012*sl 0.076 + 0.011*sl 0.072 + 0.012*sl t plh 0.204 0.183 + 0.011*sl 0.193 + 0.008*sl 0.213 + 0.007*sl t phl 0.213 0.192 + 0.011*sl 0.202 + 0.008*sl 0.221 + 0.006*sl c to y t r 0.113 0.086 + 0.014*sl 0.086 + 0.014*sl 0.086 + 0.014*sl t f 0.101 0.077 + 0.012*sl 0.080 + 0.011*sl 0.077 + 0.011*sl t plh 0.209 0.188 + 0.011*sl 0.198 + 0.008*sl 0.219 + 0.007*sl t phl 0.224 0.202 + 0.011*sl 0.214 + 0.008*sl 0.234 + 0.007*sl d to y t r 0.113 0.086 + 0.014*sl 0.085 + 0.014*sl 0.087 + 0.014*sl t f 0.108 0.084 + 0.012*sl 0.087 + 0.011*sl 0.085 + 0.011*sl t plh 0.212 0.191 + 0.011*sl 0.201 + 0.008*sl 0.222 + 0.007*sl t phl 0.237 0.215 + 0.011*sl 0.227 + 0.008*sl 0.248 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.127 0.114 + 0.007*sl 0.112 + 0.007*sl 0.113 + 0.007*sl t f 0.099 0.088 + 0.006*sl 0.087 + 0.006*sl 0.091 + 0.006*sl t plh 0.233 0.220 + 0.007*sl 0.228 + 0.004*sl 0.255 + 0.003*sl t phl 0.226 0.213 + 0.006*sl 0.221 + 0.004*sl 0.246 + 0.003*sl b to y t r 0.127 0.114 + 0.007*sl 0.113 + 0.007*sl 0.114 + 0.007*sl t f 0.106 0.092 + 0.007*sl 0.097 + 0.006*sl 0.099 + 0.006*sl t plh 0.243 0.230 + 0.007*sl 0.238 + 0.004*sl 0.265 + 0.003*sl t phl 0.242 0.229 + 0.007*sl 0.237 + 0.004*sl 0.264 + 0.003*sl c to y t r 0.127 0.115 + 0.006*sl 0.112 + 0.007*sl 0.112 + 0.007*sl t f 0.114 0.100 + 0.007*sl 0.104 + 0.006*sl 0.106 + 0.006*sl t plh 0.248 0.235 + 0.007*sl 0.243 + 0.004*sl 0.271 + 0.003*sl t phl 0.257 0.243 + 0.007*sl 0.252 + 0.005*sl 0.281 + 0.003*sl d to y t r 0.127 0.114 + 0.007*sl 0.112 + 0.007*sl 0.113 + 0.007*sl t f 0.121 0.107 + 0.007*sl 0.111 + 0.006*sl 0.113 + 0.006*sl t plh 0.251 0.238 + 0.007*sl 0.246 + 0.004*sl 0.274 + 0.003*sl t phl 0.271 0.257 + 0.007*sl 0.266 + 0.005*sl 0.296 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-24 samsung asic ad5/ad5d2/ad5d4 5-input and with 1x/2x/4xdrive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ad5 input load (sl) ad5 ad5d2 ad5d4 abcdeabcdeabcde 0.6 0.6 0.6 0.6 0.7 0.6 0.7 0.7 0.7 0.7 0.6 0.6 0.6 0.6 0.7 gate count ad5 ad5d2 ad5d4 2.67 3.00 4.33 b c d y e a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.211 0.104 + 0.054*sl 0.101 + 0.054*sl 0.094 + 0.055*sl t f 0.110 0.065 + 0.022*sl 0.068 + 0.022*sl 0.062 + 0.022*sl t plh 0.193 0.142 + 0.025*sl 0.147 + 0.024*sl 0.149 + 0.024*sl t phl 0.200 0.168 + 0.016*sl 0.178 + 0.013*sl 0.189 + 0.012*sl b to y t r 0.212 0.106 + 0.053*sl 0.101 + 0.054*sl 0.094 + 0.055*sl t f 0.117 0.073 + 0.022*sl 0.074 + 0.021*sl 0.068 + 0.022*sl t plh 0.196 0.145 + 0.025*sl 0.151 + 0.024*sl 0.153 + 0.024*sl t phl 0.222 0.189 + 0.016*sl 0.201 + 0.013*sl 0.213 + 0.012*sl c to y t r 0.211 0.104 + 0.053*sl 0.101 + 0.054*sl 0.094 + 0.055*sl t f 0.125 0.082 + 0.022*sl 0.084 + 0.021*sl 0.077 + 0.022*sl t plh 0.195 0.144 + 0.026*sl 0.150 + 0.024*sl 0.152 + 0.024*sl t phl 0.242 0.207 + 0.017*sl 0.221 + 0.014*sl 0.234 + 0.012*sl d to y t r 0.203 0.095 + 0.054*sl 0.092 + 0.055*sl 0.089 + 0.055*sl t f 0.123 0.082 + 0.021*sl 0.079 + 0.022*sl 0.072 + 0.022*sl t plh 0.175 0.125 + 0.025*sl 0.130 + 0.024*sl 0.132 + 0.024*sl t phl 0.191 0.162 + 0.014*sl 0.169 + 0.013*sl 0.175 + 0.012*sl e to y t r 0.203 0.095 + 0.054*sl 0.093 + 0.055*sl 0.088 + 0.055*sl t f 0.128 0.086 + 0.021*sl 0.083 + 0.021*sl 0.076 + 0.022*sl t plh 0.173 0.123 + 0.025*sl 0.127 + 0.024*sl 0.129 + 0.024*sl t phl 0.209 0.180 + 0.015*sl 0.187 + 0.013*sl 0.194 + 0.012*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table abcdey 0xxxx0 x0xxx0 xx0xx0 xxx0x0 xxxx00 111111
samsung asic 3-25 STD111 ad5/ad5d2/ad5d4 5-input and with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ad5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.154 0.099 + 0.027*sl 0.101 + 0.027*sl 0.091 + 0.027*sl t f 0.099 0.075 + 0.012*sl 0.079 + 0.011*sl 0.078 + 0.011*sl t plh 0.192 0.165 + 0.014*sl 0.170 + 0.012*sl 0.177 + 0.012*sl t phl 0.213 0.192 + 0.010*sl 0.202 + 0.008*sl 0.222 + 0.006*sl b to y t r 0.153 0.099 + 0.027*sl 0.100 + 0.027*sl 0.091 + 0.027*sl t f 0.106 0.082 + 0.012*sl 0.086 + 0.011*sl 0.083 + 0.011*sl t plh 0.195 0.168 + 0.014*sl 0.173 + 0.012*sl 0.180 + 0.012*sl t phl 0.228 0.207 + 0.011*sl 0.218 + 0.008*sl 0.240 + 0.006*sl c to y t r 0.154 0.100 + 0.027*sl 0.101 + 0.027*sl 0.090 + 0.027*sl t f 0.113 0.088 + 0.012*sl 0.093 + 0.011*sl 0.091 + 0.011*sl t plh 0.193 0.165 + 0.014*sl 0.171 + 0.012*sl 0.178 + 0.012*sl t phl 0.245 0.222 + 0.011*sl 0.235 + 0.008*sl 0.258 + 0.006*sl d to y t r 0.143 0.089 + 0.027*sl 0.088 + 0.027*sl 0.083 + 0.028*sl t f 0.116 0.093 + 0.011*sl 0.095 + 0.011*sl 0.090 + 0.011*sl t plh 0.171 0.144 + 0.014*sl 0.149 + 0.012*sl 0.155 + 0.012*sl t phl 0.208 0.190 + 0.009*sl 0.197 + 0.007*sl 0.212 + 0.006*sl e to y t r 0.142 0.089 + 0.027*sl 0.087 + 0.027*sl 0.082 + 0.028*sl t f 0.124 0.100 + 0.012*sl 0.104 + 0.011*sl 0.097 + 0.011*sl t plh 0.166 0.139 + 0.014*sl 0.144 + 0.012*sl 0.151 + 0.012*sl t phl 0.227 0.209 + 0.009*sl 0.217 + 0.007*sl 0.233 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-26 samsung asic ad5/ad5d2/ad5d4 5-input and with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ad5d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.072 0.059 + 0.006*sl 0.058 + 0.007*sl 0.048 + 0.007*sl t f 0.064 0.051 + 0.006*sl 0.053 + 0.006*sl 0.049 + 0.006*sl t plh 0.313 0.304 + 0.005*sl 0.308 + 0.003*sl 0.319 + 0.003*sl t phl 0.309 0.298 + 0.005*sl 0.304 + 0.004*sl 0.319 + 0.003*sl b to y t r 0.072 0.059 + 0.007*sl 0.058 + 0.007*sl 0.048 + 0.007*sl t f 0.064 0.051 + 0.006*sl 0.053 + 0.006*sl 0.049 + 0.006*sl t plh 0.317 0.307 + 0.005*sl 0.312 + 0.003*sl 0.322 + 0.003*sl t phl 0.332 0.321 + 0.005*sl 0.327 + 0.004*sl 0.342 + 0.003*sl c to y t r 0.072 0.059 + 0.006*sl 0.059 + 0.007*sl 0.048 + 0.007*sl t f 0.064 0.053 + 0.006*sl 0.052 + 0.006*sl 0.049 + 0.006*sl t plh 0.316 0.306 + 0.005*sl 0.311 + 0.003*sl 0.321 + 0.003*sl t phl 0.351 0.341 + 0.005*sl 0.346 + 0.004*sl 0.361 + 0.003*sl d to y t r 0.072 0.058 + 0.007*sl 0.059 + 0.007*sl 0.048 + 0.007*sl t f 0.063 0.049 + 0.007*sl 0.053 + 0.006*sl 0.049 + 0.006*sl t plh 0.298 0.288 + 0.005*sl 0.293 + 0.003*sl 0.303 + 0.003*sl t phl 0.303 0.292 + 0.005*sl 0.298 + 0.004*sl 0.313 + 0.003*sl e to y t r 0.072 0.059 + 0.007*sl 0.059 + 0.007*sl 0.048 + 0.007*sl t f 0.063 0.049 + 0.007*sl 0.054 + 0.006*sl 0.049 + 0.006*sl t plh 0.295 0.285 + 0.005*sl 0.290 + 0.003*sl 0.301 + 0.003*sl t phl 0.324 0.313 + 0.005*sl 0.319 + 0.004*sl 0.334 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-27 STD111 nd2dh/nd2/nd2d2/nd2d4 2-input nand with 0.5x/1x/2x/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nd2dh nd2 input load (sl) gate count nd2dh nd2 nd2d2 nd2d4 nd2dh nd2 nd2d2 nd2d4 abababab 0.5 0.5 1.0 1.0 2.0 2.0 4.1 4.0 1.00 1.00 1.67 2.67 a b y path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.221 0.083 + 0.069*sl 0.065 + 0.074*sl 0.047 + 0.076*sl t f 0.212 0.087 + 0.062*sl 0.068 + 0.067*sl 0.047 + 0.069*sl t plh 0.132 0.066 + 0.033*sl 0.068 + 0.032*sl 0.067 + 0.033*sl t phl 0.123 0.055 + 0.034*sl 0.059 + 0.033*sl 0.058 + 0.033*sl b to y t r 0.239 0.101 + 0.069*sl 0.083 + 0.074*sl 0.064 + 0.076*sl t f 0.205 0.078 + 0.063*sl 0.060 + 0.068*sl 0.048 + 0.069*sl t plh 0.143 0.078 + 0.032*sl 0.078 + 0.032*sl 0.077 + 0.032*sl t phl 0.117 0.049 + 0.034*sl 0.053 + 0.033*sl 0.052 + 0.033*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.145 0.086 + 0.029*sl 0.075 + 0.032*sl 0.058 + 0.034*sl t f 0.144 0.087 + 0.028*sl 0.078 + 0.031*sl 0.060 + 0.033*sl t plh 0.090 0.055 + 0.018*sl 0.065 + 0.015*sl 0.065 + 0.015*sl t phl 0.084 0.046 + 0.019*sl 0.058 + 0.016*sl 0.057 + 0.016*sl b to y t r 0.162 0.104 + 0.029*sl 0.091 + 0.032*sl 0.074 + 0.034*sl t f 0.136 0.078 + 0.029*sl 0.067 + 0.032*sl 0.055 + 0.033*sl t plh 0.102 0.069 + 0.016*sl 0.075 + 0.015*sl 0.074 + 0.015*sl t phl 0.078 0.042 + 0.018*sl 0.050 + 0.016*sl 0.051 + 0.016*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table aby 001 011 101 110
STD111 3-28 samsung asic nd2dh/nd2/nd2d2/nd2d4 2-input nand with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nd2d2 nd2d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.115 0.087 + 0.014*sl 0.081 + 0.016*sl 0.063 + 0.017*sl t f 0.115 0.085 + 0.015*sl 0.084 + 0.015*sl 0.064 + 0.016*sl t plh 0.072 0.052 + 0.010*sl 0.061 + 0.008*sl 0.066 + 0.007*sl t phl 0.065 0.044 + 0.011*sl 0.054 + 0.008*sl 0.058 + 0.008*sl b to y t r 0.132 0.105 + 0.014*sl 0.097 + 0.016*sl 0.079 + 0.017*sl t f 0.107 0.078 + 0.014*sl 0.075 + 0.015*sl 0.057 + 0.016*sl t plh 0.086 0.068 + 0.009*sl 0.073 + 0.008*sl 0.074 + 0.007*sl t phl 0.060 0.041 + 0.010*sl 0.047 + 0.008*sl 0.051 + 0.008*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.100 0.084 + 0.008*sl 0.085 + 0.008*sl 0.063 + 0.008*sl t f 0.099 0.083 + 0.008*sl 0.086 + 0.007*sl 0.065 + 0.008*sl t plh 0.060 0.049 + 0.006*sl 0.055 + 0.004*sl 0.065 + 0.004*sl t phl 0.054 0.042 + 0.006*sl 0.048 + 0.004*sl 0.058 + 0.004*sl b to y t r 0.117 0.102 + 0.007*sl 0.102 + 0.008*sl 0.080 + 0.008*sl t f 0.093 0.079 + 0.007*sl 0.077 + 0.008*sl 0.057 + 0.008*sl t plh 0.075 0.065 + 0.005*sl 0.069 + 0.004*sl 0.074 + 0.004*sl t phl 0.050 0.039 + 0.005*sl 0.044 + 0.004*sl 0.051 + 0.004*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-29 STD111 nd3dh/nd3/nd3d2/nd3d4 3-input nand with 0.5x/1x/2x/4x drive logic symbol cell data input load (sl) nd3dh nd3 nd3d2 nd3d4 abcabcabcabc 0.4 0.4 0.5 0.8 0.9 0.9 1.7 1.8 1.7 3.6 3.6 3.6 gate count nd3dh nd3 nd3d2 nd3d4 1.33 1.33 2.33 4.00 a b c y truth table abcy 0xx1 x0x1 xx01 1110
STD111 3-30 samsung asic nd3dh/nd3/nd3d2/nd3d4 3-input nand with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nd3dh nd3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.297 0.107 + 0.095*sl 0.088 + 0.100*sl 0.079 + 0.101*sl t f 0.306 0.120 + 0.093*sl 0.102 + 0.098*sl 0.089 + 0.099*sl t plh 0.171 0.084 + 0.043*sl 0.084 + 0.044*sl 0.083 + 0.044*sl t phl 0.162 0.071 + 0.045*sl 0.070 + 0.045*sl 0.069 + 0.046*sl b to y t r 0.319 0.128 + 0.096*sl 0.110 + 0.100*sl 0.101 + 0.101*sl t f 0.302 0.113 + 0.095*sl 0.100 + 0.098*sl 0.089 + 0.099*sl t plh 0.185 0.099 + 0.043*sl 0.098 + 0.043*sl 0.097 + 0.044*sl t phl 0.164 0.073 + 0.046*sl 0.074 + 0.046*sl 0.073 + 0.046*sl c to y t r 0.344 0.153 + 0.095*sl 0.134 + 0.100*sl 0.124 + 0.101*sl t f 0.298 0.106 + 0.096*sl 0.097 + 0.098*sl 0.089 + 0.099*sl t plh 0.198 0.111 + 0.043*sl 0.110 + 0.044*sl 0.110 + 0.044*sl t phl 0.163 0.072 + 0.046*sl 0.072 + 0.046*sl 0.072 + 0.046*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.183 0.101 + 0.041*sl 0.091 + 0.044*sl 0.074 + 0.046*sl t f 0.202 0.118 + 0.042*sl 0.105 + 0.045*sl 0.088 + 0.047*sl t plh 0.115 0.073 + 0.021*sl 0.078 + 0.020*sl 0.077 + 0.020*sl t phl 0.108 0.063 + 0.023*sl 0.067 + 0.022*sl 0.065 + 0.022*sl b to y t r 0.204 0.122 + 0.041*sl 0.110 + 0.044*sl 0.094 + 0.046*sl t f 0.197 0.110 + 0.043*sl 0.099 + 0.046*sl 0.088 + 0.047*sl t plh 0.129 0.089 + 0.020*sl 0.091 + 0.020*sl 0.089 + 0.020*sl t phl 0.110 0.064 + 0.023*sl 0.069 + 0.022*sl 0.068 + 0.022*sl c to y t r 0.227 0.145 + 0.041*sl 0.134 + 0.044*sl 0.116 + 0.046*sl t f 0.190 0.102 + 0.044*sl 0.093 + 0.047*sl 0.085 + 0.047*sl t plh 0.140 0.100 + 0.020*sl 0.101 + 0.020*sl 0.101 + 0.020*sl t phl 0.109 0.063 + 0.023*sl 0.067 + 0.022*sl 0.066 + 0.022*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-31 STD111 nd3dh/nd3/nd3d2/nd3d4 3-input nand with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nd3d2 nd3d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.135 0.095 + 0.020*sl 0.089 + 0.021*sl 0.070 + 0.023*sl t f 0.153 0.113 + 0.020*sl 0.105 + 0.022*sl 0.084 + 0.023*sl t plh 0.091 0.067 + 0.012*sl 0.075 + 0.010*sl 0.075 + 0.010*sl t phl 0.081 0.055 + 0.013*sl 0.063 + 0.011*sl 0.063 + 0.011*sl b to y t r 0.155 0.116 + 0.020*sl 0.109 + 0.022*sl 0.090 + 0.023*sl t f 0.148 0.108 + 0.020*sl 0.098 + 0.023*sl 0.083 + 0.024*sl t plh 0.105 0.083 + 0.011*sl 0.087 + 0.010*sl 0.087 + 0.010*sl t phl 0.082 0.056 + 0.013*sl 0.063 + 0.011*sl 0.064 + 0.011*sl c to y t r 0.179 0.141 + 0.019*sl 0.133 + 0.022*sl 0.113 + 0.023*sl t f 0.139 0.098 + 0.021*sl 0.090 + 0.023*sl 0.079 + 0.024*sl t plh 0.117 0.096 + 0.010*sl 0.098 + 0.010*sl 0.097 + 0.010*sl t phl 0.081 0.056 + 0.012*sl 0.060 + 0.011*sl 0.062 + 0.011*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.116 0.098 + 0.009*sl 0.093 + 0.011*sl 0.072 + 0.011*sl t f 0.133 0.113 + 0.010*sl 0.110 + 0.011*sl 0.087 + 0.012*sl t plh 0.077 0.064 + 0.007*sl 0.070 + 0.005*sl 0.074 + 0.005*sl t phl 0.067 0.053 + 0.007*sl 0.059 + 0.006*sl 0.062 + 0.005*sl b to y t r 0.136 0.118 + 0.009*sl 0.113 + 0.011*sl 0.092 + 0.011*sl t f 0.127 0.106 + 0.010*sl 0.102 + 0.011*sl 0.084 + 0.012*sl t plh 0.095 0.083 + 0.006*sl 0.087 + 0.005*sl 0.087 + 0.005*sl t phl 0.070 0.057 + 0.007*sl 0.061 + 0.006*sl 0.065 + 0.005*sl c to y t r 0.160 0.141 + 0.010*sl 0.138 + 0.011*sl 0.115 + 0.011*sl t f 0.118 0.097 + 0.010*sl 0.093 + 0.011*sl 0.080 + 0.012*sl t plh 0.106 0.095 + 0.006*sl 0.097 + 0.005*sl 0.097 + 0.005*sl t phl 0.069 0.056 + 0.006*sl 0.059 + 0.006*sl 0.062 + 0.005*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-32 samsung asic nd4dh/nd4/nd4d2/nd4d2b/nd4d4 4-input nand with 0.5x/1x/2x/2x(buffered)/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nd4dh input load (sl) nd4dh nd4 nd4d2 nd4d2b nd4d4 a b c d abcdabcdabcdabcd 0.4 0.4 0.4 0.4 0.9 0.8 0.8 0.8 1.5 1.6 1.7 1.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 gate count nd4dh nd4 nd4d2 nd4d2b nd4d4 1.67 1.67 2.67 2.67 3.00 a b c y d path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.331 0.114 + 0.108*sl 0.096 + 0.113*sl 0.089 + 0.114*sl t f 0.397 0.151 + 0.123*sl 0.132 + 0.128*sl 0.127 + 0.129*sl t plh 0.188 0.091 + 0.049*sl 0.090 + 0.049*sl 0.090 + 0.049*sl t phl 0.192 0.077 + 0.058*sl 0.075 + 0.058*sl 0.074 + 0.058*sl b to y t r 0.356 0.138 + 0.109*sl 0.122 + 0.113*sl 0.115 + 0.114*sl t f 0.397 0.149 + 0.124*sl 0.136 + 0.128*sl 0.128 + 0.129*sl t plh 0.205 0.107 + 0.049*sl 0.106 + 0.049*sl 0.106 + 0.049*sl t phl 0.203 0.087 + 0.058*sl 0.087 + 0.058*sl 0.087 + 0.058*sl c to y t r 0.383 0.167 + 0.108*sl 0.148 + 0.113*sl 0.142 + 0.114*sl t f 0.394 0.143 + 0.126*sl 0.134 + 0.128*sl 0.128 + 0.129*sl t plh 0.219 0.120 + 0.049*sl 0.121 + 0.049*sl 0.121 + 0.049*sl t phl 0.210 0.093 + 0.059*sl 0.093 + 0.058*sl 0.094 + 0.058*sl d to y t r 0.411 0.195 + 0.108*sl 0.176 + 0.113*sl 0.169 + 0.114*sl t f 0.391 0.139 + 0.126*sl 0.132 + 0.128*sl 0.128 + 0.129*sl t plh 0.230 0.129 + 0.050*sl 0.132 + 0.049*sl 0.134 + 0.049*sl t phl 0.211 0.094 + 0.059*sl 0.095 + 0.058*sl 0.096 + 0.058*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table abcdy 0xxx1 x0xx1 xx0x1 xxx01 11110
samsung asic 3-33 STD111 nd4dh/nd4/nd4d2/nd4d2b/nd4d4 4-input nand with 0.5x/1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nd4 nd4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.201 0.104 + 0.049*sl 0.091 + 0.052*sl 0.076 + 0.054*sl t f 0.253 0.140 + 0.057*sl 0.127 + 0.060*sl 0.110 + 0.062*sl t plh 0.127 0.079 + 0.024*sl 0.082 + 0.023*sl 0.081 + 0.023*sl t phl 0.122 0.066 + 0.028*sl 0.067 + 0.028*sl 0.065 + 0.028*sl b to y t r 0.225 0.127 + 0.049*sl 0.115 + 0.052*sl 0.100 + 0.054*sl t f 0.251 0.137 + 0.057*sl 0.125 + 0.060*sl 0.114 + 0.062*sl t plh 0.143 0.097 + 0.023*sl 0.097 + 0.023*sl 0.097 + 0.023*sl t phl 0.131 0.073 + 0.029*sl 0.077 + 0.028*sl 0.076 + 0.028*sl c to y t r 0.251 0.154 + 0.049*sl 0.141 + 0.052*sl 0.126 + 0.054*sl t f 0.247 0.130 + 0.058*sl 0.121 + 0.061*sl 0.113 + 0.062*sl t plh 0.156 0.109 + 0.023*sl 0.110 + 0.023*sl 0.110 + 0.023*sl t phl 0.137 0.080 + 0.029*sl 0.082 + 0.028*sl 0.083 + 0.028*sl d to y t r 0.278 0.181 + 0.049*sl 0.169 + 0.052*sl 0.152 + 0.054*sl t f 0.243 0.125 + 0.059*sl 0.118 + 0.061*sl 0.111 + 0.062*sl t plh 0.166 0.118 + 0.024*sl 0.120 + 0.023*sl 0.122 + 0.023*sl t phl 0.139 0.082 + 0.029*sl 0.084 + 0.028*sl 0.084 + 0.028*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.148 0.102 + 0.023*sl 0.092 + 0.026*sl 0.074 + 0.027*sl t f 0.191 0.137 + 0.027*sl 0.128 + 0.030*sl 0.108 + 0.031*sl t plh 0.099 0.072 + 0.013*sl 0.079 + 0.012*sl 0.079 + 0.012*sl t phl 0.091 0.060 + 0.015*sl 0.066 + 0.014*sl 0.063 + 0.014*sl b to y t r 0.172 0.126 + 0.023*sl 0.117 + 0.026*sl 0.099 + 0.027*sl t f 0.190 0.134 + 0.028*sl 0.126 + 0.030*sl 0.111 + 0.031*sl t plh 0.118 0.094 + 0.012*sl 0.096 + 0.012*sl 0.095 + 0.012*sl t phl 0.100 0.070 + 0.015*sl 0.075 + 0.014*sl 0.075 + 0.014*sl c to y t r 0.199 0.153 + 0.023*sl 0.145 + 0.025*sl 0.125 + 0.027*sl t f 0.184 0.127 + 0.028*sl 0.120 + 0.030*sl 0.109 + 0.031*sl t plh 0.132 0.108 + 0.012*sl 0.109 + 0.012*sl 0.110 + 0.012*sl t phl 0.107 0.076 + 0.015*sl 0.081 + 0.014*sl 0.082 + 0.014*sl d to y t r 0.226 0.179 + 0.023*sl 0.171 + 0.025*sl 0.151 + 0.027*sl t f 0.179 0.122 + 0.029*sl 0.116 + 0.030*sl 0.107 + 0.031*sl t plh 0.140 0.116 + 0.012*sl 0.117 + 0.012*sl 0.120 + 0.012*sl t phl 0.109 0.079 + 0.015*sl 0.082 + 0.014*sl 0.083 + 0.014*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-34 samsung asic nd4dh/nd4/nd4d2/nd4d2b/nd4d4 4-input nand with 0.5x/1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nd4d2b nd4d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.071 0.045 + 0.013*sl 0.042 + 0.014*sl 0.035 + 0.014*sl t f 0.067 0.042 + 0.013*sl 0.046 + 0.011*sl 0.038 + 0.012*sl t plh 0.215 0.200 + 0.008*sl 0.204 + 0.006*sl 0.208 + 0.006*sl t phl 0.218 0.201 + 0.008*sl 0.208 + 0.007*sl 0.215 + 0.006*sl b to y t r 0.071 0.045 + 0.013*sl 0.043 + 0.014*sl 0.035 + 0.014*sl t f 0.067 0.045 + 0.011*sl 0.044 + 0.011*sl 0.038 + 0.012*sl t plh 0.234 0.219 + 0.008*sl 0.224 + 0.006*sl 0.227 + 0.006*sl t phl 0.227 0.210 + 0.008*sl 0.217 + 0.007*sl 0.224 + 0.006*sl c to y t r 0.073 0.047 + 0.013*sl 0.044 + 0.014*sl 0.035 + 0.014*sl t f 0.067 0.043 + 0.012*sl 0.046 + 0.011*sl 0.038 + 0.012*sl t plh 0.251 0.235 + 0.008*sl 0.240 + 0.006*sl 0.244 + 0.006*sl t phl 0.232 0.216 + 0.008*sl 0.222 + 0.007*sl 0.229 + 0.006*sl d to y t r 0.073 0.048 + 0.013*sl 0.045 + 0.014*sl 0.036 + 0.014*sl t f 0.066 0.041 + 0.013*sl 0.047 + 0.011*sl 0.038 + 0.012*sl t plh 0.264 0.249 + 0.008*sl 0.254 + 0.006*sl 0.257 + 0.006*sl t phl 0.235 0.218 + 0.008*sl 0.224 + 0.007*sl 0.232 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.071 0.058 + 0.007*sl 0.058 + 0.007*sl 0.048 + 0.007*sl t f 0.070 0.058 + 0.006*sl 0.058 + 0.006*sl 0.056 + 0.006*sl t plh 0.245 0.235 + 0.005*sl 0.240 + 0.003*sl 0.250 + 0.003*sl t phl 0.247 0.237 + 0.005*sl 0.242 + 0.004*sl 0.258 + 0.003*sl b to y t r 0.072 0.059 + 0.007*sl 0.059 + 0.007*sl 0.048 + 0.007*sl t f 0.069 0.056 + 0.007*sl 0.059 + 0.006*sl 0.056 + 0.006*sl t plh 0.264 0.255 + 0.005*sl 0.260 + 0.003*sl 0.270 + 0.003*sl t phl 0.257 0.246 + 0.005*sl 0.252 + 0.004*sl 0.268 + 0.003*sl c to y t r 0.073 0.060 + 0.006*sl 0.059 + 0.007*sl 0.049 + 0.007*sl t f 0.069 0.056 + 0.007*sl 0.060 + 0.006*sl 0.054 + 0.006*sl t plh 0.282 0.272 + 0.005*sl 0.277 + 0.003*sl 0.288 + 0.003*sl t phl 0.262 0.251 + 0.005*sl 0.257 + 0.004*sl 0.273 + 0.003*sl d to y t r 0.074 0.061 + 0.006*sl 0.060 + 0.007*sl 0.050 + 0.007*sl t f 0.070 0.058 + 0.006*sl 0.060 + 0.006*sl 0.054 + 0.006*sl t plh 0.296 0.287 + 0.005*sl 0.291 + 0.003*sl 0.302 + 0.003*sl t phl 0.264 0.254 + 0.005*sl 0.259 + 0.004*sl 0.275 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-35 STD111 nd5/nd5d2/nd5d4 5-input nand with 1x/2x/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nd5 input load (sl) gate count nd5 nd5d2 nd5d4 nd5 nd5d2 nd5d4 abcdeabcdeabcde 0.7 0.8 0.8 0.9 0.9 0.7 0.8 0.8 0.9 0.9 0.7 0.8 0.8 0.9 0.9 3.00 3.33 4.00 b c d y e a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.101 0.047 + 0.027*sl 0.042 + 0.028*sl 0.038 + 0.029*sl t f 0.104 0.056 + 0.024*sl 0.058 + 0.023*sl 0.053 + 0.024*sl t plh 0.235 0.208 + 0.013*sl 0.211 + 0.012*sl 0.212 + 0.012*sl t phl 0.224 0.191 + 0.016*sl 0.201 + 0.014*sl 0.209 + 0.013*sl b to y t r 0.102 0.049 + 0.026*sl 0.043 + 0.028*sl 0.038 + 0.029*sl t f 0.105 0.057 + 0.024*sl 0.058 + 0.023*sl 0.054 + 0.024*sl t plh 0.258 0.231 + 0.013*sl 0.235 + 0.012*sl 0.236 + 0.012*sl t phl 0.228 0.195 + 0.016*sl 0.205 + 0.014*sl 0.213 + 0.013*sl c to y t r 0.103 0.050 + 0.026*sl 0.044 + 0.028*sl 0.038 + 0.029*sl t f 0.104 0.055 + 0.024*sl 0.058 + 0.023*sl 0.053 + 0.024*sl t plh 0.278 0.251 + 0.013*sl 0.254 + 0.012*sl 0.255 + 0.012*sl t phl 0.227 0.194 + 0.016*sl 0.204 + 0.014*sl 0.212 + 0.013*sl d to y t r 0.105 0.052 + 0.026*sl 0.046 + 0.028*sl 0.040 + 0.029*sl t f 0.104 0.055 + 0.024*sl 0.058 + 0.023*sl 0.053 + 0.024*sl t plh 0.229 0.201 + 0.014*sl 0.206 + 0.013*sl 0.207 + 0.012*sl t phl 0.214 0.182 + 0.016*sl 0.191 + 0.014*sl 0.200 + 0.013*sl e to y t r 0.105 0.052 + 0.026*sl 0.046 + 0.028*sl 0.040 + 0.029*sl t f 0.104 0.056 + 0.024*sl 0.058 + 0.024*sl 0.053 + 0.024*sl t plh 0.246 0.218 + 0.014*sl 0.223 + 0.013*sl 0.224 + 0.012*sl t phl 0.211 0.178 + 0.016*sl 0.188 + 0.014*sl 0.196 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table abcdey 0xxxx1 x0xxx1 xx0xx1 xxx0x1 xxxx01 111110
STD111 3-36 samsung asic nd5/nd5d2/nd5d4 5-input nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nd5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.073 0.047 + 0.013*sl 0.045 + 0.014*sl 0.036 + 0.014*sl t f 0.086 0.059 + 0.013*sl 0.065 + 0.012*sl 0.064 + 0.012*sl t plh 0.239 0.223 + 0.008*sl 0.228 + 0.007*sl 0.233 + 0.006*sl t phl 0.233 0.212 + 0.010*sl 0.222 + 0.008*sl 0.239 + 0.007*sl b to y t r 0.075 0.048 + 0.013*sl 0.047 + 0.014*sl 0.037 + 0.014*sl t f 0.087 0.062 + 0.012*sl 0.064 + 0.012*sl 0.063 + 0.012*sl t plh 0.263 0.247 + 0.008*sl 0.252 + 0.006*sl 0.257 + 0.006*sl t phl 0.237 0.217 + 0.010*sl 0.226 + 0.008*sl 0.243 + 0.007*sl c to y t r 0.076 0.050 + 0.013*sl 0.049 + 0.014*sl 0.037 + 0.014*sl t f 0.086 0.060 + 0.013*sl 0.065 + 0.012*sl 0.064 + 0.012*sl t plh 0.283 0.267 + 0.008*sl 0.272 + 0.007*sl 0.277 + 0.006*sl t phl 0.236 0.215 + 0.010*sl 0.225 + 0.008*sl 0.242 + 0.007*sl d to y t r 0.078 0.051 + 0.013*sl 0.051 + 0.014*sl 0.040 + 0.014*sl t f 0.086 0.061 + 0.013*sl 0.064 + 0.012*sl 0.063 + 0.012*sl t plh 0.231 0.215 + 0.008*sl 0.221 + 0.007*sl 0.226 + 0.006*sl t phl 0.223 0.202 + 0.010*sl 0.212 + 0.008*sl 0.229 + 0.007*sl e to y t r 0.079 0.052 + 0.013*sl 0.052 + 0.013*sl 0.040 + 0.014*sl t f 0.085 0.059 + 0.013*sl 0.064 + 0.012*sl 0.063 + 0.012*sl t plh 0.248 0.232 + 0.008*sl 0.238 + 0.007*sl 0.243 + 0.006*sl t phl 0.219 0.199 + 0.010*sl 0.209 + 0.008*sl 0.226 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-37 STD111 nd5/nd5d2/nd5d4 5-input nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nd5d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.076 0.063 + 0.007*sl 0.063 + 0.007*sl 0.052 + 0.007*sl t f 0.102 0.087 + 0.007*sl 0.092 + 0.006*sl 0.096 + 0.006*sl t plh 0.269 0.259 + 0.005*sl 0.265 + 0.004*sl 0.276 + 0.003*sl t phl 0.279 0.266 + 0.007*sl 0.274 + 0.004*sl 0.300 + 0.003*sl b to y t r 0.076 0.062 + 0.007*sl 0.064 + 0.007*sl 0.053 + 0.007*sl t f 0.102 0.089 + 0.007*sl 0.091 + 0.006*sl 0.095 + 0.006*sl t plh 0.294 0.284 + 0.005*sl 0.289 + 0.004*sl 0.301 + 0.003*sl t phl 0.283 0.270 + 0.006*sl 0.278 + 0.004*sl 0.304 + 0.003*sl c to y t r 0.077 0.064 + 0.007*sl 0.064 + 0.007*sl 0.054 + 0.007*sl t f 0.101 0.087 + 0.007*sl 0.092 + 0.006*sl 0.096 + 0.006*sl t plh 0.315 0.305 + 0.005*sl 0.310 + 0.004*sl 0.322 + 0.003*sl t phl 0.282 0.269 + 0.007*sl 0.277 + 0.004*sl 0.303 + 0.003*sl d to y t r 0.079 0.066 + 0.007*sl 0.067 + 0.007*sl 0.055 + 0.007*sl t f 0.101 0.086 + 0.007*sl 0.091 + 0.006*sl 0.095 + 0.006*sl t plh 0.255 0.244 + 0.005*sl 0.250 + 0.004*sl 0.263 + 0.003*sl t phl 0.268 0.255 + 0.007*sl 0.263 + 0.004*sl 0.290 + 0.003*sl e to y t r 0.080 0.067 + 0.006*sl 0.067 + 0.007*sl 0.055 + 0.007*sl t f 0.101 0.088 + 0.007*sl 0.091 + 0.006*sl 0.094 + 0.006*sl t plh 0.273 0.263 + 0.005*sl 0.269 + 0.004*sl 0.282 + 0.003*sl t phl 0.265 0.252 + 0.006*sl 0.260 + 0.004*sl 0.286 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-38 samsung asic nd6/nd6d2/nd6d4 6-input nand with 1x/2x/4x drive logic symbol cell data input load (sl) nd6 nd6d2 nd6d4 abcdefabcdefabcdef 0.7 0.8 0.8 0.7 0.8 0.8 0.7 0.8 0.8 0.7 0.8 0.8 0.7 0.8 0.8 0.7 0.8 0.8 gate count nd6 nd6d2 nd6d4 3.33 3.67 4.33 b c d y e a f truth table abcdefy 1111110 other states 1
samsung asic 3-39 STD111 nd6/nd6d2/nd6d4 6-input nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nd6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.104 0.050 + 0.027*sl 0.045 + 0.028*sl 0.040 + 0.029*sl t f 0.105 0.058 + 0.024*sl 0.059 + 0.023*sl 0.054 + 0.024*sl t plh 0.239 0.212 + 0.013*sl 0.216 + 0.013*sl 0.217 + 0.012*sl t phl 0.225 0.192 + 0.016*sl 0.202 + 0.014*sl 0.210 + 0.013*sl b to y t r 0.104 0.051 + 0.027*sl 0.046 + 0.028*sl 0.041 + 0.029*sl t f 0.106 0.058 + 0.024*sl 0.059 + 0.023*sl 0.055 + 0.024*sl t plh 0.263 0.236 + 0.013*sl 0.240 + 0.012*sl 0.241 + 0.012*sl t phl 0.228 0.196 + 0.016*sl 0.205 + 0.014*sl 0.213 + 0.013*sl c to y t r 0.105 0.053 + 0.026*sl 0.047 + 0.028*sl 0.041 + 0.029*sl t f 0.105 0.058 + 0.024*sl 0.059 + 0.023*sl 0.054 + 0.024*sl t plh 0.283 0.256 + 0.013*sl 0.260 + 0.012*sl 0.261 + 0.012*sl t phl 0.227 0.195 + 0.016*sl 0.204 + 0.014*sl 0.213 + 0.013*sl d to y t r 0.107 0.054 + 0.027*sl 0.050 + 0.028*sl 0.043 + 0.028*sl t f 0.105 0.056 + 0.024*sl 0.060 + 0.023*sl 0.054 + 0.024*sl t plh 0.258 0.231 + 0.014*sl 0.235 + 0.013*sl 0.237 + 0.012*sl t phl 0.235 0.203 + 0.016*sl 0.212 + 0.014*sl 0.221 + 0.013*sl e to y t r 0.109 0.057 + 0.026*sl 0.051 + 0.028*sl 0.043 + 0.028*sl t f 0.105 0.057 + 0.024*sl 0.060 + 0.023*sl 0.054 + 0.024*sl t plh 0.283 0.255 + 0.014*sl 0.260 + 0.013*sl 0.261 + 0.012*sl t phl 0.239 0.206 + 0.016*sl 0.216 + 0.014*sl 0.224 + 0.013*sl f to y t r 0.110 0.057 + 0.026*sl 0.051 + 0.028*sl 0.044 + 0.028*sl t f 0.106 0.058 + 0.024*sl 0.060 + 0.023*sl 0.054 + 0.024*sl t plh 0.299 0.272 + 0.014*sl 0.277 + 0.012*sl 0.278 + 0.012*sl t phl 0.238 0.205 + 0.016*sl 0.215 + 0.014*sl 0.223 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-40 samsung asic nd6/nd6d2/nd6d4 6-input nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nd6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.075 0.049 + 0.013*sl 0.046 + 0.014*sl 0.037 + 0.014*sl t f 0.086 0.060 + 0.013*sl 0.063 + 0.012*sl 0.063 + 0.012*sl t plh 0.243 0.227 + 0.008*sl 0.233 + 0.007*sl 0.237 + 0.006*sl t phl 0.232 0.212 + 0.010*sl 0.221 + 0.008*sl 0.238 + 0.007*sl b to y t r 0.076 0.050 + 0.013*sl 0.048 + 0.014*sl 0.038 + 0.014*sl t f 0.087 0.062 + 0.012*sl 0.064 + 0.012*sl 0.063 + 0.012*sl t plh 0.267 0.251 + 0.008*sl 0.257 + 0.007*sl 0.262 + 0.006*sl t phl 0.236 0.216 + 0.010*sl 0.225 + 0.008*sl 0.242 + 0.007*sl c to y t r 0.077 0.051 + 0.013*sl 0.050 + 0.014*sl 0.039 + 0.014*sl t f 0.086 0.059 + 0.013*sl 0.065 + 0.012*sl 0.063 + 0.012*sl t plh 0.288 0.272 + 0.008*sl 0.277 + 0.007*sl 0.282 + 0.006*sl t phl 0.235 0.214 + 0.010*sl 0.224 + 0.008*sl 0.241 + 0.007*sl d to y t r 0.079 0.053 + 0.013*sl 0.051 + 0.014*sl 0.042 + 0.014*sl t f 0.087 0.062 + 0.012*sl 0.064 + 0.012*sl 0.063 + 0.012*sl t plh 0.261 0.244 + 0.008*sl 0.250 + 0.007*sl 0.256 + 0.006*sl t phl 0.242 0.222 + 0.010*sl 0.231 + 0.008*sl 0.249 + 0.007*sl e to y t r 0.081 0.054 + 0.013*sl 0.054 + 0.013*sl 0.042 + 0.014*sl t f 0.086 0.060 + 0.013*sl 0.065 + 0.012*sl 0.064 + 0.012*sl t plh 0.285 0.269 + 0.008*sl 0.275 + 0.007*sl 0.281 + 0.006*sl t phl 0.246 0.225 + 0.010*sl 0.235 + 0.008*sl 0.252 + 0.007*sl f to y t r 0.081 0.055 + 0.013*sl 0.053 + 0.013*sl 0.043 + 0.014*sl t f 0.087 0.061 + 0.013*sl 0.065 + 0.012*sl 0.063 + 0.012*sl t plh 0.302 0.286 + 0.008*sl 0.292 + 0.007*sl 0.298 + 0.006*sl t phl 0.245 0.225 + 0.010*sl 0.234 + 0.008*sl 0.251 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-41 STD111 nd6/nd6d2/nd6d4 6-input nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nd6d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.077 0.063 + 0.007*sl 0.064 + 0.007*sl 0.054 + 0.007*sl t f 0.102 0.087 + 0.007*sl 0.092 + 0.006*sl 0.096 + 0.006*sl t plh 0.274 0.265 + 0.005*sl 0.270 + 0.004*sl 0.282 + 0.003*sl t phl 0.279 0.266 + 0.007*sl 0.274 + 0.004*sl 0.300 + 0.003*sl b to y t r 0.078 0.065 + 0.006*sl 0.065 + 0.007*sl 0.054 + 0.007*sl t f 0.102 0.089 + 0.007*sl 0.092 + 0.006*sl 0.095 + 0.006*sl t plh 0.299 0.289 + 0.005*sl 0.295 + 0.004*sl 0.307 + 0.003*sl t phl 0.283 0.270 + 0.006*sl 0.278 + 0.004*sl 0.304 + 0.003*sl c to y t r 0.080 0.066 + 0.007*sl 0.067 + 0.007*sl 0.055 + 0.007*sl t f 0.102 0.088 + 0.007*sl 0.093 + 0.006*sl 0.096 + 0.006*sl t plh 0.321 0.311 + 0.005*sl 0.316 + 0.004*sl 0.328 + 0.003*sl t phl 0.282 0.269 + 0.007*sl 0.277 + 0.004*sl 0.303 + 0.003*sl d to y t r 0.083 0.071 + 0.006*sl 0.069 + 0.007*sl 0.059 + 0.007*sl t f 0.103 0.090 + 0.007*sl 0.092 + 0.006*sl 0.095 + 0.006*sl t plh 0.291 0.281 + 0.005*sl 0.286 + 0.004*sl 0.300 + 0.003*sl t phl 0.290 0.277 + 0.006*sl 0.284 + 0.004*sl 0.311 + 0.003*sl e to y t r 0.084 0.072 + 0.006*sl 0.071 + 0.007*sl 0.059 + 0.007*sl t f 0.103 0.088 + 0.007*sl 0.093 + 0.006*sl 0.096 + 0.006*sl t plh 0.316 0.305 + 0.005*sl 0.311 + 0.004*sl 0.325 + 0.003*sl t phl 0.293 0.280 + 0.006*sl 0.288 + 0.004*sl 0.314 + 0.003*sl f to y t r 0.085 0.072 + 0.006*sl 0.071 + 0.007*sl 0.060 + 0.007*sl t f 0.102 0.088 + 0.007*sl 0.092 + 0.006*sl 0.096 + 0.006*sl t plh 0.333 0.323 + 0.005*sl 0.329 + 0.004*sl 0.342 + 0.003*sl t phl 0.292 0.279 + 0.007*sl 0.287 + 0.004*sl 0.313 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-42 samsung asic nd8/nd8d2/nd8d4 8-input nand with 1x/2x/4x drive logic symbol cell data input load (sl) gate count nd8 nd8 abcdefgh 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 4.00 nd8d2 nd8d2 abcdefgh 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 4.33 nd8d4 nd8d4 abcdefgh 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 5.00 c d e y f b g a h truth table abcdefghy 111111110 other states 1
samsung asic 3-43 STD111 nd8/nd8d2/nd8d4 8-input nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.104 0.051 + 0.027*sl 0.047 + 0.028*sl 0.041 + 0.029*sl t f 0.106 0.059 + 0.024*sl 0.060 + 0.023*sl 0.056 + 0.024*sl t plh 0.257 0.230 + 0.014*sl 0.234 + 0.012*sl 0.235 + 0.012*sl t phl 0.239 0.207 + 0.016*sl 0.216 + 0.014*sl 0.224 + 0.013*sl b to y t r 0.106 0.053 + 0.026*sl 0.048 + 0.028*sl 0.042 + 0.029*sl t f 0.105 0.057 + 0.024*sl 0.060 + 0.023*sl 0.055 + 0.024*sl t plh 0.284 0.257 + 0.014*sl 0.261 + 0.013*sl 0.263 + 0.012*sl t phl 0.249 0.217 + 0.016*sl 0.226 + 0.014*sl 0.235 + 0.013*sl c to y t r 0.107 0.055 + 0.026*sl 0.048 + 0.028*sl 0.042 + 0.029*sl t f 0.105 0.055 + 0.025*sl 0.060 + 0.023*sl 0.055 + 0.024*sl t plh 0.307 0.280 + 0.014*sl 0.284 + 0.013*sl 0.286 + 0.012*sl t phl 0.256 0.223 + 0.016*sl 0.232 + 0.014*sl 0.241 + 0.013*sl d to y t r 0.109 0.057 + 0.026*sl 0.050 + 0.028*sl 0.043 + 0.028*sl t f 0.105 0.057 + 0.024*sl 0.060 + 0.024*sl 0.056 + 0.024*sl t plh 0.327 0.299 + 0.014*sl 0.303 + 0.013*sl 0.305 + 0.012*sl t phl 0.258 0.226 + 0.016*sl 0.235 + 0.014*sl 0.243 + 0.013*sl e to y t r 0.111 0.059 + 0.026*sl 0.052 + 0.028*sl 0.045 + 0.028*sl t f 0.106 0.058 + 0.024*sl 0.061 + 0.023*sl 0.056 + 0.024*sl t plh 0.278 0.250 + 0.014*sl 0.255 + 0.013*sl 0.257 + 0.012*sl t phl 0.250 0.218 + 0.016*sl 0.227 + 0.014*sl 0.236 + 0.013*sl f to y t r 0.112 0.060 + 0.026*sl 0.053 + 0.028*sl 0.046 + 0.028*sl t f 0.106 0.057 + 0.025*sl 0.061 + 0.023*sl 0.056 + 0.024*sl t plh 0.305 0.277 + 0.014*sl 0.282 + 0.013*sl 0.284 + 0.012*sl t phl 0.260 0.228 + 0.016*sl 0.237 + 0.014*sl 0.246 + 0.013*sl g to y t r 0.112 0.060 + 0.026*sl 0.055 + 0.028*sl 0.047 + 0.028*sl t f 0.107 0.059 + 0.024*sl 0.061 + 0.023*sl 0.055 + 0.024*sl t plh 0.329 0.301 + 0.014*sl 0.306 + 0.013*sl 0.308 + 0.012*sl t phl 0.267 0.235 + 0.016*sl 0.244 + 0.014*sl 0.253 + 0.013*sl h to y t r 0.114 0.062 + 0.026*sl 0.056 + 0.027*sl 0.047 + 0.028*sl t f 0.107 0.059 + 0.024*sl 0.061 + 0.023*sl 0.055 + 0.024*sl t plh 0.349 0.321 + 0.014*sl 0.326 + 0.013*sl 0.328 + 0.012*sl t phl 0.270 0.237 + 0.016*sl 0.247 + 0.014*sl 0.255 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-44 samsung asic nd8/nd8d2/nd8d4 8-input nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nd8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.079 0.053 + 0.013*sl 0.051 + 0.014*sl 0.041 + 0.014*sl t f 0.088 0.062 + 0.013*sl 0.066 + 0.012*sl 0.065 + 0.012*sl t plh 0.265 0.248 + 0.008*sl 0.254 + 0.007*sl 0.260 + 0.006*sl t phl 0.250 0.230 + 0.010*sl 0.239 + 0.008*sl 0.256 + 0.007*sl b to y t r 0.080 0.054 + 0.013*sl 0.053 + 0.013*sl 0.042 + 0.014*sl t f 0.087 0.061 + 0.013*sl 0.066 + 0.012*sl 0.065 + 0.012*sl t plh 0.292 0.276 + 0.008*sl 0.282 + 0.007*sl 0.288 + 0.006*sl t phl 0.260 0.240 + 0.010*sl 0.249 + 0.008*sl 0.266 + 0.007*sl c to y t r 0.081 0.054 + 0.013*sl 0.054 + 0.013*sl 0.043 + 0.014*sl t f 0.087 0.062 + 0.013*sl 0.065 + 0.012*sl 0.065 + 0.012*sl t plh 0.316 0.300 + 0.008*sl 0.305 + 0.007*sl 0.311 + 0.006*sl t phl 0.266 0.246 + 0.010*sl 0.256 + 0.008*sl 0.272 + 0.007*sl d to y t r 0.083 0.056 + 0.013*sl 0.056 + 0.013*sl 0.044 + 0.014*sl t f 0.088 0.062 + 0.013*sl 0.066 + 0.012*sl 0.065 + 0.012*sl t plh 0.336 0.320 + 0.008*sl 0.326 + 0.007*sl 0.331 + 0.006*sl t phl 0.269 0.249 + 0.010*sl 0.258 + 0.008*sl 0.275 + 0.007*sl e to y t r 0.085 0.059 + 0.013*sl 0.058 + 0.013*sl 0.046 + 0.014*sl t f 0.088 0.063 + 0.013*sl 0.066 + 0.012*sl 0.066 + 0.012*sl t plh 0.283 0.266 + 0.008*sl 0.272 + 0.007*sl 0.279 + 0.006*sl t phl 0.259 0.239 + 0.010*sl 0.248 + 0.008*sl 0.265 + 0.007*sl f to y t r 0.087 0.060 + 0.013*sl 0.060 + 0.013*sl 0.046 + 0.014*sl t f 0.089 0.063 + 0.013*sl 0.068 + 0.012*sl 0.066 + 0.012*sl t plh 0.310 0.294 + 0.008*sl 0.300 + 0.007*sl 0.307 + 0.006*sl t phl 0.269 0.249 + 0.010*sl 0.258 + 0.008*sl 0.276 + 0.007*sl g to y t r 0.087 0.061 + 0.013*sl 0.061 + 0.013*sl 0.047 + 0.014*sl t f 0.088 0.062 + 0.013*sl 0.068 + 0.012*sl 0.065 + 0.012*sl t plh 0.335 0.318 + 0.008*sl 0.324 + 0.007*sl 0.332 + 0.006*sl t phl 0.276 0.255 + 0.010*sl 0.265 + 0.008*sl 0.282 + 0.007*sl h to y t r 0.089 0.062 + 0.013*sl 0.062 + 0.013*sl 0.048 + 0.014*sl t f 0.088 0.062 + 0.013*sl 0.066 + 0.012*sl 0.066 + 0.012*sl t plh 0.355 0.338 + 0.008*sl 0.345 + 0.007*sl 0.352 + 0.006*sl t phl 0.278 0.258 + 0.010*sl 0.267 + 0.008*sl 0.285 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-45 STD111 nd8/nd8d2/nd8d4 8-input nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nd8d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.083 0.070 + 0.007*sl 0.070 + 0.007*sl 0.059 + 0.007*sl t f 0.103 0.090 + 0.007*sl 0.093 + 0.006*sl 0.097 + 0.006*sl t plh 0.300 0.290 + 0.005*sl 0.295 + 0.004*sl 0.309 + 0.003*sl t phl 0.298 0.285 + 0.006*sl 0.293 + 0.004*sl 0.319 + 0.003*sl b to y t r 0.084 0.071 + 0.006*sl 0.071 + 0.007*sl 0.060 + 0.007*sl t f 0.104 0.091 + 0.006*sl 0.092 + 0.006*sl 0.096 + 0.006*sl t plh 0.328 0.318 + 0.005*sl 0.323 + 0.004*sl 0.337 + 0.003*sl t phl 0.309 0.296 + 0.006*sl 0.304 + 0.004*sl 0.330 + 0.003*sl c to y t r 0.085 0.072 + 0.006*sl 0.071 + 0.007*sl 0.061 + 0.007*sl t f 0.104 0.089 + 0.007*sl 0.094 + 0.006*sl 0.097 + 0.006*sl t plh 0.353 0.342 + 0.005*sl 0.348 + 0.004*sl 0.362 + 0.003*sl t phl 0.315 0.302 + 0.006*sl 0.310 + 0.004*sl 0.336 + 0.003*sl d to y t r 0.087 0.074 + 0.006*sl 0.073 + 0.007*sl 0.063 + 0.007*sl t f 0.103 0.089 + 0.007*sl 0.094 + 0.006*sl 0.097 + 0.006*sl t plh 0.374 0.363 + 0.005*sl 0.369 + 0.004*sl 0.383 + 0.003*sl t phl 0.317 0.304 + 0.007*sl 0.312 + 0.004*sl 0.338 + 0.003*sl e to y t r 0.090 0.078 + 0.006*sl 0.076 + 0.007*sl 0.066 + 0.007*sl t f 0.104 0.092 + 0.006*sl 0.092 + 0.006*sl 0.097 + 0.006*sl t plh 0.316 0.306 + 0.005*sl 0.312 + 0.004*sl 0.327 + 0.003*sl t phl 0.307 0.294 + 0.006*sl 0.302 + 0.004*sl 0.328 + 0.003*sl f to y t r 0.091 0.079 + 0.006*sl 0.077 + 0.007*sl 0.066 + 0.007*sl t f 0.104 0.089 + 0.007*sl 0.095 + 0.006*sl 0.098 + 0.006*sl t plh 0.344 0.333 + 0.005*sl 0.340 + 0.004*sl 0.355 + 0.003*sl t phl 0.317 0.304 + 0.007*sl 0.312 + 0.004*sl 0.338 + 0.003*sl g to y t r 0.092 0.080 + 0.006*sl 0.078 + 0.006*sl 0.067 + 0.007*sl t f 0.104 0.092 + 0.006*sl 0.093 + 0.006*sl 0.097 + 0.006*sl t plh 0.369 0.359 + 0.005*sl 0.365 + 0.004*sl 0.380 + 0.003*sl t phl 0.324 0.311 + 0.006*sl 0.319 + 0.004*sl 0.345 + 0.003*sl h to y t r 0.094 0.082 + 0.006*sl 0.080 + 0.006*sl 0.068 + 0.007*sl t f 0.104 0.092 + 0.006*sl 0.092 + 0.006*sl 0.097 + 0.006*sl t plh 0.390 0.380 + 0.005*sl 0.386 + 0.004*sl 0.401 + 0.003*sl t phl 0.326 0.313 + 0.006*sl 0.321 + 0.004*sl 0.347 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-46 samsung asic nr2dh/nr2/nr2d2/nr2d2b/nr2d4/nr2a 2-input nor with 0.5x/1x/2x/2x(buffered)/4x/(2x/1x) drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nr2dh nr2 input load (sl) nr2dh nr2 nr2d2 nr2d2b nr2d4 nr2a abababababab 0.5 0.6 1.1 1.1 2.2 2.3 1.0 1.0 1.0 1.0 1.7 1.8 gate count nr2dh nr2 nr2d2 nr2d2b nr2d4 nr2a 1.00 1.00 1.67 2.00 2.33 1.67 y a b path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.339 0.116 + 0.112*sl 0.099 + 0.116*sl 0.089 + 0.117*sl t f 0.143 0.075 + 0.034*sl 0.061 + 0.038*sl 0.039 + 0.040*sl t plh 0.178 0.080 + 0.049*sl 0.077 + 0.050*sl 0.074 + 0.050*sl t phl 0.093 0.044 + 0.024*sl 0.057 + 0.021*sl 0.056 + 0.021*sl b to y t r 0.336 0.110 + 0.113*sl 0.098 + 0.116*sl 0.089 + 0.117*sl t f 0.160 0.092 + 0.034*sl 0.078 + 0.038*sl 0.055 + 0.040*sl t plh 0.177 0.077 + 0.050*sl 0.076 + 0.050*sl 0.076 + 0.050*sl t phl 0.103 0.057 + 0.023*sl 0.065 + 0.021*sl 0.065 + 0.021*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.211 0.110 + 0.051*sl 0.099 + 0.053*sl 0.083 + 0.055*sl t f 0.105 0.070 + 0.017*sl 0.071 + 0.017*sl 0.053 + 0.019*sl t plh 0.119 0.070 + 0.024*sl 0.074 + 0.023*sl 0.070 + 0.024*sl t phl 0.064 0.034 + 0.015*sl 0.050 + 0.011*sl 0.055 + 0.010*sl b to y t r 0.206 0.103 + 0.051*sl 0.093 + 0.054*sl 0.084 + 0.055*sl t f 0.124 0.093 + 0.016*sl 0.089 + 0.017*sl 0.070 + 0.019*sl t plh 0.117 0.068 + 0.024*sl 0.071 + 0.023*sl 0.070 + 0.024*sl t phl 0.076 0.048 + 0.014*sl 0.061 + 0.011*sl 0.064 + 0.010*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table aby 001 010 100 110
samsung asic 3-47 STD111 nr2dh/nr2/nr2d2/nr2d2b/nr2d4/nr2a 2-input nor with 0.5x/1x/2x/2x(buffered)/4x/(2x/1x) drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nr2d2 nr2d2b nr2d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.153 0.103 + 0.025*sl 0.097 + 0.026*sl 0.079 + 0.027*sl t f 0.083 0.064 + 0.010*sl 0.068 + 0.008*sl 0.056 + 0.009*sl t plh 0.091 0.064 + 0.013*sl 0.071 + 0.012*sl 0.068 + 0.012*sl t phl 0.045 0.026 + 0.009*sl 0.039 + 0.006*sl 0.054 + 0.005*sl b to y t r 0.148 0.100 + 0.024*sl 0.090 + 0.027*sl 0.077 + 0.028*sl t f 0.105 0.088 + 0.008*sl 0.089 + 0.008*sl 0.072 + 0.009*sl t plh 0.089 0.063 + 0.013*sl 0.067 + 0.012*sl 0.067 + 0.012*sl t phl 0.059 0.042 + 0.008*sl 0.052 + 0.006*sl 0.062 + 0.005*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.068 0.041 + 0.013*sl 0.039 + 0.014*sl 0.031 + 0.014*sl t f 0.066 0.041 + 0.013*sl 0.045 + 0.012*sl 0.037 + 0.012*sl t plh 0.186 0.171 + 0.007*sl 0.176 + 0.006*sl 0.178 + 0.006*sl t phl 0.180 0.162 + 0.009*sl 0.169 + 0.007*sl 0.178 + 0.006*sl b to y t r 0.068 0.041 + 0.013*sl 0.039 + 0.014*sl 0.030 + 0.014*sl t f 0.067 0.043 + 0.012*sl 0.044 + 0.012*sl 0.038 + 0.012*sl t plh 0.186 0.171 + 0.008*sl 0.176 + 0.006*sl 0.178 + 0.006*sl t phl 0.199 0.182 + 0.009*sl 0.189 + 0.007*sl 0.197 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.066 0.053 + 0.007*sl 0.053 + 0.007*sl 0.042 + 0.007*sl t f 0.071 0.059 + 0.006*sl 0.059 + 0.006*sl 0.058 + 0.006*sl t plh 0.213 0.204 + 0.004*sl 0.208 + 0.003*sl 0.216 + 0.003*sl t phl 0.207 0.196 + 0.005*sl 0.202 + 0.004*sl 0.220 + 0.003*sl b to y t r 0.066 0.052 + 0.007*sl 0.052 + 0.007*sl 0.042 + 0.007*sl t f 0.071 0.059 + 0.006*sl 0.060 + 0.006*sl 0.058 + 0.006*sl t plh 0.213 0.204 + 0.004*sl 0.208 + 0.003*sl 0.216 + 0.003*sl t phl 0.226 0.215 + 0.005*sl 0.221 + 0.004*sl 0.239 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-48 samsung asic nr2dh/nr2/nr2d2/nr2d2b/nr2d4/nr2a 2-input nor with 0.5x/1x/2x/2x(buffered)/4x/(2x/1x) drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nr2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.153 0.107 + 0.023*sl 0.097 + 0.025*sl 0.085 + 0.027*sl t f 0.104 0.072 + 0.016*sl 0.066 + 0.018*sl 0.053 + 0.019*sl t plh 0.076 0.047 + 0.015*sl 0.057 + 0.012*sl 0.059 + 0.012*sl t phl 0.078 0.051 + 0.014*sl 0.062 + 0.011*sl 0.065 + 0.010*sl b to y t r 0.143 0.096 + 0.023*sl 0.085 + 0.026*sl 0.075 + 0.027*sl t f 0.135 0.103 + 0.016*sl 0.097 + 0.018*sl 0.086 + 0.019*sl t plh 0.078 0.050 + 0.014*sl 0.056 + 0.012*sl 0.059 + 0.012*sl t phl 0.100 0.077 + 0.012*sl 0.082 + 0.010*sl 0.082 + 0.010*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-49 STD111 nr3dh/nr3/nr3d2/nr3d2b/nr3d4/nr3a 3-input nor with 0.5x/1x/2x/2x(buffered)/4x/(2x/1x) drive logic symbol cell data input load (sl) nr3dh nr3 nr3d2 nr3d2b nr3d4 nr3a abcabcabcabcabcabc 0.5 0.5 0.5 1.0 1.0 1.0 1.9 2.1 2.2 1.0 1.0 1.0 0.9 1.0 1.0 1.5 1.7 1.7 gate count nr3dh nr3 nr3d2 nr3d2b nr3d4 nr3a 1.33 1.33 2.33 2.33 2.67 2.00 y a b c truth table abcy 0001 other states 0
STD111 3-50 samsung asic nr3dh/nr3/nr3d2/nr3d2b/nr3d4/nr3a 3-input nor with 0.5x/1x/2x/2x(buffered)/4x/(2x/1x) drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nr3dh nr3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.532 0.190 + 0.171*sl 0.175 + 0.175*sl 0.177 + 0.175*sl t f 0.167 0.083 + 0.042*sl 0.063 + 0.047*sl 0.044 + 0.049*sl t plh 0.245 0.097 + 0.074*sl 0.094 + 0.075*sl 0.092 + 0.075*sl t phl 0.113 0.058 + 0.027*sl 0.065 + 0.025*sl 0.064 + 0.026*sl b to y t r 0.535 0.192 + 0.171*sl 0.181 + 0.174*sl 0.177 + 0.175*sl t f 0.185 0.100 + 0.043*sl 0.083 + 0.047*sl 0.062 + 0.049*sl t plh 0.265 0.115 + 0.075*sl 0.115 + 0.075*sl 0.116 + 0.075*sl t phl 0.125 0.072 + 0.027*sl 0.076 + 0.026*sl 0.076 + 0.026*sl c to y t r 0.532 0.188 + 0.172*sl 0.179 + 0.174*sl 0.177 + 0.175*sl t f 0.206 0.120 + 0.043*sl 0.104 + 0.047*sl 0.083 + 0.049*sl t plh 0.273 0.122 + 0.076*sl 0.123 + 0.075*sl 0.125 + 0.075*sl t phl 0.131 0.077 + 0.027*sl 0.081 + 0.026*sl 0.084 + 0.026*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.327 0.171 + 0.078*sl 0.159 + 0.081*sl 0.147 + 0.082*sl t f 0.118 0.077 + 0.020*sl 0.071 + 0.022*sl 0.056 + 0.024*sl t plh 0.156 0.088 + 0.034*sl 0.084 + 0.035*sl 0.082 + 0.035*sl t phl 0.080 0.047 + 0.016*sl 0.061 + 0.013*sl 0.062 + 0.013*sl b to y t r 0.329 0.171 + 0.079*sl 0.163 + 0.081*sl 0.152 + 0.082*sl t f 0.138 0.098 + 0.020*sl 0.090 + 0.022*sl 0.075 + 0.024*sl t plh 0.172 0.101 + 0.035*sl 0.101 + 0.035*sl 0.102 + 0.035*sl t phl 0.094 0.064 + 0.015*sl 0.073 + 0.013*sl 0.073 + 0.013*sl c to y t r 0.325 0.166 + 0.080*sl 0.159 + 0.081*sl 0.151 + 0.082*sl t f 0.159 0.119 + 0.020*sl 0.110 + 0.022*sl 0.096 + 0.024*sl t plh 0.179 0.107 + 0.036*sl 0.108 + 0.035*sl 0.109 + 0.035*sl t phl 0.100 0.070 + 0.015*sl 0.077 + 0.013*sl 0.079 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-51 STD111 nr3dh/nr3/nr3d2/nr3d2b/nr3d4/nr3a 3-input nor with 0.5x/1x/2x/2x(buffered)/4x/(2x/1x) drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nr3d2 nr3d2b path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.231 0.155 + 0.038*sl 0.147 + 0.040*sl 0.130 + 0.041*sl t f 0.092 0.070 + 0.011*sl 0.072 + 0.011*sl 0.054 + 0.012*sl t plh 0.113 0.077 + 0.018*sl 0.078 + 0.017*sl 0.074 + 0.018*sl t phl 0.058 0.038 + 0.010*sl 0.050 + 0.007*sl 0.059 + 0.006*sl b to y t r 0.233 0.157 + 0.038*sl 0.148 + 0.040*sl 0.136 + 0.041*sl t f 0.114 0.094 + 0.010*sl 0.093 + 0.010*sl 0.074 + 0.012*sl t plh 0.127 0.090 + 0.019*sl 0.094 + 0.018*sl 0.094 + 0.018*sl t phl 0.074 0.056 + 0.009*sl 0.065 + 0.007*sl 0.070 + 0.006*sl c to y t r 0.228 0.151 + 0.039*sl 0.144 + 0.041*sl 0.134 + 0.041*sl t f 0.134 0.114 + 0.010*sl 0.112 + 0.011*sl 0.095 + 0.012*sl t plh 0.135 0.098 + 0.019*sl 0.101 + 0.018*sl 0.102 + 0.018*sl t phl 0.080 0.062 + 0.009*sl 0.070 + 0.007*sl 0.076 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.071 0.045 + 0.013*sl 0.041 + 0.014*sl 0.033 + 0.014*sl t f 0.073 0.048 + 0.013*sl 0.051 + 0.012*sl 0.045 + 0.012*sl t plh 0.216 0.201 + 0.008*sl 0.205 + 0.006*sl 0.208 + 0.006*sl t phl 0.201 0.183 + 0.009*sl 0.190 + 0.007*sl 0.201 + 0.006*sl b to y t r 0.071 0.045 + 0.013*sl 0.042 + 0.014*sl 0.032 + 0.014*sl t f 0.073 0.049 + 0.012*sl 0.051 + 0.012*sl 0.045 + 0.012*sl t plh 0.232 0.217 + 0.008*sl 0.221 + 0.006*sl 0.224 + 0.006*sl t phl 0.221 0.202 + 0.009*sl 0.210 + 0.007*sl 0.221 + 0.006*sl c to y t r 0.070 0.044 + 0.013*sl 0.040 + 0.014*sl 0.033 + 0.014*sl t f 0.073 0.049 + 0.012*sl 0.051 + 0.012*sl 0.045 + 0.012*sl t plh 0.239 0.224 + 0.008*sl 0.228 + 0.006*sl 0.231 + 0.006*sl t phl 0.232 0.213 + 0.009*sl 0.221 + 0.007*sl 0.232 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-52 samsung asic nr3dh/nr3/nr3d2/nr3d2b/nr3d4/nr3a 3-input nor with 0.5x/1x/2x/2x(buffered)/4x/(2x/1x) drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nr3d4 nr3a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.071 0.058 + 0.006*sl 0.058 + 0.007*sl 0.045 + 0.007*sl t f 0.086 0.073 + 0.007*sl 0.076 + 0.006*sl 0.075 + 0.006*sl t plh 0.246 0.237 + 0.005*sl 0.241 + 0.003*sl 0.250 + 0.003*sl t phl 0.241 0.229 + 0.006*sl 0.236 + 0.004*sl 0.259 + 0.003*sl b to y t r 0.071 0.058 + 0.007*sl 0.058 + 0.007*sl 0.045 + 0.007*sl t f 0.086 0.073 + 0.007*sl 0.076 + 0.006*sl 0.076 + 0.006*sl t plh 0.262 0.253 + 0.005*sl 0.257 + 0.003*sl 0.266 + 0.003*sl t phl 0.260 0.248 + 0.006*sl 0.255 + 0.004*sl 0.277 + 0.003*sl c to y t r 0.070 0.057 + 0.007*sl 0.057 + 0.007*sl 0.045 + 0.007*sl t f 0.086 0.074 + 0.006*sl 0.076 + 0.006*sl 0.076 + 0.006*sl t plh 0.269 0.260 + 0.005*sl 0.265 + 0.003*sl 0.273 + 0.003*sl t phl 0.275 0.263 + 0.006*sl 0.270 + 0.004*sl 0.292 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.221 0.147 + 0.037*sl 0.138 + 0.039*sl 0.124 + 0.041*sl t f 0.114 0.073 + 0.020*sl 0.067 + 0.022*sl 0.055 + 0.023*sl t plh 0.096 0.058 + 0.019*sl 0.063 + 0.017*sl 0.061 + 0.018*sl t phl 0.092 0.062 + 0.015*sl 0.072 + 0.012*sl 0.072 + 0.012*sl b to y t r 0.219 0.144 + 0.038*sl 0.135 + 0.040*sl 0.126 + 0.041*sl t f 0.149 0.108 + 0.021*sl 0.102 + 0.022*sl 0.091 + 0.023*sl t plh 0.115 0.075 + 0.020*sl 0.082 + 0.018*sl 0.082 + 0.018*sl t phl 0.118 0.092 + 0.013*sl 0.094 + 0.012*sl 0.095 + 0.012*sl c to y t r 0.213 0.136 + 0.039*sl 0.130 + 0.040*sl 0.122 + 0.041*sl t f 0.190 0.147 + 0.022*sl 0.143 + 0.023*sl 0.132 + 0.024*sl t plh 0.124 0.086 + 0.019*sl 0.090 + 0.018*sl 0.091 + 0.018*sl t phl 0.134 0.106 + 0.014*sl 0.108 + 0.013*sl 0.112 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-53 STD111 nr4dh/nr4/nr4d2/nr4d4 4-input nor with 0.5x/1x/2x/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nr4dh input load (sl) nr4dh nr4 nr4d2 nr4d4 abcdabcdabcdabcd 0.5 0.5 0.5 0.5 0.9 1.0 0.9 1.0 0.9 1.0 0.9 1.0 0.9 1.0 0.9 1.0 gate count nr4dh nr4 nr4d2 nr4d4 2.67 2.67 3.00 3.67 y a b c d path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.174 0.056 + 0.059*sl 0.051 + 0.060*sl 0.043 + 0.061*sl t f 0.147 0.053 + 0.047*sl 0.048 + 0.048*sl 0.039 + 0.049*sl t plh 0.259 0.203 + 0.028*sl 0.209 + 0.027*sl 0.210 + 0.026*sl t phl 0.252 0.196 + 0.028*sl 0.205 + 0.026*sl 0.206 + 0.026*sl b to y t r 0.175 0.058 + 0.059*sl 0.051 + 0.060*sl 0.043 + 0.061*sl t f 0.147 0.053 + 0.047*sl 0.048 + 0.048*sl 0.039 + 0.049*sl t plh 0.259 0.203 + 0.028*sl 0.209 + 0.026*sl 0.210 + 0.026*sl t phl 0.272 0.216 + 0.028*sl 0.225 + 0.026*sl 0.226 + 0.026*sl c to y t r 0.175 0.058 + 0.059*sl 0.051 + 0.060*sl 0.043 + 0.061*sl t f 0.152 0.060 + 0.046*sl 0.053 + 0.048*sl 0.041 + 0.049*sl t plh 0.256 0.200 + 0.028*sl 0.206 + 0.027*sl 0.207 + 0.026*sl t phl 0.265 0.209 + 0.028*sl 0.219 + 0.026*sl 0.221 + 0.026*sl d to y t r 0.175 0.058 + 0.059*sl 0.052 + 0.060*sl 0.043 + 0.061*sl t f 0.152 0.060 + 0.046*sl 0.053 + 0.048*sl 0.041 + 0.049*sl t plh 0.258 0.202 + 0.028*sl 0.208 + 0.027*sl 0.209 + 0.026*sl t phl 0.287 0.230 + 0.028*sl 0.240 + 0.026*sl 0.243 + 0.026*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table abcdy 00001 other states 0
STD111 3-54 samsung asic nr4dh/nr4/nr4d2/nr4d4 4-input nor with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nr4 nr4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.105 0.051 + 0.027*sl 0.049 + 0.028*sl 0.043 + 0.028*sl t f 0.091 0.045 + 0.023*sl 0.044 + 0.023*sl 0.037 + 0.024*sl t plh 0.201 0.173 + 0.014*sl 0.178 + 0.013*sl 0.181 + 0.012*sl t phl 0.195 0.166 + 0.014*sl 0.173 + 0.013*sl 0.176 + 0.012*sl b to y t r 0.106 0.052 + 0.027*sl 0.048 + 0.028*sl 0.043 + 0.028*sl t f 0.090 0.044 + 0.023*sl 0.045 + 0.023*sl 0.038 + 0.024*sl t plh 0.202 0.174 + 0.014*sl 0.179 + 0.013*sl 0.182 + 0.012*sl t phl 0.217 0.188 + 0.014*sl 0.194 + 0.013*sl 0.197 + 0.012*sl c to y t r 0.106 0.052 + 0.027*sl 0.048 + 0.028*sl 0.043 + 0.028*sl t f 0.096 0.051 + 0.022*sl 0.049 + 0.023*sl 0.042 + 0.024*sl t plh 0.201 0.173 + 0.014*sl 0.178 + 0.013*sl 0.181 + 0.012*sl t phl 0.208 0.178 + 0.015*sl 0.186 + 0.013*sl 0.189 + 0.012*sl d to y t r 0.105 0.051 + 0.027*sl 0.048 + 0.028*sl 0.043 + 0.028*sl t f 0.095 0.050 + 0.023*sl 0.050 + 0.023*sl 0.042 + 0.024*sl t plh 0.202 0.174 + 0.014*sl 0.179 + 0.013*sl 0.182 + 0.012*sl t phl 0.229 0.200 + 0.015*sl 0.207 + 0.013*sl 0.211 + 0.012*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.078 0.050 + 0.014*sl 0.052 + 0.014*sl 0.044 + 0.014*sl t f 0.072 0.048 + 0.012*sl 0.049 + 0.012*sl 0.044 + 0.012*sl t plh 0.208 0.192 + 0.008*sl 0.198 + 0.007*sl 0.206 + 0.006*sl t phl 0.200 0.182 + 0.009*sl 0.190 + 0.007*sl 0.201 + 0.006*sl b to y t r 0.079 0.051 + 0.014*sl 0.053 + 0.014*sl 0.045 + 0.014*sl t f 0.071 0.045 + 0.013*sl 0.051 + 0.011*sl 0.044 + 0.012*sl t plh 0.209 0.192 + 0.008*sl 0.198 + 0.007*sl 0.207 + 0.006*sl t phl 0.221 0.203 + 0.009*sl 0.211 + 0.007*sl 0.222 + 0.006*sl c to y t r 0.077 0.050 + 0.014*sl 0.050 + 0.014*sl 0.044 + 0.014*sl t f 0.077 0.053 + 0.012*sl 0.055 + 0.011*sl 0.049 + 0.012*sl t plh 0.205 0.188 + 0.008*sl 0.194 + 0.007*sl 0.203 + 0.006*sl t phl 0.211 0.192 + 0.009*sl 0.200 + 0.007*sl 0.213 + 0.006*sl d to y t r 0.079 0.051 + 0.014*sl 0.052 + 0.014*sl 0.044 + 0.014*sl t f 0.076 0.051 + 0.013*sl 0.055 + 0.011*sl 0.049 + 0.012*sl t plh 0.205 0.189 + 0.008*sl 0.195 + 0.007*sl 0.204 + 0.006*sl t phl 0.232 0.213 + 0.009*sl 0.222 + 0.007*sl 0.234 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-55 STD111 nr4dh/nr4/nr4d2/nr4d4 4-input nor with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nr4d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.082 0.069 + 0.007*sl 0.068 + 0.007*sl 0.064 + 0.007*sl t f 0.080 0.067 + 0.006*sl 0.069 + 0.006*sl 0.070 + 0.006*sl t plh 0.241 0.230 + 0.005*sl 0.236 + 0.004*sl 0.252 + 0.003*sl t phl 0.235 0.223 + 0.006*sl 0.230 + 0.004*sl 0.251 + 0.003*sl b to y t r 0.082 0.069 + 0.007*sl 0.068 + 0.007*sl 0.064 + 0.007*sl t f 0.080 0.067 + 0.007*sl 0.070 + 0.006*sl 0.070 + 0.006*sl t plh 0.241 0.231 + 0.005*sl 0.236 + 0.004*sl 0.253 + 0.003*sl t phl 0.256 0.244 + 0.006*sl 0.251 + 0.004*sl 0.272 + 0.003*sl c to y t r 0.082 0.068 + 0.007*sl 0.068 + 0.007*sl 0.063 + 0.007*sl t f 0.087 0.074 + 0.007*sl 0.077 + 0.006*sl 0.076 + 0.006*sl t plh 0.236 0.225 + 0.005*sl 0.231 + 0.004*sl 0.247 + 0.003*sl t phl 0.244 0.232 + 0.006*sl 0.239 + 0.004*sl 0.262 + 0.003*sl d to y t r 0.081 0.068 + 0.007*sl 0.068 + 0.007*sl 0.063 + 0.007*sl t f 0.088 0.075 + 0.006*sl 0.077 + 0.006*sl 0.076 + 0.006*sl t plh 0.236 0.226 + 0.005*sl 0.231 + 0.004*sl 0.248 + 0.003*sl t phl 0.268 0.256 + 0.006*sl 0.263 + 0.004*sl 0.286 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-56 samsung asic nr5/nr5d2/nr5d4 5-input nor with 1x/2x/4x drive logic symbol cell data input load (sl) gate count nr5 nr5d2 nr5d4 nr5 nr5d2 nr5d4 abcdeabcdeabcde 0.9 0.9 0.9 0.9 1.0 0.9 0.9 0.9 0.9 1.0 0.9 0.9 0.9 0.9 1.0 3.00 4.00 3.33 y b c d e a truth table abcdey 000001 other states 0
samsung asic 3-57 STD111 nr5/nr5d2/nr5d4 5-input nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nr5 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.106 0.053 + 0.026*sl 0.049 + 0.028*sl 0.044 + 0.028*sl t f 0.090 0.042 + 0.024*sl 0.044 + 0.024*sl 0.038 + 0.024*sl t plh 0.231 0.203 + 0.014*sl 0.208 + 0.013*sl 0.211 + 0.012*sl t phl 0.214 0.185 + 0.015*sl 0.191 + 0.013*sl 0.194 + 0.013*sl b to y t r 0.106 0.053 + 0.026*sl 0.049 + 0.028*sl 0.044 + 0.028*sl t f 0.091 0.043 + 0.024*sl 0.043 + 0.024*sl 0.038 + 0.024*sl t plh 0.249 0.221 + 0.014*sl 0.227 + 0.013*sl 0.230 + 0.012*sl t phl 0.239 0.210 + 0.015*sl 0.216 + 0.013*sl 0.219 + 0.013*sl c to y t r 0.106 0.053 + 0.026*sl 0.049 + 0.027*sl 0.044 + 0.028*sl t f 0.091 0.043 + 0.024*sl 0.044 + 0.024*sl 0.038 + 0.024*sl t plh 0.257 0.229 + 0.014*sl 0.235 + 0.013*sl 0.237 + 0.012*sl t phl 0.253 0.224 + 0.015*sl 0.230 + 0.013*sl 0.234 + 0.013*sl d to y t r 0.104 0.051 + 0.027*sl 0.048 + 0.028*sl 0.042 + 0.028*sl t f 0.097 0.051 + 0.023*sl 0.049 + 0.023*sl 0.040 + 0.024*sl t plh 0.200 0.172 + 0.014*sl 0.177 + 0.013*sl 0.180 + 0.012*sl t phl 0.208 0.178 + 0.015*sl 0.185 + 0.013*sl 0.189 + 0.013*sl e to y t r 0.103 0.049 + 0.027*sl 0.047 + 0.028*sl 0.042 + 0.028*sl t f 0.096 0.049 + 0.023*sl 0.049 + 0.023*sl 0.041 + 0.024*sl t plh 0.201 0.173 + 0.014*sl 0.178 + 0.013*sl 0.181 + 0.012*sl t phl 0.230 0.200 + 0.015*sl 0.207 + 0.013*sl 0.211 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-58 samsung asic nr5/nr5d2/nr5d4 5-input nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nr5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.081 0.054 + 0.013*sl 0.054 + 0.014*sl 0.047 + 0.014*sl t f 0.073 0.049 + 0.012*sl 0.051 + 0.012*sl 0.045 + 0.012*sl t plh 0.240 0.223 + 0.008*sl 0.229 + 0.007*sl 0.238 + 0.006*sl t phl 0.220 0.202 + 0.009*sl 0.209 + 0.007*sl 0.220 + 0.006*sl b to y t r 0.082 0.056 + 0.013*sl 0.054 + 0.014*sl 0.047 + 0.014*sl t f 0.074 0.049 + 0.012*sl 0.051 + 0.012*sl 0.045 + 0.012*sl t plh 0.258 0.242 + 0.008*sl 0.248 + 0.007*sl 0.256 + 0.006*sl t phl 0.245 0.227 + 0.009*sl 0.234 + 0.007*sl 0.245 + 0.006*sl c to y t r 0.082 0.055 + 0.013*sl 0.055 + 0.013*sl 0.048 + 0.014*sl t f 0.074 0.049 + 0.012*sl 0.052 + 0.012*sl 0.046 + 0.012*sl t plh 0.266 0.249 + 0.008*sl 0.255 + 0.007*sl 0.264 + 0.006*sl t phl 0.260 0.242 + 0.009*sl 0.249 + 0.007*sl 0.260 + 0.006*sl d to y t r 0.078 0.051 + 0.014*sl 0.051 + 0.014*sl 0.045 + 0.014*sl t f 0.078 0.054 + 0.012*sl 0.056 + 0.012*sl 0.050 + 0.012*sl t plh 0.204 0.187 + 0.008*sl 0.193 + 0.007*sl 0.202 + 0.006*sl t phl 0.213 0.194 + 0.009*sl 0.202 + 0.007*sl 0.214 + 0.006*sl e to y t r 0.079 0.052 + 0.014*sl 0.053 + 0.014*sl 0.045 + 0.014*sl t f 0.077 0.052 + 0.013*sl 0.057 + 0.012*sl 0.049 + 0.012*sl t plh 0.205 0.188 + 0.008*sl 0.194 + 0.007*sl 0.203 + 0.006*sl t phl 0.234 0.215 + 0.009*sl 0.224 + 0.007*sl 0.236 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-59 STD111 nr5/nr5d2/nr5d4 5-input nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nr5d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.088 0.074 + 0.007*sl 0.074 + 0.007*sl 0.067 + 0.007*sl t f 0.082 0.069 + 0.006*sl 0.071 + 0.006*sl 0.071 + 0.006*sl t plh 0.279 0.268 + 0.005*sl 0.274 + 0.004*sl 0.290 + 0.003*sl t phl 0.257 0.246 + 0.006*sl 0.252 + 0.004*sl 0.273 + 0.003*sl b to y t r 0.088 0.075 + 0.006*sl 0.074 + 0.007*sl 0.068 + 0.007*sl t f 0.083 0.070 + 0.006*sl 0.072 + 0.006*sl 0.071 + 0.006*sl t plh 0.297 0.287 + 0.005*sl 0.293 + 0.004*sl 0.309 + 0.003*sl t phl 0.282 0.271 + 0.006*sl 0.277 + 0.004*sl 0.298 + 0.003*sl c to y t r 0.088 0.075 + 0.006*sl 0.074 + 0.007*sl 0.068 + 0.007*sl t f 0.084 0.071 + 0.006*sl 0.073 + 0.006*sl 0.072 + 0.006*sl t plh 0.305 0.294 + 0.005*sl 0.300 + 0.004*sl 0.317 + 0.003*sl t phl 0.298 0.287 + 0.006*sl 0.293 + 0.004*sl 0.314 + 0.003*sl d to y t r 0.083 0.069 + 0.007*sl 0.070 + 0.007*sl 0.065 + 0.007*sl t f 0.088 0.075 + 0.006*sl 0.077 + 0.006*sl 0.076 + 0.006*sl t plh 0.237 0.227 + 0.005*sl 0.233 + 0.004*sl 0.249 + 0.003*sl t phl 0.247 0.235 + 0.006*sl 0.242 + 0.004*sl 0.264 + 0.003*sl e to y t r 0.083 0.069 + 0.007*sl 0.070 + 0.007*sl 0.065 + 0.007*sl t f 0.088 0.075 + 0.006*sl 0.077 + 0.006*sl 0.076 + 0.006*sl t plh 0.238 0.228 + 0.005*sl 0.233 + 0.004*sl 0.250 + 0.003*sl t phl 0.268 0.256 + 0.006*sl 0.263 + 0.004*sl 0.286 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-60 samsung asic nr6/nr6d2/nr6d4 6-input nor with 1x/2x/4x drive logic symbol cell data input load (sl) nr6 nr6d2 nr6d4 abcdefabcdefabcdef 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 gate count nr6 nr6d2 nr6d4 3.33 3.67 4.33 y b c d e a f truth table abcdefy 0000001 other states 0
samsung asic 3-61 STD111 nr6/nr6d2/nr6d4 6-input nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nr6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.107 0.054 + 0.026*sl 0.049 + 0.028*sl 0.044 + 0.028*sl t f 0.091 0.045 + 0.023*sl 0.044 + 0.023*sl 0.038 + 0.024*sl t plh 0.234 0.206 + 0.014*sl 0.212 + 0.013*sl 0.214 + 0.012*sl t phl 0.216 0.187 + 0.015*sl 0.193 + 0.013*sl 0.197 + 0.012*sl b to y t r 0.107 0.054 + 0.026*sl 0.050 + 0.028*sl 0.044 + 0.028*sl t f 0.091 0.045 + 0.023*sl 0.044 + 0.023*sl 0.039 + 0.024*sl t plh 0.253 0.224 + 0.014*sl 0.230 + 0.013*sl 0.233 + 0.012*sl t phl 0.241 0.211 + 0.015*sl 0.218 + 0.013*sl 0.222 + 0.012*sl c to y t r 0.107 0.054 + 0.027*sl 0.050 + 0.027*sl 0.045 + 0.028*sl t f 0.091 0.044 + 0.023*sl 0.045 + 0.023*sl 0.039 + 0.024*sl t plh 0.260 0.232 + 0.014*sl 0.238 + 0.013*sl 0.241 + 0.012*sl t phl 0.255 0.225 + 0.015*sl 0.233 + 0.013*sl 0.236 + 0.012*sl d to y t r 0.106 0.053 + 0.027*sl 0.050 + 0.027*sl 0.045 + 0.028*sl t f 0.096 0.052 + 0.022*sl 0.049 + 0.023*sl 0.042 + 0.024*sl t plh 0.232 0.204 + 0.014*sl 0.210 + 0.013*sl 0.213 + 0.012*sl t phl 0.229 0.199 + 0.015*sl 0.207 + 0.013*sl 0.211 + 0.012*sl e to y t r 0.107 0.054 + 0.027*sl 0.051 + 0.027*sl 0.045 + 0.028*sl t f 0.096 0.052 + 0.022*sl 0.049 + 0.023*sl 0.042 + 0.024*sl t plh 0.250 0.221 + 0.014*sl 0.228 + 0.013*sl 0.231 + 0.012*sl t phl 0.254 0.224 + 0.015*sl 0.232 + 0.013*sl 0.236 + 0.012*sl f to y t r 0.107 0.054 + 0.027*sl 0.051 + 0.027*sl 0.045 + 0.028*sl t f 0.097 0.053 + 0.022*sl 0.050 + 0.023*sl 0.043 + 0.024*sl t plh 0.259 0.231 + 0.014*sl 0.237 + 0.013*sl 0.240 + 0.012*sl t phl 0.270 0.240 + 0.015*sl 0.248 + 0.013*sl 0.252 + 0.012*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-62 samsung asic nr6/nr6d2/nr6d4 6-input nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nr6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.082 0.055 + 0.014*sl 0.055 + 0.014*sl 0.048 + 0.014*sl t f 0.073 0.049 + 0.012*sl 0.052 + 0.011*sl 0.046 + 0.012*sl t plh 0.243 0.226 + 0.008*sl 0.232 + 0.007*sl 0.241 + 0.006*sl t phl 0.221 0.203 + 0.009*sl 0.211 + 0.007*sl 0.222 + 0.006*sl b to y t r 0.082 0.055 + 0.014*sl 0.055 + 0.014*sl 0.048 + 0.014*sl t f 0.074 0.050 + 0.012*sl 0.052 + 0.011*sl 0.046 + 0.012*sl t plh 0.261 0.244 + 0.008*sl 0.251 + 0.007*sl 0.259 + 0.006*sl t phl 0.246 0.228 + 0.009*sl 0.236 + 0.007*sl 0.247 + 0.006*sl c to y t r 0.083 0.056 + 0.014*sl 0.056 + 0.013*sl 0.048 + 0.014*sl t f 0.074 0.050 + 0.012*sl 0.052 + 0.011*sl 0.047 + 0.012*sl t plh 0.269 0.252 + 0.008*sl 0.258 + 0.007*sl 0.267 + 0.006*sl t phl 0.261 0.243 + 0.009*sl 0.251 + 0.007*sl 0.262 + 0.006*sl d to y t r 0.081 0.053 + 0.014*sl 0.054 + 0.014*sl 0.048 + 0.014*sl t f 0.078 0.053 + 0.012*sl 0.057 + 0.011*sl 0.051 + 0.012*sl t plh 0.237 0.220 + 0.008*sl 0.227 + 0.007*sl 0.236 + 0.006*sl t phl 0.233 0.214 + 0.009*sl 0.222 + 0.007*sl 0.235 + 0.006*sl e to y t r 0.082 0.054 + 0.014*sl 0.055 + 0.014*sl 0.048 + 0.014*sl t f 0.078 0.054 + 0.012*sl 0.057 + 0.011*sl 0.051 + 0.012*sl t plh 0.255 0.238 + 0.008*sl 0.245 + 0.007*sl 0.254 + 0.006*sl t phl 0.258 0.240 + 0.009*sl 0.248 + 0.007*sl 0.260 + 0.006*sl f to y t r 0.082 0.054 + 0.014*sl 0.056 + 0.013*sl 0.048 + 0.014*sl t f 0.080 0.056 + 0.012*sl 0.058 + 0.011*sl 0.052 + 0.012*sl t plh 0.265 0.248 + 0.008*sl 0.254 + 0.007*sl 0.263 + 0.006*sl t phl 0.275 0.256 + 0.009*sl 0.264 + 0.007*sl 0.277 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-63 STD111 nr6/nr6d2/nr6d4 6-input nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nr6d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.088 0.075 + 0.007*sl 0.075 + 0.007*sl 0.068 + 0.007*sl t f 0.082 0.069 + 0.007*sl 0.072 + 0.006*sl 0.071 + 0.006*sl t plh 0.280 0.269 + 0.005*sl 0.275 + 0.004*sl 0.291 + 0.003*sl t phl 0.258 0.246 + 0.006*sl 0.253 + 0.004*sl 0.274 + 0.003*sl b to y t r 0.088 0.075 + 0.006*sl 0.075 + 0.007*sl 0.068 + 0.007*sl t f 0.083 0.070 + 0.006*sl 0.073 + 0.006*sl 0.072 + 0.006*sl t plh 0.298 0.288 + 0.005*sl 0.293 + 0.004*sl 0.310 + 0.003*sl t phl 0.283 0.272 + 0.006*sl 0.278 + 0.004*sl 0.299 + 0.003*sl c to y t r 0.088 0.075 + 0.006*sl 0.075 + 0.007*sl 0.068 + 0.007*sl t f 0.084 0.072 + 0.006*sl 0.073 + 0.006*sl 0.072 + 0.006*sl t plh 0.306 0.295 + 0.005*sl 0.301 + 0.004*sl 0.318 + 0.003*sl t phl 0.299 0.288 + 0.006*sl 0.294 + 0.004*sl 0.315 + 0.003*sl d to y t r 0.086 0.073 + 0.007*sl 0.073 + 0.007*sl 0.068 + 0.007*sl t f 0.088 0.075 + 0.007*sl 0.078 + 0.006*sl 0.078 + 0.006*sl t plh 0.269 0.259 + 0.005*sl 0.265 + 0.004*sl 0.282 + 0.003*sl t phl 0.267 0.255 + 0.006*sl 0.262 + 0.004*sl 0.285 + 0.003*sl e to y t r 0.086 0.073 + 0.006*sl 0.072 + 0.007*sl 0.068 + 0.007*sl t f 0.088 0.075 + 0.007*sl 0.078 + 0.006*sl 0.078 + 0.006*sl t plh 0.287 0.277 + 0.005*sl 0.283 + 0.004*sl 0.300 + 0.003*sl t phl 0.293 0.281 + 0.006*sl 0.287 + 0.004*sl 0.310 + 0.003*sl f to y t r 0.086 0.073 + 0.007*sl 0.073 + 0.007*sl 0.068 + 0.007*sl t f 0.089 0.076 + 0.007*sl 0.079 + 0.006*sl 0.078 + 0.006*sl t plh 0.297 0.286 + 0.005*sl 0.292 + 0.004*sl 0.309 + 0.003*sl t phl 0.310 0.298 + 0.006*sl 0.305 + 0.004*sl 0.328 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-64 samsung asic nr8/nr8d2/nr8d4 8-input nor with 1x/2x/4x drive logic symbol cell data input load (sl) gate count nr8 nr8 abcdefgh 0.9 0.9 0.9 0.9 0.9 0.9 1.0 1.0 4.33 nr8d2 nr8d2 abcdefgh 0.9 0.9 0.9 0.9 0.9 0.9 0.9 1.0 4.67 nr8d4 nr8d4 abcdefgh 0.9 0.9 0.9 0.9 0.9 0.9 0.9 1.0 5.33 y c d e f b g a h truth table abcdefghy 000000001 other states 0
samsung asic 3-65 STD111 nr8/nr8d2/nr8d4 8-input nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nr8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.118 0.064 + 0.027*sl 0.063 + 0.027*sl 0.058 + 0.028*sl t f 0.101 0.052 + 0.024*sl 0.058 + 0.023*sl 0.049 + 0.024*sl t plh 0.258 0.227 + 0.015*sl 0.236 + 0.013*sl 0.243 + 0.012*sl t phl 0.235 0.205 + 0.015*sl 0.212 + 0.013*sl 0.218 + 0.013*sl b to y t r 0.118 0.064 + 0.027*sl 0.063 + 0.027*sl 0.058 + 0.028*sl t f 0.098 0.052 + 0.023*sl 0.053 + 0.023*sl 0.047 + 0.024*sl t plh 0.276 0.246 + 0.015*sl 0.254 + 0.013*sl 0.261 + 0.012*sl t phl 0.260 0.229 + 0.015*sl 0.237 + 0.013*sl 0.243 + 0.013*sl c to y t r 0.118 0.063 + 0.027*sl 0.063 + 0.027*sl 0.059 + 0.028*sl t f 0.101 0.055 + 0.023*sl 0.055 + 0.023*sl 0.048 + 0.024*sl t plh 0.285 0.254 + 0.015*sl 0.262 + 0.013*sl 0.269 + 0.012*sl t phl 0.275 0.244 + 0.015*sl 0.253 + 0.013*sl 0.259 + 0.013*sl d to y t r 0.119 0.066 + 0.027*sl 0.065 + 0.027*sl 0.059 + 0.028*sl t f 0.104 0.058 + 0.023*sl 0.058 + 0.023*sl 0.051 + 0.024*sl t plh 0.260 0.229 + 0.015*sl 0.238 + 0.013*sl 0.245 + 0.012*sl t phl 0.250 0.218 + 0.016*sl 0.228 + 0.013*sl 0.235 + 0.013*sl e to y t r 0.119 0.065 + 0.027*sl 0.064 + 0.027*sl 0.059 + 0.028*sl t f 0.104 0.058 + 0.023*sl 0.059 + 0.023*sl 0.051 + 0.024*sl t plh 0.278 0.247 + 0.015*sl 0.256 + 0.013*sl 0.263 + 0.012*sl t phl 0.271 0.240 + 0.016*sl 0.249 + 0.013*sl 0.256 + 0.013*sl f to y t r 0.119 0.066 + 0.027*sl 0.064 + 0.027*sl 0.059 + 0.028*sl t f 0.106 0.060 + 0.023*sl 0.060 + 0.023*sl 0.053 + 0.023*sl t plh 0.287 0.256 + 0.015*sl 0.265 + 0.013*sl 0.272 + 0.012*sl t phl 0.286 0.254 + 0.016*sl 0.264 + 0.013*sl 0.271 + 0.013*sl g to y t r 0.117 0.063 + 0.027*sl 0.062 + 0.027*sl 0.058 + 0.028*sl t f 0.109 0.064 + 0.023*sl 0.065 + 0.023*sl 0.058 + 0.023*sl t plh 0.240 0.209 + 0.015*sl 0.218 + 0.013*sl 0.225 + 0.012*sl t phl 0.245 0.213 + 0.016*sl 0.223 + 0.013*sl 0.231 + 0.013*sl h to y t r 0.117 0.063 + 0.027*sl 0.062 + 0.027*sl 0.058 + 0.028*sl t f 0.110 0.065 + 0.023*sl 0.065 + 0.023*sl 0.058 + 0.023*sl t plh 0.241 0.210 + 0.015*sl 0.218 + 0.013*sl 0.225 + 0.012*sl t phl 0.266 0.233 + 0.016*sl 0.244 + 0.013*sl 0.252 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-66 samsung asic nr8/nr8d2/nr8d4 8-input nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nr8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.094 0.066 + 0.014*sl 0.067 + 0.014*sl 0.063 + 0.014*sl t f 0.080 0.053 + 0.013*sl 0.059 + 0.012*sl 0.055 + 0.012*sl t plh 0.268 0.249 + 0.009*sl 0.257 + 0.007*sl 0.271 + 0.006*sl t phl 0.241 0.222 + 0.010*sl 0.231 + 0.007*sl 0.246 + 0.007*sl b to y t r 0.094 0.066 + 0.014*sl 0.068 + 0.014*sl 0.063 + 0.014*sl t f 0.080 0.054 + 0.013*sl 0.059 + 0.012*sl 0.055 + 0.012*sl t plh 0.286 0.267 + 0.009*sl 0.275 + 0.007*sl 0.290 + 0.006*sl t phl 0.266 0.246 + 0.010*sl 0.255 + 0.007*sl 0.270 + 0.007*sl c to y t r 0.095 0.068 + 0.013*sl 0.067 + 0.014*sl 0.063 + 0.014*sl t f 0.081 0.055 + 0.013*sl 0.060 + 0.012*sl 0.055 + 0.012*sl t plh 0.294 0.275 + 0.009*sl 0.283 + 0.007*sl 0.298 + 0.006*sl t phl 0.282 0.263 + 0.010*sl 0.271 + 0.007*sl 0.287 + 0.007*sl d to y t r 0.095 0.066 + 0.014*sl 0.069 + 0.014*sl 0.063 + 0.014*sl t f 0.087 0.062 + 0.013*sl 0.066 + 0.012*sl 0.061 + 0.012*sl t plh 0.267 0.248 + 0.010*sl 0.256 + 0.007*sl 0.271 + 0.006*sl t phl 0.255 0.234 + 0.010*sl 0.244 + 0.008*sl 0.261 + 0.007*sl e to y t r 0.094 0.066 + 0.014*sl 0.066 + 0.014*sl 0.064 + 0.014*sl t f 0.087 0.061 + 0.013*sl 0.066 + 0.012*sl 0.061 + 0.012*sl t plh 0.285 0.266 + 0.010*sl 0.274 + 0.007*sl 0.290 + 0.006*sl t phl 0.276 0.255 + 0.010*sl 0.265 + 0.008*sl 0.282 + 0.007*sl f to y t r 0.094 0.065 + 0.014*sl 0.067 + 0.014*sl 0.064 + 0.014*sl t f 0.088 0.064 + 0.012*sl 0.066 + 0.012*sl 0.061 + 0.012*sl t plh 0.294 0.274 + 0.010*sl 0.283 + 0.007*sl 0.298 + 0.006*sl t phl 0.291 0.271 + 0.010*sl 0.281 + 0.008*sl 0.297 + 0.007*sl g to y t r 0.092 0.064 + 0.014*sl 0.066 + 0.014*sl 0.062 + 0.014*sl t f 0.093 0.067 + 0.013*sl 0.073 + 0.011*sl 0.067 + 0.012*sl t plh 0.246 0.226 + 0.010*sl 0.235 + 0.007*sl 0.250 + 0.006*sl t phl 0.249 0.227 + 0.011*sl 0.238 + 0.008*sl 0.257 + 0.007*sl h to y t r 0.092 0.063 + 0.014*sl 0.065 + 0.014*sl 0.062 + 0.014*sl t f 0.093 0.068 + 0.012*sl 0.071 + 0.012*sl 0.067 + 0.012*sl t plh 0.246 0.227 + 0.010*sl 0.235 + 0.007*sl 0.250 + 0.006*sl t phl 0.269 0.248 + 0.011*sl 0.259 + 0.008*sl 0.277 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-67 STD111 nr8/nr8d2/nr8d4 8-input nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nr8d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.107 0.094 + 0.007*sl 0.093 + 0.007*sl 0.092 + 0.007*sl t f 0.095 0.081 + 0.007*sl 0.085 + 0.006*sl 0.087 + 0.006*sl t plh 0.316 0.304 + 0.006*sl 0.311 + 0.004*sl 0.334 + 0.003*sl t phl 0.286 0.274 + 0.006*sl 0.281 + 0.004*sl 0.306 + 0.003*sl b to y t r 0.107 0.094 + 0.007*sl 0.093 + 0.007*sl 0.092 + 0.007*sl t f 0.095 0.082 + 0.007*sl 0.085 + 0.006*sl 0.087 + 0.006*sl t plh 0.335 0.322 + 0.006*sl 0.330 + 0.004*sl 0.352 + 0.003*sl t phl 0.311 0.298 + 0.006*sl 0.306 + 0.004*sl 0.331 + 0.003*sl c to y t r 0.106 0.094 + 0.006*sl 0.092 + 0.007*sl 0.090 + 0.007*sl t f 0.096 0.085 + 0.006*sl 0.084 + 0.006*sl 0.088 + 0.006*sl t plh 0.343 0.331 + 0.006*sl 0.338 + 0.004*sl 0.361 + 0.003*sl t phl 0.328 0.316 + 0.006*sl 0.323 + 0.004*sl 0.348 + 0.003*sl d to y t r 0.107 0.094 + 0.006*sl 0.092 + 0.007*sl 0.091 + 0.007*sl t f 0.102 0.089 + 0.007*sl 0.092 + 0.006*sl 0.094 + 0.006*sl t plh 0.312 0.300 + 0.006*sl 0.307 + 0.004*sl 0.331 + 0.003*sl t phl 0.293 0.280 + 0.007*sl 0.288 + 0.004*sl 0.315 + 0.003*sl e to y t r 0.107 0.094 + 0.007*sl 0.093 + 0.007*sl 0.092 + 0.007*sl t f 0.102 0.088 + 0.007*sl 0.094 + 0.006*sl 0.094 + 0.006*sl t plh 0.330 0.318 + 0.006*sl 0.325 + 0.004*sl 0.348 + 0.003*sl t phl 0.318 0.305 + 0.007*sl 0.313 + 0.004*sl 0.340 + 0.003*sl f to y t r 0.106 0.093 + 0.007*sl 0.093 + 0.007*sl 0.092 + 0.007*sl t f 0.103 0.089 + 0.007*sl 0.093 + 0.006*sl 0.095 + 0.006*sl t plh 0.338 0.326 + 0.006*sl 0.334 + 0.004*sl 0.357 + 0.003*sl t phl 0.334 0.321 + 0.007*sl 0.329 + 0.004*sl 0.356 + 0.003*sl g to y t r 0.105 0.091 + 0.007*sl 0.091 + 0.007*sl 0.089 + 0.007*sl t f 0.109 0.096 + 0.007*sl 0.099 + 0.006*sl 0.101 + 0.006*sl t plh 0.290 0.278 + 0.006*sl 0.286 + 0.004*sl 0.309 + 0.003*sl t phl 0.292 0.279 + 0.007*sl 0.287 + 0.004*sl 0.316 + 0.003*sl h to y t r 0.105 0.091 + 0.007*sl 0.091 + 0.007*sl 0.089 + 0.007*sl t f 0.108 0.093 + 0.008*sl 0.100 + 0.006*sl 0.102 + 0.006*sl t plh 0.291 0.279 + 0.006*sl 0.286 + 0.004*sl 0.309 + 0.003*sl t phl 0.313 0.299 + 0.007*sl 0.308 + 0.004*sl 0.336 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-68 samsung asic or2dh/or2/or2d2/or2d4 2-input or with 0.5x/1x/2x/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) or2dh or2 input load (sl) gate count or2dh or2 or2d2 or2d4 or2dh or2 or2d2 or2d4 abababab 0.5 0.5 0.9 0.9 0.9 0.9 0.9 0.9 1.33 1.33 1.67 2.33 y a b path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.172 0.055 + 0.059*sl 0.047 + 0.061*sl 0.040 + 0.061*sl t f 0.157 0.062 + 0.047*sl 0.060 + 0.048*sl 0.049 + 0.049*sl t plh 0.176 0.122 + 0.027*sl 0.124 + 0.026*sl 0.124 + 0.026*sl t phl 0.198 0.139 + 0.029*sl 0.151 + 0.026*sl 0.156 + 0.026*sl b to y t r 0.175 0.058 + 0.058*sl 0.050 + 0.060*sl 0.042 + 0.061*sl t f 0.158 0.065 + 0.047*sl 0.061 + 0.048*sl 0.049 + 0.049*sl t plh 0.199 0.145 + 0.027*sl 0.148 + 0.026*sl 0.148 + 0.026*sl t phl 0.200 0.141 + 0.029*sl 0.154 + 0.026*sl 0.159 + 0.026*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.103 0.050 + 0.026*sl 0.045 + 0.028*sl 0.038 + 0.029*sl t f 0.102 0.053 + 0.024*sl 0.058 + 0.023*sl 0.049 + 0.024*sl t plh 0.137 0.110 + 0.014*sl 0.114 + 0.012*sl 0.115 + 0.012*sl t phl 0.154 0.121 + 0.016*sl 0.131 + 0.014*sl 0.139 + 0.013*sl b to y t r 0.106 0.053 + 0.026*sl 0.048 + 0.028*sl 0.041 + 0.028*sl t f 0.102 0.053 + 0.024*sl 0.056 + 0.023*sl 0.050 + 0.024*sl t plh 0.160 0.133 + 0.014*sl 0.137 + 0.013*sl 0.138 + 0.012*sl t phl 0.155 0.123 + 0.016*sl 0.133 + 0.014*sl 0.140 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table aby 000 011 101 111
samsung asic 3-69 STD111 or2dh/or2/or2d2/or2d4 2-input or with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) or2d2 or2d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.078 0.051 + 0.013*sl 0.050 + 0.014*sl 0.041 + 0.014*sl t f 0.084 0.059 + 0.013*sl 0.063 + 0.012*sl 0.062 + 0.012*sl t plh 0.146 0.130 + 0.008*sl 0.135 + 0.007*sl 0.141 + 0.006*sl t phl 0.164 0.145 + 0.010*sl 0.153 + 0.007*sl 0.169 + 0.006*sl b to y t r 0.083 0.057 + 0.013*sl 0.055 + 0.013*sl 0.045 + 0.014*sl t f 0.085 0.059 + 0.013*sl 0.063 + 0.012*sl 0.062 + 0.012*sl t plh 0.167 0.150 + 0.008*sl 0.156 + 0.007*sl 0.163 + 0.006*sl t phl 0.164 0.145 + 0.010*sl 0.154 + 0.008*sl 0.170 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.084 0.071 + 0.006*sl 0.070 + 0.007*sl 0.062 + 0.007*sl t f 0.100 0.087 + 0.007*sl 0.090 + 0.006*sl 0.094 + 0.006*sl t plh 0.183 0.173 + 0.005*sl 0.178 + 0.004*sl 0.193 + 0.003*sl t phl 0.210 0.197 + 0.006*sl 0.205 + 0.004*sl 0.230 + 0.003*sl b to y t r 0.092 0.079 + 0.006*sl 0.078 + 0.006*sl 0.068 + 0.007*sl t f 0.101 0.087 + 0.007*sl 0.091 + 0.006*sl 0.094 + 0.006*sl t plh 0.203 0.193 + 0.005*sl 0.199 + 0.004*sl 0.215 + 0.003*sl t phl 0.211 0.198 + 0.006*sl 0.206 + 0.004*sl 0.231 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-70 samsung asic or3dh/or3/or3d2/or3d4 3-input or with 0.5x/1x/2x/4x drive logic symbol cell data input load (sl) or3dh or3 or3d2 or3d4 abcabcabcabc 0.4 0.5 0.5 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 gate count or3dh or3 or3d2 or3d4 1.67 1.67 2.00 2.67 y a b c truth table abcy 0000 1xx1 x1x1 xx11
samsung asic 3-71 STD111 or3dh/or3/or3d2/or3d4 3-input or with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) or3dh or3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.175 0.058 + 0.058*sl 0.051 + 0.060*sl 0.042 + 0.061*sl t f 0.181 0.083 + 0.049*sl 0.089 + 0.047*sl 0.080 + 0.048*sl t plh 0.195 0.140 + 0.028*sl 0.144 + 0.026*sl 0.145 + 0.026*sl t phl 0.244 0.177 + 0.033*sl 0.198 + 0.028*sl 0.215 + 0.026*sl b to y t r 0.181 0.066 + 0.057*sl 0.056 + 0.060*sl 0.045 + 0.061*sl t f 0.181 0.083 + 0.049*sl 0.090 + 0.047*sl 0.080 + 0.048*sl t plh 0.221 0.165 + 0.028*sl 0.170 + 0.027*sl 0.171 + 0.026*sl t phl 0.264 0.198 + 0.033*sl 0.219 + 0.028*sl 0.236 + 0.026*sl c to y t r 0.186 0.071 + 0.058*sl 0.063 + 0.060*sl 0.052 + 0.061*sl t f 0.181 0.084 + 0.049*sl 0.090 + 0.047*sl 0.080 + 0.048*sl t plh 0.238 0.180 + 0.029*sl 0.189 + 0.027*sl 0.191 + 0.026*sl t phl 0.275 0.208 + 0.033*sl 0.229 + 0.028*sl 0.246 + 0.026*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.106 0.054 + 0.026*sl 0.048 + 0.028*sl 0.041 + 0.028*sl t f 0.118 0.068 + 0.025*sl 0.076 + 0.023*sl 0.077 + 0.023*sl t plh 0.154 0.126 + 0.014*sl 0.131 + 0.013*sl 0.133 + 0.012*sl t phl 0.188 0.152 + 0.018*sl 0.164 + 0.015*sl 0.180 + 0.013*sl b to y t r 0.112 0.060 + 0.026*sl 0.055 + 0.027*sl 0.045 + 0.028*sl t f 0.121 0.073 + 0.024*sl 0.077 + 0.023*sl 0.078 + 0.023*sl t plh 0.179 0.151 + 0.014*sl 0.157 + 0.013*sl 0.159 + 0.012*sl t phl 0.206 0.171 + 0.018*sl 0.183 + 0.015*sl 0.199 + 0.013*sl c to y t r 0.118 0.066 + 0.026*sl 0.061 + 0.027*sl 0.053 + 0.028*sl t f 0.121 0.072 + 0.024*sl 0.078 + 0.023*sl 0.076 + 0.023*sl t plh 0.195 0.166 + 0.015*sl 0.173 + 0.013*sl 0.177 + 0.012*sl t phl 0.215 0.180 + 0.018*sl 0.192 + 0.015*sl 0.207 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-72 samsung asic or3dh/or3/or3d2/or3d4 3-input or with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) or3d2 or3d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.086 0.062 + 0.012*sl 0.057 + 0.013*sl 0.047 + 0.014*sl t f 0.110 0.084 + 0.013*sl 0.089 + 0.012*sl 0.095 + 0.012*sl t plh 0.164 0.146 + 0.009*sl 0.154 + 0.007*sl 0.162 + 0.006*sl t phl 0.207 0.185 + 0.011*sl 0.196 + 0.008*sl 0.220 + 0.007*sl b to y t r 0.091 0.065 + 0.013*sl 0.063 + 0.013*sl 0.053 + 0.014*sl t f 0.112 0.085 + 0.013*sl 0.090 + 0.012*sl 0.096 + 0.012*sl t plh 0.189 0.171 + 0.009*sl 0.178 + 0.007*sl 0.188 + 0.006*sl t phl 0.227 0.204 + 0.011*sl 0.215 + 0.008*sl 0.239 + 0.007*sl c to y t r 0.099 0.071 + 0.014*sl 0.073 + 0.013*sl 0.060 + 0.014*sl t f 0.112 0.086 + 0.013*sl 0.089 + 0.012*sl 0.096 + 0.012*sl t plh 0.205 0.187 + 0.009*sl 0.195 + 0.007*sl 0.206 + 0.006*sl t phl 0.236 0.213 + 0.011*sl 0.224 + 0.008*sl 0.248 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.093 0.080 + 0.006*sl 0.079 + 0.007*sl 0.071 + 0.007*sl t f 0.141 0.127 + 0.007*sl 0.131 + 0.006*sl 0.139 + 0.006*sl t plh 0.205 0.195 + 0.005*sl 0.201 + 0.004*sl 0.218 + 0.003*sl t phl 0.274 0.259 + 0.007*sl 0.268 + 0.005*sl 0.301 + 0.004*sl b to y t r 0.101 0.089 + 0.006*sl 0.087 + 0.007*sl 0.079 + 0.007*sl t f 0.142 0.127 + 0.007*sl 0.131 + 0.006*sl 0.139 + 0.006*sl t plh 0.229 0.218 + 0.006*sl 0.225 + 0.004*sl 0.244 + 0.003*sl t phl 0.295 0.280 + 0.007*sl 0.289 + 0.005*sl 0.322 + 0.004*sl c to y t r 0.110 0.099 + 0.006*sl 0.095 + 0.007*sl 0.087 + 0.007*sl t f 0.140 0.125 + 0.007*sl 0.129 + 0.006*sl 0.139 + 0.006*sl t plh 0.247 0.235 + 0.006*sl 0.243 + 0.004*sl 0.263 + 0.003*sl t phl 0.304 0.290 + 0.007*sl 0.299 + 0.005*sl 0.332 + 0.004*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-73 STD111 or4dh/or4/or4d2/or4d4 4-input or with 0.5x/1x/2x/4x drive logic symbol cell data input load (sl) or4dh or4 or4d2 or4d4 abcdabcdabcdabcd 0.5 0.5 0.5 0.5 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 gate count or4dh or4 or4d2 or4d4 2.33 2.33 2.67 4.00 y a b c d truth table abcdy 00000 1xxx1 x1xx1 xx1x1 xxx11
STD111 3-74 samsung asic or4dh/or4/or4d2/or4d4 4-input or with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) or4dh or4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.205 0.063 + 0.071*sl 0.056 + 0.073*sl 0.051 + 0.073*sl t f 0.212 0.078 + 0.067*sl 0.074 + 0.068*sl 0.064 + 0.069*sl t plh 0.195 0.131 + 0.032*sl 0.133 + 0.032*sl 0.133 + 0.032*sl t phl 0.217 0.145 + 0.036*sl 0.154 + 0.033*sl 0.157 + 0.033*sl b to y t r 0.207 0.066 + 0.071*sl 0.059 + 0.073*sl 0.053 + 0.073*sl t f 0.213 0.080 + 0.067*sl 0.074 + 0.068*sl 0.064 + 0.069*sl t plh 0.218 0.153 + 0.032*sl 0.156 + 0.032*sl 0.156 + 0.032*sl t phl 0.218 0.146 + 0.036*sl 0.156 + 0.033*sl 0.158 + 0.033*sl c to y t r 0.222 0.081 + 0.071*sl 0.074 + 0.073*sl 0.068 + 0.073*sl t f 0.207 0.072 + 0.067*sl 0.067 + 0.069*sl 0.060 + 0.069*sl t plh 0.204 0.140 + 0.032*sl 0.141 + 0.032*sl 0.142 + 0.032*sl t phl 0.215 0.144 + 0.035*sl 0.151 + 0.033*sl 0.154 + 0.033*sl d to y t r 0.225 0.085 + 0.070*sl 0.076 + 0.073*sl 0.069 + 0.073*sl t f 0.207 0.072 + 0.067*sl 0.067 + 0.069*sl 0.060 + 0.069*sl t plh 0.227 0.163 + 0.032*sl 0.165 + 0.032*sl 0.166 + 0.032*sl t phl 0.217 0.146 + 0.035*sl 0.153 + 0.033*sl 0.156 + 0.033*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.122 0.058 + 0.032*sl 0.052 + 0.034*sl 0.047 + 0.034*sl t f 0.134 0.069 + 0.032*sl 0.069 + 0.032*sl 0.063 + 0.033*sl t plh 0.150 0.119 + 0.016*sl 0.122 + 0.015*sl 0.122 + 0.015*sl t phl 0.163 0.126 + 0.019*sl 0.134 + 0.017*sl 0.139 + 0.016*sl b to y t r 0.125 0.061 + 0.032*sl 0.057 + 0.033*sl 0.049 + 0.034*sl t f 0.134 0.069 + 0.032*sl 0.069 + 0.032*sl 0.063 + 0.033*sl t plh 0.173 0.141 + 0.016*sl 0.144 + 0.015*sl 0.146 + 0.015*sl t phl 0.165 0.127 + 0.019*sl 0.135 + 0.017*sl 0.140 + 0.016*sl c to y t r 0.139 0.075 + 0.032*sl 0.069 + 0.034*sl 0.064 + 0.034*sl t f 0.129 0.066 + 0.032*sl 0.061 + 0.033*sl 0.059 + 0.033*sl t plh 0.159 0.128 + 0.015*sl 0.130 + 0.015*sl 0.130 + 0.015*sl t phl 0.164 0.128 + 0.018*sl 0.134 + 0.016*sl 0.137 + 0.016*sl d to y t r 0.143 0.079 + 0.032*sl 0.073 + 0.033*sl 0.067 + 0.034*sl t f 0.130 0.067 + 0.032*sl 0.063 + 0.033*sl 0.058 + 0.033*sl t plh 0.182 0.151 + 0.016*sl 0.153 + 0.015*sl 0.154 + 0.015*sl t phl 0.165 0.129 + 0.018*sl 0.135 + 0.016*sl 0.139 + 0.016*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-75 STD111 or4dh/or4/or4d2/or4d4 4-input or with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) or4d2 or4d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.092 0.061 + 0.016*sl 0.056 + 0.017*sl 0.049 + 0.017*sl t f 0.105 0.071 + 0.017*sl 0.074 + 0.016*sl 0.071 + 0.016*sl t plh 0.159 0.141 + 0.009*sl 0.146 + 0.008*sl 0.149 + 0.008*sl t phl 0.171 0.149 + 0.011*sl 0.157 + 0.009*sl 0.169 + 0.008*sl b to y t r 0.097 0.066 + 0.016*sl 0.063 + 0.017*sl 0.052 + 0.017*sl t f 0.106 0.073 + 0.017*sl 0.075 + 0.016*sl 0.072 + 0.016*sl t plh 0.181 0.162 + 0.009*sl 0.167 + 0.008*sl 0.172 + 0.008*sl t phl 0.172 0.150 + 0.011*sl 0.158 + 0.009*sl 0.171 + 0.008*sl c to y t r 0.112 0.080 + 0.016*sl 0.077 + 0.017*sl 0.066 + 0.017*sl t f 0.102 0.071 + 0.016*sl 0.069 + 0.016*sl 0.065 + 0.017*sl t plh 0.170 0.152 + 0.009*sl 0.156 + 0.008*sl 0.158 + 0.008*sl t phl 0.172 0.152 + 0.010*sl 0.157 + 0.009*sl 0.167 + 0.008*sl d to y t r 0.117 0.086 + 0.015*sl 0.083 + 0.016*sl 0.070 + 0.017*sl t f 0.103 0.071 + 0.016*sl 0.069 + 0.016*sl 0.065 + 0.017*sl t plh 0.191 0.174 + 0.009*sl 0.178 + 0.008*sl 0.181 + 0.008*sl t phl 0.173 0.152 + 0.010*sl 0.158 + 0.009*sl 0.168 + 0.008*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.069 0.056 + 0.007*sl 0.056 + 0.007*sl 0.046 + 0.007*sl t f 0.064 0.050 + 0.007*sl 0.055 + 0.006*sl 0.050 + 0.006*sl t plh 0.274 0.265 + 0.005*sl 0.269 + 0.003*sl 0.280 + 0.003*sl t phl 0.281 0.270 + 0.005*sl 0.276 + 0.004*sl 0.291 + 0.003*sl b to y t r 0.069 0.056 + 0.007*sl 0.056 + 0.007*sl 0.046 + 0.007*sl t f 0.064 0.050 + 0.007*sl 0.055 + 0.006*sl 0.050 + 0.006*sl t plh 0.298 0.288 + 0.005*sl 0.293 + 0.003*sl 0.303 + 0.003*sl t phl 0.282 0.272 + 0.005*sl 0.277 + 0.004*sl 0.293 + 0.003*sl c to y t r 0.070 0.056 + 0.007*sl 0.057 + 0.007*sl 0.046 + 0.007*sl t f 0.064 0.051 + 0.007*sl 0.054 + 0.006*sl 0.050 + 0.006*sl t plh 0.286 0.277 + 0.005*sl 0.281 + 0.003*sl 0.291 + 0.003*sl t phl 0.280 0.269 + 0.005*sl 0.275 + 0.004*sl 0.290 + 0.003*sl d to y t r 0.070 0.056 + 0.007*sl 0.057 + 0.007*sl 0.047 + 0.007*sl t f 0.064 0.050 + 0.007*sl 0.054 + 0.006*sl 0.050 + 0.006*sl t plh 0.310 0.301 + 0.005*sl 0.305 + 0.003*sl 0.316 + 0.003*sl t phl 0.282 0.272 + 0.005*sl 0.277 + 0.004*sl 0.292 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-76 samsung asic or5/or5d2/or5d4 5-input or with 1x/2x/4x drive logic symbol cell data input load (sl) gate count or5 or5d2 or5d4 or5 or5d2 or5d4 abcdeabcdeabcde 0.8 0.9 0.9 0.9 0.9 0.8 0.9 0.9 0.9 0.9 0.8 0.9 0.9 0.9 0.9 2.67 3.00 4.33 y b c d e a truth table abcdey 000000 1xxxx1 x1xxx1 xx1xx1 xxx1x1 xxxx11
samsung asic 3-77 STD111 or5/or5d2/or5d4 5-input or with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) or5 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.125 0.060 + 0.032*sl 0.055 + 0.034*sl 0.050 + 0.034*sl t f 0.150 0.083 + 0.034*sl 0.088 + 0.032*sl 0.085 + 0.033*sl t plh 0.167 0.135 + 0.016*sl 0.139 + 0.015*sl 0.140 + 0.015*sl t phl 0.197 0.156 + 0.020*sl 0.167 + 0.018*sl 0.180 + 0.016*sl b to y t r 0.130 0.066 + 0.032*sl 0.061 + 0.033*sl 0.053 + 0.034*sl t f 0.153 0.087 + 0.033*sl 0.089 + 0.032*sl 0.087 + 0.033*sl t plh 0.193 0.160 + 0.016*sl 0.165 + 0.015*sl 0.167 + 0.015*sl t phl 0.217 0.175 + 0.021*sl 0.187 + 0.018*sl 0.199 + 0.016*sl c to y t r 0.137 0.074 + 0.032*sl 0.067 + 0.033*sl 0.061 + 0.034*sl t f 0.153 0.086 + 0.033*sl 0.090 + 0.032*sl 0.086 + 0.033*sl t plh 0.209 0.175 + 0.017*sl 0.181 + 0.015*sl 0.185 + 0.015*sl t phl 0.226 0.184 + 0.021*sl 0.196 + 0.018*sl 0.208 + 0.016*sl d to y t r 0.140 0.075 + 0.032*sl 0.069 + 0.034*sl 0.064 + 0.034*sl t f 0.130 0.066 + 0.032*sl 0.062 + 0.033*sl 0.060 + 0.033*sl t plh 0.159 0.128 + 0.015*sl 0.130 + 0.015*sl 0.130 + 0.015*sl t phl 0.164 0.128 + 0.018*sl 0.134 + 0.017*sl 0.138 + 0.016*sl e to y t r 0.143 0.079 + 0.032*sl 0.074 + 0.033*sl 0.067 + 0.034*sl t f 0.130 0.066 + 0.032*sl 0.062 + 0.033*sl 0.059 + 0.033*sl t plh 0.182 0.151 + 0.016*sl 0.153 + 0.015*sl 0.154 + 0.015*sl t phl 0.165 0.129 + 0.018*sl 0.135 + 0.017*sl 0.140 + 0.016*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-78 samsung asic or5/or5d2/or5d4 5-input or with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) or5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.097 0.064 + 0.016*sl 0.063 + 0.017*sl 0.054 + 0.017*sl t f 0.129 0.096 + 0.017*sl 0.097 + 0.016*sl 0.100 + 0.016*sl t plh 0.178 0.159 + 0.009*sl 0.165 + 0.008*sl 0.170 + 0.008*sl t phl 0.212 0.187 + 0.012*sl 0.197 + 0.010*sl 0.218 + 0.008*sl b to y t r 0.104 0.072 + 0.016*sl 0.070 + 0.016*sl 0.059 + 0.017*sl t f 0.132 0.099 + 0.016*sl 0.099 + 0.016*sl 0.100 + 0.016*sl t plh 0.203 0.184 + 0.010*sl 0.190 + 0.008*sl 0.196 + 0.008*sl t phl 0.231 0.206 + 0.012*sl 0.217 + 0.010*sl 0.238 + 0.008*sl c to y t r 0.112 0.083 + 0.015*sl 0.076 + 0.016*sl 0.066 + 0.017*sl t f 0.132 0.100 + 0.016*sl 0.100 + 0.016*sl 0.101 + 0.016*sl t plh 0.220 0.200 + 0.010*sl 0.207 + 0.008*sl 0.216 + 0.008*sl t phl 0.242 0.217 + 0.012*sl 0.227 + 0.010*sl 0.248 + 0.008*sl d to y t r 0.111 0.081 + 0.015*sl 0.076 + 0.017*sl 0.067 + 0.017*sl t f 0.102 0.070 + 0.016*sl 0.069 + 0.016*sl 0.067 + 0.017*sl t plh 0.169 0.152 + 0.009*sl 0.156 + 0.008*sl 0.158 + 0.008*sl t phl 0.172 0.152 + 0.010*sl 0.157 + 0.009*sl 0.168 + 0.008*sl e to y t r 0.117 0.087 + 0.015*sl 0.082 + 0.016*sl 0.070 + 0.017*sl t f 0.103 0.071 + 0.016*sl 0.069 + 0.016*sl 0.067 + 0.017*sl t plh 0.191 0.174 + 0.009*sl 0.177 + 0.008*sl 0.181 + 0.008*sl t phl 0.173 0.152 + 0.010*sl 0.158 + 0.009*sl 0.169 + 0.008*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-79 STD111 or5/or5d2/or5d4 5-input or with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) or5d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.070 0.056 + 0.007*sl 0.057 + 0.007*sl 0.046 + 0.007*sl t f 0.065 0.053 + 0.006*sl 0.054 + 0.006*sl 0.051 + 0.006*sl t plh 0.291 0.281 + 0.005*sl 0.286 + 0.003*sl 0.296 + 0.003*sl t phl 0.313 0.303 + 0.005*sl 0.308 + 0.004*sl 0.323 + 0.003*sl b to y t r 0.069 0.055 + 0.007*sl 0.056 + 0.007*sl 0.046 + 0.007*sl t f 0.065 0.052 + 0.006*sl 0.054 + 0.006*sl 0.051 + 0.006*sl t plh 0.317 0.308 + 0.005*sl 0.312 + 0.003*sl 0.322 + 0.003*sl t phl 0.332 0.321 + 0.005*sl 0.326 + 0.004*sl 0.342 + 0.003*sl c to y t r 0.070 0.056 + 0.007*sl 0.057 + 0.007*sl 0.046 + 0.007*sl t f 0.065 0.053 + 0.006*sl 0.053 + 0.006*sl 0.051 + 0.006*sl t plh 0.333 0.324 + 0.005*sl 0.328 + 0.003*sl 0.338 + 0.003*sl t phl 0.340 0.329 + 0.005*sl 0.334 + 0.004*sl 0.350 + 0.003*sl d to y t r 0.070 0.056 + 0.007*sl 0.057 + 0.007*sl 0.046 + 0.007*sl t f 0.064 0.051 + 0.007*sl 0.054 + 0.006*sl 0.051 + 0.006*sl t plh 0.286 0.277 + 0.005*sl 0.281 + 0.003*sl 0.291 + 0.003*sl t phl 0.280 0.270 + 0.005*sl 0.275 + 0.004*sl 0.291 + 0.003*sl e to y t r 0.070 0.056 + 0.007*sl 0.057 + 0.007*sl 0.047 + 0.007*sl t f 0.064 0.050 + 0.007*sl 0.055 + 0.006*sl 0.050 + 0.006*sl t plh 0.311 0.301 + 0.005*sl 0.306 + 0.003*sl 0.316 + 0.003*sl t phl 0.282 0.272 + 0.005*sl 0.277 + 0.004*sl 0.293 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-80 samsung asic xn2/xn2d2/xn2d4 2-input exclusive-nor with 1x/2x/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) xn2 input load (sl) gate count xn2 xn2d2 xn2d4 xn2 xn2d2 xn2d4 ababab 0.7 1.5 0.7 1.5 0.7 1.5 2.33 2.33 3.00 y a b path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.123 0.070 + 0.027*sl 0.069 + 0.027*sl 0.061 + 0.028*sl t f 0.123 0.075 + 0.024*sl 0.081 + 0.022*sl 0.076 + 0.023*sl t plh 0.238 0.208 + 0.015*sl 0.216 + 0.013*sl 0.222 + 0.012*sl t phl 0.250 0.216 + 0.017*sl 0.228 + 0.014*sl 0.239 + 0.013*sl b to y t r 0.117 0.062 + 0.027*sl 0.062 + 0.027*sl 0.058 + 0.028*sl t f 0.113 0.064 + 0.025*sl 0.070 + 0.023*sl 0.070 + 0.023*sl t plh 0.215 0.184 + 0.015*sl 0.193 + 0.013*sl 0.199 + 0.012*sl t phl 0.196 0.161 + 0.018*sl 0.173 + 0.014*sl 0.187 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table aby 001 010 100 111
samsung asic 3-81 STD111 xn2/xn2d2/xn2d4 2-input exclusive-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) xn2d2 xn2d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.107 0.080 + 0.014*sl 0.081 + 0.013*sl 0.077 + 0.014*sl t f 0.113 0.087 + 0.013*sl 0.092 + 0.012*sl 0.096 + 0.011*sl t plh 0.251 0.232 + 0.009*sl 0.240 + 0.007*sl 0.255 + 0.006*sl t phl 0.267 0.245 + 0.011*sl 0.256 + 0.008*sl 0.277 + 0.007*sl b to y t r 0.102 0.074 + 0.014*sl 0.076 + 0.014*sl 0.073 + 0.014*sl t f 0.106 0.080 + 0.013*sl 0.085 + 0.012*sl 0.092 + 0.011*sl t plh 0.228 0.209 + 0.009*sl 0.217 + 0.007*sl 0.232 + 0.006*sl t phl 0.207 0.184 + 0.012*sl 0.196 + 0.008*sl 0.222 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.126 0.114 + 0.006*sl 0.112 + 0.007*sl 0.112 + 0.007*sl t f 0.136 0.121 + 0.007*sl 0.126 + 0.006*sl 0.138 + 0.006*sl t plh 0.300 0.288 + 0.006*sl 0.295 + 0.004*sl 0.319 + 0.003*sl t phl 0.325 0.311 + 0.007*sl 0.320 + 0.005*sl 0.351 + 0.004*sl b to y t r 0.125 0.112 + 0.006*sl 0.110 + 0.007*sl 0.110 + 0.007*sl t f 0.134 0.119 + 0.007*sl 0.125 + 0.006*sl 0.136 + 0.006*sl t plh 0.275 0.263 + 0.006*sl 0.270 + 0.004*sl 0.294 + 0.003*sl t phl 0.251 0.237 + 0.007*sl 0.246 + 0.005*sl 0.281 + 0.004*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-82 samsung asic xn3/xn3d2/xn3d4 3-input exclusive-nor with 1x/2x/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) xn3 input load (sl) gate count xn3 xn3d2 xn3d 4 xn3 xn3d2 xn3d4 abcabcabc 1.4 0.7 1.5 1.4 0.7 1.5 1.3 0.7 1.5 3.67 4.00 4.67 y a b c path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.142 0.083 + 0.029*sl 0.089 + 0.028*sl 0.090 + 0.028*sl t f 0.129 0.075 + 0.027*sl 0.083 + 0.025*sl 0.093 + 0.024*sl t plh 0.211 0.175 + 0.018*sl 0.187 + 0.015*sl 0.204 + 0.013*sl t phl 0.224 0.189 + 0.017*sl 0.201 + 0.014*sl 0.212 + 0.013*sl b to y t r 0.162 0.106 + 0.028*sl 0.109 + 0.027*sl 0.107 + 0.027*sl t f 0.177 0.125 + 0.026*sl 0.133 + 0.024*sl 0.141 + 0.023*sl t plh 0.373 0.342 + 0.016*sl 0.351 + 0.013*sl 0.358 + 0.012*sl t phl 0.375 0.332 + 0.022*sl 0.350 + 0.017*sl 0.374 + 0.014*sl c to y t r 0.160 0.105 + 0.028*sl 0.107 + 0.027*sl 0.105 + 0.027*sl t f 0.165 0.114 + 0.026*sl 0.122 + 0.023*sl 0.126 + 0.023*sl t plh 0.332 0.295 + 0.018*sl 0.309 + 0.015*sl 0.325 + 0.013*sl t phl 0.353 0.319 + 0.017*sl 0.330 + 0.014*sl 0.341 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table abcy 0001 0010 0100 0111 1000 1011 1101 1110
samsung asic 3-83 STD111 xn3/xn3d2/xn3d4 3-input exclusive-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) xn3d2 xn3d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.131 0.102 + 0.015*sl 0.103 + 0.014*sl 0.110 + 0.014*sl t f 0.122 0.091 + 0.016*sl 0.101 + 0.013*sl 0.117 + 0.012*sl t plh 0.222 0.197 + 0.012*sl 0.211 + 0.009*sl 0.238 + 0.007*sl t phl 0.235 0.213 + 0.011*sl 0.225 + 0.008*sl 0.246 + 0.007*sl b to y t r 0.148 0.121 + 0.014*sl 0.120 + 0.014*sl 0.124 + 0.014*sl t f 0.168 0.136 + 0.016*sl 0.150 + 0.013*sl 0.163 + 0.012*sl t plh 0.386 0.366 + 0.010*sl 0.376 + 0.007*sl 0.391 + 0.006*sl t phl 0.390 0.362 + 0.014*sl 0.378 + 0.010*sl 0.413 + 0.007*sl c to y t r 0.147 0.120 + 0.014*sl 0.119 + 0.014*sl 0.122 + 0.014*sl t f 0.168 0.137 + 0.015*sl 0.148 + 0.013*sl 0.160 + 0.012*sl t plh 0.346 0.322 + 0.012*sl 0.336 + 0.008*sl 0.361 + 0.007*sl t phl 0.367 0.345 + 0.011*sl 0.356 + 0.008*sl 0.378 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.175 0.163 + 0.006*sl 0.160 + 0.007*sl 0.163 + 0.007*sl t f 0.168 0.152 + 0.008*sl 0.158 + 0.007*sl 0.178 + 0.006*sl t plh 0.282 0.265 + 0.008*sl 0.276 + 0.005*sl 0.316 + 0.004*sl t phl 0.293 0.279 + 0.007*sl 0.288 + 0.005*sl 0.320 + 0.004*sl b to y t r 0.120 0.107 + 0.007*sl 0.107 + 0.007*sl 0.103 + 0.007*sl t f 0.193 0.177 + 0.008*sl 0.183 + 0.006*sl 0.199 + 0.006*sl t plh 0.438 0.425 + 0.006*sl 0.433 + 0.004*sl 0.458 + 0.003*sl t phl 0.464 0.446 + 0.009*sl 0.457 + 0.006*sl 0.502 + 0.004*sl c to y t r 0.183 0.170 + 0.007*sl 0.169 + 0.007*sl 0.170 + 0.007*sl t f 0.128 0.114 + 0.007*sl 0.118 + 0.006*sl 0.122 + 0.006*sl t plh 0.408 0.392 + 0.008*sl 0.403 + 0.005*sl 0.438 + 0.004*sl t phl 0.427 0.413 + 0.007*sl 0.422 + 0.005*sl 0.453 + 0.004*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-84 samsung asic xo2/xo2d2/xo2d4 2-input exclusive-or with 1x/2x/4x drive logic symbol cell data input load (sl) gate count xo2 xo2d2 xo2d4 xo2 xo2d2 xo2d4 ababab 0.7 1.3 0.7 1.3 0.7 1.3 2.33 2.33 3.00 y a b truth table aby 000 011 101 110
samsung asic 3-85 STD111 xo2/xo2d2/xo2d4 2-input exclusive-or with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) xo2 xo2d2 xo2d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.124 0.071 + 0.026*sl 0.071 + 0.027*sl 0.062 + 0.028*sl t f 0.123 0.076 + 0.024*sl 0.081 + 0.022*sl 0.077 + 0.023*sl t plh 0.239 0.209 + 0.015*sl 0.217 + 0.013*sl 0.223 + 0.012*sl t phl 0.254 0.220 + 0.017*sl 0.232 + 0.014*sl 0.243 + 0.013*sl b to y t r 0.120 0.067 + 0.027*sl 0.066 + 0.027*sl 0.060 + 0.028*sl t f 0.114 0.065 + 0.024*sl 0.070 + 0.023*sl 0.069 + 0.023*sl t plh 0.189 0.158 + 0.016*sl 0.167 + 0.013*sl 0.175 + 0.012*sl t phl 0.221 0.187 + 0.017*sl 0.199 + 0.014*sl 0.210 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.106 0.079 + 0.013*sl 0.079 + 0.013*sl 0.075 + 0.014*sl t f 0.111 0.084 + 0.013*sl 0.090 + 0.012*sl 0.095 + 0.011*sl t plh 0.248 0.229 + 0.009*sl 0.238 + 0.007*sl 0.252 + 0.006*sl t phl 0.265 0.243 + 0.011*sl 0.254 + 0.008*sl 0.275 + 0.007*sl b to y t r 0.103 0.076 + 0.014*sl 0.076 + 0.014*sl 0.073 + 0.014*sl t f 0.103 0.076 + 0.014*sl 0.083 + 0.012*sl 0.090 + 0.011*sl t plh 0.197 0.177 + 0.010*sl 0.186 + 0.007*sl 0.204 + 0.006*sl t phl 0.232 0.211 + 0.011*sl 0.222 + 0.008*sl 0.243 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.127 0.115 + 0.006*sl 0.113 + 0.007*sl 0.112 + 0.007*sl t f 0.135 0.120 + 0.007*sl 0.125 + 0.006*sl 0.137 + 0.006*sl t plh 0.299 0.286 + 0.006*sl 0.294 + 0.004*sl 0.318 + 0.003*sl t phl 0.327 0.313 + 0.007*sl 0.322 + 0.005*sl 0.353 + 0.004*sl b to y t r 0.125 0.111 + 0.007*sl 0.112 + 0.007*sl 0.111 + 0.007*sl t f 0.132 0.117 + 0.007*sl 0.122 + 0.006*sl 0.135 + 0.006*sl t plh 0.239 0.226 + 0.007*sl 0.234 + 0.004*sl 0.262 + 0.003*sl t phl 0.295 0.281 + 0.007*sl 0.290 + 0.005*sl 0.321 + 0.004*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-86 samsung asic xo3/xo3d2/xo3d4 3-input exclusive-or with 1x/2x/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) xo3 input load (sl) gate count xo3 xo3d2 xo3d4 xo3 xo3d2 xo3d4 abcabcabc 1.4 0.7 1.5 1.4 0.7 1.5 1.4 0.7 1.5 3.67 4.00 4.67 y a b c path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.134 0.075 + 0.030*sl 0.080 + 0.028*sl 0.084 + 0.028*sl t f 0.143 0.087 + 0.028*sl 0.097 + 0.025*sl 0.112 + 0.024*sl t plh 0.217 0.186 + 0.015*sl 0.195 + 0.013*sl 0.201 + 0.012*sl t phl 0.220 0.177 + 0.022*sl 0.194 + 0.017*sl 0.219 + 0.014*sl b to y t r 0.162 0.106 + 0.028*sl 0.109 + 0.027*sl 0.108 + 0.027*sl t f 0.177 0.125 + 0.026*sl 0.134 + 0.024*sl 0.142 + 0.023*sl t plh 0.374 0.343 + 0.015*sl 0.352 + 0.013*sl 0.359 + 0.012*sl t phl 0.376 0.333 + 0.022*sl 0.352 + 0.017*sl 0.375 + 0.014*sl c to y t r 0.160 0.105 + 0.028*sl 0.107 + 0.027*sl 0.106 + 0.027*sl t f 0.165 0.114 + 0.026*sl 0.122 + 0.023*sl 0.126 + 0.023*sl t plh 0.331 0.294 + 0.018*sl 0.308 + 0.015*sl 0.324 + 0.013*sl t phl 0.352 0.318 + 0.017*sl 0.329 + 0.014*sl 0.341 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table abcy 0000 0011 0101 0110 1001 1010 1100 1111
samsung asic 3-87 STD111 xo3/xo3d2/xo3d4 3-input exclusive-or with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) xo3d2 xo3d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.124 0.095 + 0.015*sl 0.096 + 0.014*sl 0.105 + 0.014*sl t f 0.139 0.106 + 0.017*sl 0.119 + 0.013*sl 0.138 + 0.012*sl t plh 0.228 0.209 + 0.010*sl 0.218 + 0.007*sl 0.232 + 0.006*sl t phl 0.230 0.201 + 0.014*sl 0.217 + 0.010*sl 0.255 + 0.008*sl b to y t r 0.148 0.120 + 0.014*sl 0.120 + 0.014*sl 0.124 + 0.014*sl t f 0.169 0.136 + 0.016*sl 0.150 + 0.013*sl 0.164 + 0.012*sl t plh 0.387 0.367 + 0.010*sl 0.376 + 0.007*sl 0.392 + 0.006*sl t phl 0.392 0.364 + 0.014*sl 0.380 + 0.010*sl 0.415 + 0.007*sl c to y t r 0.147 0.120 + 0.014*sl 0.119 + 0.014*sl 0.122 + 0.014*sl t f 0.168 0.137 + 0.015*sl 0.148 + 0.013*sl 0.161 + 0.012*sl t plh 0.345 0.321 + 0.012*sl 0.335 + 0.008*sl 0.360 + 0.007*sl t phl 0.366 0.344 + 0.011*sl 0.355 + 0.008*sl 0.377 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.154 0.141 + 0.006*sl 0.139 + 0.007*sl 0.142 + 0.007*sl t f 0.196 0.180 + 0.008*sl 0.185 + 0.007*sl 0.208 + 0.006*sl t plh 0.278 0.265 + 0.006*sl 0.273 + 0.004*sl 0.298 + 0.003*sl t phl 0.300 0.281 + 0.009*sl 0.293 + 0.006*sl 0.342 + 0.004*sl b to y t r 0.120 0.106 + 0.007*sl 0.108 + 0.007*sl 0.103 + 0.007*sl t f 0.194 0.178 + 0.008*sl 0.184 + 0.006*sl 0.200 + 0.006*sl t plh 0.439 0.426 + 0.006*sl 0.434 + 0.004*sl 0.459 + 0.003*sl t phl 0.465 0.448 + 0.009*sl 0.458 + 0.006*sl 0.504 + 0.004*sl c to y t r 0.183 0.170 + 0.007*sl 0.169 + 0.007*sl 0.170 + 0.007*sl t f 0.127 0.113 + 0.007*sl 0.118 + 0.006*sl 0.122 + 0.006*sl t plh 0.406 0.391 + 0.008*sl 0.402 + 0.005*sl 0.437 + 0.004*sl t phl 0.426 0.412 + 0.007*sl 0.421 + 0.005*sl 0.452 + 0.004*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-88 samsung asic ao21dh/ao21/ao21d2/ao21d2b/ao21d4 2-and into 2-nor with 0.5x/1x/2x/2x(bufferd)/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao21dh input load (sl) ao21dh ao21 ao21d2 ao21d2b ao21d4 abcabcabcabcabc 0.5 0.5 0.5 1.0 1.0 1.0 2.0 2.0 2.1 1.0 1.0 1.0 1.0 1.0 1.0 gate count ao21dh ao21 ao21d2 ao21d2b ao21d4 1.33 1.33 2.33 2.33 2.67 a b y c path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.359 0.129 + 0.115*sl 0.112 + 0.119*sl 0.104 + 0.120*sl t f 0.249 0.091 + 0.079*sl 0.074 + 0.084*sl 0.059 + 0.085*sl t plh 0.178 0.076 + 0.051*sl 0.074 + 0.051*sl 0.073 + 0.051*sl t phl 0.152 0.071 + 0.041*sl 0.071 + 0.040*sl 0.071 + 0.041*sl b to y t r 0.383 0.153 + 0.115*sl 0.134 + 0.120*sl 0.127 + 0.121*sl t f 0.244 0.083 + 0.080*sl 0.069 + 0.084*sl 0.060 + 0.085*sl t plh 0.191 0.089 + 0.051*sl 0.087 + 0.052*sl 0.086 + 0.052*sl t phl 0.146 0.064 + 0.041*sl 0.066 + 0.041*sl 0.065 + 0.041*sl c to y t r 0.378 0.143 + 0.118*sl 0.133 + 0.120*sl 0.128 + 0.121*sl t f 0.198 0.111 + 0.044*sl 0.097 + 0.047*sl 0.077 + 0.049*sl t plh 0.212 0.108 + 0.052*sl 0.109 + 0.052*sl 0.109 + 0.052*sl t phl 0.138 0.086 + 0.026*sl 0.088 + 0.026*sl 0.088 + 0.026*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table abcy 0x01 x001 other states 0
samsung asic 3-89 STD111 ao21dh/ao21/ao21d2/ao21d2b/ao21d4 2-and into 2-nor with 0.5x/1x/2x/2x(bufferd)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao21 ao21d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.228 0.125 + 0.051*sl 0.115 + 0.054*sl 0.097 + 0.056*sl t f 0.164 0.093 + 0.036*sl 0.080 + 0.039*sl 0.065 + 0.041*sl t plh 0.117 0.068 + 0.025*sl 0.071 + 0.024*sl 0.069 + 0.024*sl t phl 0.105 0.063 + 0.021*sl 0.070 + 0.019*sl 0.068 + 0.020*sl b to y t r 0.251 0.148 + 0.052*sl 0.136 + 0.055*sl 0.119 + 0.056*sl t f 0.158 0.085 + 0.036*sl 0.073 + 0.040*sl 0.063 + 0.041*sl t plh 0.132 0.084 + 0.024*sl 0.084 + 0.024*sl 0.082 + 0.024*sl t phl 0.099 0.057 + 0.021*sl 0.063 + 0.020*sl 0.062 + 0.020*sl c to y t r 0.242 0.135 + 0.054*sl 0.128 + 0.056*sl 0.119 + 0.056*sl t f 0.150 0.109 + 0.020*sl 0.103 + 0.022*sl 0.089 + 0.023*sl t plh 0.148 0.099 + 0.025*sl 0.100 + 0.024*sl 0.100 + 0.024*sl t phl 0.107 0.080 + 0.014*sl 0.085 + 0.012*sl 0.085 + 0.012*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.177 0.129 + 0.024*sl 0.120 + 0.027*sl 0.101 + 0.028*sl t f 0.130 0.097 + 0.017*sl 0.088 + 0.019*sl 0.069 + 0.020*sl t plh 0.094 0.067 + 0.013*sl 0.073 + 0.012*sl 0.072 + 0.012*sl t phl 0.084 0.060 + 0.012*sl 0.069 + 0.010*sl 0.069 + 0.010*sl b to y t r 0.200 0.150 + 0.025*sl 0.143 + 0.027*sl 0.123 + 0.028*sl t f 0.122 0.089 + 0.017*sl 0.078 + 0.020*sl 0.065 + 0.020*sl t plh 0.109 0.084 + 0.013*sl 0.087 + 0.012*sl 0.084 + 0.012*sl t phl 0.078 0.056 + 0.011*sl 0.061 + 0.010*sl 0.063 + 0.010*sl c to y t r 0.189 0.136 + 0.026*sl 0.131 + 0.028*sl 0.121 + 0.028*sl t f 0.128 0.108 + 0.010*sl 0.105 + 0.011*sl 0.090 + 0.012*sl t plh 0.120 0.094 + 0.013*sl 0.097 + 0.012*sl 0.097 + 0.012*sl t phl 0.094 0.078 + 0.008*sl 0.083 + 0.006*sl 0.085 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-90 samsung asic ao21dh/ao21/ao21d2/ao21d2b/ao21d4 2-and into 2-nor with 0.5x/1x/2x/2x(bufferd)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao21d2b ao21d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.078 0.051 + 0.013*sl 0.050 + 0.014*sl 0.040 + 0.014*sl t f 0.069 0.044 + 0.013*sl 0.048 + 0.012*sl 0.040 + 0.012*sl t plh 0.220 0.203 + 0.008*sl 0.209 + 0.007*sl 0.215 + 0.006*sl t phl 0.201 0.183 + 0.009*sl 0.191 + 0.007*sl 0.200 + 0.006*sl b to y t r 0.077 0.051 + 0.013*sl 0.049 + 0.014*sl 0.041 + 0.014*sl t f 0.070 0.046 + 0.012*sl 0.047 + 0.012*sl 0.041 + 0.012*sl t plh 0.238 0.222 + 0.008*sl 0.228 + 0.007*sl 0.234 + 0.006*sl t phl 0.196 0.178 + 0.009*sl 0.186 + 0.007*sl 0.195 + 0.006*sl c to y t r 0.078 0.051 + 0.013*sl 0.051 + 0.013*sl 0.039 + 0.014*sl t f 0.068 0.042 + 0.013*sl 0.047 + 0.012*sl 0.039 + 0.012*sl t plh 0.254 0.238 + 0.008*sl 0.243 + 0.007*sl 0.249 + 0.006*sl t phl 0.208 0.190 + 0.009*sl 0.198 + 0.007*sl 0.207 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.072 0.059 + 0.007*sl 0.059 + 0.007*sl 0.049 + 0.007*sl t f 0.065 0.054 + 0.006*sl 0.053 + 0.006*sl 0.051 + 0.006*sl t plh 0.241 0.231 + 0.005*sl 0.236 + 0.004*sl 0.247 + 0.003*sl t phl 0.222 0.212 + 0.005*sl 0.217 + 0.004*sl 0.233 + 0.003*sl b to y t r 0.073 0.059 + 0.007*sl 0.060 + 0.007*sl 0.049 + 0.007*sl t f 0.065 0.051 + 0.007*sl 0.055 + 0.006*sl 0.051 + 0.006*sl t plh 0.258 0.248 + 0.005*sl 0.253 + 0.004*sl 0.264 + 0.003*sl t phl 0.216 0.206 + 0.005*sl 0.211 + 0.004*sl 0.227 + 0.003*sl c to y t r 0.073 0.059 + 0.007*sl 0.060 + 0.007*sl 0.049 + 0.007*sl t f 0.064 0.052 + 0.006*sl 0.054 + 0.006*sl 0.050 + 0.006*sl t plh 0.274 0.265 + 0.005*sl 0.269 + 0.003*sl 0.280 + 0.003*sl t phl 0.225 0.214 + 0.005*sl 0.220 + 0.004*sl 0.235 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-91 STD111 ao211dh/ao211/ao211d2/ao211d2b/ao211d4 2-and into 3-nor with 0.5x/1x/2x/2x(buffered)/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao211dh input load (sl) ao211dh ao211 ao211d2 ao211d2b ao211d4 abcdabcdabcdabcdabcd 0.5 0.5 0.5 0.5 0.9 0.9 0.9 0.9 2.0 1.9 1.8 1.8 0.9 1.0 0.9 0.9 0.9 0.9 0.9 0.9 gate count ao211dh ao211 ao211d2 ao211d2b ao211d4 1.67 1.67 2.67 2.67 3.00 a b y c d path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.565 0.221 + 0.172*sl 0.206 + 0.176*sl 0.214 + 0.175*sl t f 0.299 0.109 + 0.095*sl 0.093 + 0.099*sl 0.085 + 0.100*sl t plh 0.238 0.088 + 0.075*sl 0.086 + 0.075*sl 0.086 + 0.075*sl t phl 0.182 0.088 + 0.047*sl 0.087 + 0.048*sl 0.087 + 0.048*sl b to y t r 0.591 0.248 + 0.172*sl 0.233 + 0.176*sl 0.241 + 0.175*sl t f 0.296 0.104 + 0.096*sl 0.092 + 0.099*sl 0.085 + 0.100*sl t plh 0.253 0.105 + 0.074*sl 0.103 + 0.075*sl 0.102 + 0.075*sl t phl 0.177 0.082 + 0.048*sl 0.082 + 0.048*sl 0.082 + 0.048*sl c to y t r 0.600 0.257 + 0.171*sl 0.246 + 0.174*sl 0.243 + 0.175*sl t f 0.262 0.134 + 0.064*sl 0.121 + 0.067*sl 0.110 + 0.068*sl t plh 0.309 0.158 + 0.076*sl 0.160 + 0.075*sl 0.162 + 0.075*sl t phl 0.186 0.115 + 0.036*sl 0.116 + 0.035*sl 0.118 + 0.035*sl d to y t r 0.599 0.255 + 0.172*sl 0.246 + 0.174*sl 0.243 + 0.175*sl t f 0.289 0.162 + 0.064*sl 0.149 + 0.067*sl 0.136 + 0.068*sl t plh 0.316 0.165 + 0.076*sl 0.167 + 0.075*sl 0.169 + 0.075*sl t phl 0.196 0.123 + 0.037*sl 0.127 + 0.036*sl 0.130 + 0.035*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table abcdy 0x001 x0001 other states 0
STD111 3-92 samsung asic ao211dh/ao211/ao211d2/ao211d2b/ao211d4 2-and into 3-nor with 0.5x/1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao211 ao211d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.361 0.202 + 0.080*sl 0.192 + 0.082*sl 0.180 + 0.083*sl t f 0.191 0.106 + 0.043*sl 0.094 + 0.046*sl 0.080 + 0.047*sl t plh 0.153 0.085 + 0.034*sl 0.079 + 0.035*sl 0.079 + 0.035*sl t phl 0.126 0.079 + 0.023*sl 0.082 + 0.023*sl 0.081 + 0.023*sl b to y t r 0.386 0.230 + 0.078*sl 0.218 + 0.081*sl 0.205 + 0.083*sl t f 0.186 0.097 + 0.044*sl 0.089 + 0.046*sl 0.079 + 0.047*sl t plh 0.167 0.099 + 0.034*sl 0.095 + 0.035*sl 0.094 + 0.035*sl t phl 0.120 0.073 + 0.024*sl 0.076 + 0.023*sl 0.075 + 0.023*sl c to y t r 0.391 0.233 + 0.079*sl 0.225 + 0.081*sl 0.217 + 0.082*sl t f 0.188 0.129 + 0.030*sl 0.123 + 0.031*sl 0.109 + 0.033*sl t plh 0.213 0.142 + 0.036*sl 0.143 + 0.036*sl 0.145 + 0.035*sl t phl 0.143 0.108 + 0.017*sl 0.109 + 0.017*sl 0.111 + 0.017*sl d to y t r 0.389 0.229 + 0.080*sl 0.223 + 0.082*sl 0.216 + 0.082*sl t f 0.215 0.155 + 0.030*sl 0.150 + 0.031*sl 0.136 + 0.033*sl t plh 0.221 0.149 + 0.036*sl 0.150 + 0.036*sl 0.152 + 0.035*sl t phl 0.153 0.116 + 0.018*sl 0.119 + 0.018*sl 0.122 + 0.017*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.277 0.198 + 0.040*sl 0.192 + 0.041*sl 0.175 + 0.042*sl t f 0.147 0.105 + 0.021*sl 0.097 + 0.023*sl 0.080 + 0.024*sl t plh 0.117 0.082 + 0.017*sl 0.081 + 0.018*sl 0.078 + 0.018*sl t phl 0.102 0.076 + 0.013*sl 0.082 + 0.012*sl 0.081 + 0.012*sl b to y t r 0.302 0.225 + 0.039*sl 0.217 + 0.041*sl 0.200 + 0.042*sl t f 0.142 0.098 + 0.022*sl 0.092 + 0.024*sl 0.079 + 0.024*sl t plh 0.131 0.097 + 0.017*sl 0.095 + 0.018*sl 0.092 + 0.018*sl t phl 0.095 0.069 + 0.013*sl 0.074 + 0.012*sl 0.074 + 0.012*sl c to y t r 0.306 0.227 + 0.039*sl 0.222 + 0.041*sl 0.211 + 0.042*sl t f 0.159 0.129 + 0.015*sl 0.125 + 0.016*sl 0.110 + 0.017*sl t plh 0.175 0.138 + 0.018*sl 0.139 + 0.018*sl 0.141 + 0.018*sl t phl 0.126 0.107 + 0.009*sl 0.109 + 0.009*sl 0.110 + 0.009*sl d to y t r 0.304 0.224 + 0.040*sl 0.220 + 0.041*sl 0.210 + 0.042*sl t f 0.185 0.155 + 0.015*sl 0.153 + 0.016*sl 0.139 + 0.017*sl t plh 0.182 0.145 + 0.018*sl 0.146 + 0.018*sl 0.149 + 0.018*sl t phl 0.135 0.117 + 0.009*sl 0.118 + 0.009*sl 0.121 + 0.009*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-93 STD111 ao211dh/ao211/ao211d2/ao211d2b/ao211d4 2-and into 3-nor with 0.5x/1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao211d2b ao211d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.083 0.057 + 0.013*sl 0.056 + 0.013*sl 0.044 + 0.014*sl t f 0.070 0.045 + 0.013*sl 0.049 + 0.012*sl 0.041 + 0.012*sl t plh 0.260 0.244 + 0.008*sl 0.250 + 0.007*sl 0.257 + 0.006*sl t phl 0.224 0.206 + 0.009*sl 0.213 + 0.007*sl 0.223 + 0.006*sl b to y t r 0.083 0.057 + 0.013*sl 0.055 + 0.013*sl 0.045 + 0.014*sl t f 0.071 0.047 + 0.012*sl 0.048 + 0.012*sl 0.042 + 0.012*sl t plh 0.280 0.263 + 0.008*sl 0.269 + 0.007*sl 0.276 + 0.006*sl t phl 0.218 0.200 + 0.009*sl 0.207 + 0.007*sl 0.217 + 0.006*sl c to y t r 0.085 0.058 + 0.013*sl 0.057 + 0.013*sl 0.045 + 0.014*sl t f 0.069 0.044 + 0.013*sl 0.048 + 0.012*sl 0.041 + 0.012*sl t plh 0.325 0.308 + 0.008*sl 0.315 + 0.007*sl 0.321 + 0.006*sl t phl 0.246 0.228 + 0.009*sl 0.236 + 0.007*sl 0.245 + 0.006*sl d to y t r 0.084 0.057 + 0.013*sl 0.058 + 0.013*sl 0.044 + 0.014*sl t f 0.070 0.046 + 0.012*sl 0.049 + 0.012*sl 0.042 + 0.012*sl t plh 0.331 0.315 + 0.008*sl 0.321 + 0.007*sl 0.328 + 0.006*sl t phl 0.259 0.241 + 0.009*sl 0.249 + 0.007*sl 0.258 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.079 0.066 + 0.006*sl 0.066 + 0.007*sl 0.054 + 0.007*sl t f 0.066 0.053 + 0.006*sl 0.055 + 0.006*sl 0.052 + 0.006*sl t plh 0.285 0.276 + 0.005*sl 0.281 + 0.004*sl 0.292 + 0.003*sl t phl 0.244 0.233 + 0.005*sl 0.239 + 0.004*sl 0.254 + 0.003*sl b to y t r 0.080 0.067 + 0.006*sl 0.067 + 0.007*sl 0.054 + 0.007*sl t f 0.066 0.054 + 0.006*sl 0.055 + 0.006*sl 0.052 + 0.006*sl t plh 0.304 0.294 + 0.005*sl 0.300 + 0.004*sl 0.311 + 0.003*sl t phl 0.237 0.227 + 0.005*sl 0.232 + 0.004*sl 0.248 + 0.003*sl c to y t r 0.080 0.068 + 0.006*sl 0.066 + 0.007*sl 0.055 + 0.007*sl t f 0.065 0.054 + 0.005*sl 0.053 + 0.006*sl 0.050 + 0.006*sl t plh 0.349 0.340 + 0.005*sl 0.345 + 0.004*sl 0.357 + 0.003*sl t phl 0.264 0.254 + 0.005*sl 0.259 + 0.004*sl 0.274 + 0.003*sl d to y t r 0.080 0.067 + 0.006*sl 0.067 + 0.007*sl 0.055 + 0.007*sl t f 0.066 0.052 + 0.007*sl 0.055 + 0.006*sl 0.052 + 0.006*sl t plh 0.358 0.348 + 0.005*sl 0.353 + 0.004*sl 0.365 + 0.003*sl t phl 0.279 0.268 + 0.005*sl 0.274 + 0.004*sl 0.289 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-94 samsung asic ao2111/ao2111d2 2-and into 4-nor with 1x/2x drive logic symbol cell data input load (sl) gate count a02111 ao2111d2 ao2111 ao2111d2 abcdeabcde 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 2.00 2.67 y c d a b e truth table abcdey 11xxx0 xx1xx0 xxx1x0 xxxx10 other states 1
samsung asic 3-95 STD111 ao2111/ao2111d2 2-and into 4-nor with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao2111 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.510 0.293 + 0.108*sl 0.284 + 0.111*sl 0.281 + 0.111*sl t f 0.198 0.112 + 0.043*sl 0.101 + 0.046*sl 0.088 + 0.047*sl t plh 0.183 0.093 + 0.045*sl 0.084 + 0.047*sl 0.084 + 0.047*sl t phl 0.130 0.084 + 0.023*sl 0.086 + 0.023*sl 0.085 + 0.023*sl b to y t r 0.544 0.330 + 0.107*sl 0.318 + 0.110*sl 0.314 + 0.111*sl t f 0.193 0.105 + 0.044*sl 0.096 + 0.046*sl 0.087 + 0.047*sl t plh 0.201 0.111 + 0.045*sl 0.105 + 0.047*sl 0.103 + 0.047*sl t phl 0.124 0.078 + 0.023*sl 0.080 + 0.023*sl 0.080 + 0.023*sl c to y t r 0.568 0.355 + 0.107*sl 0.347 + 0.109*sl 0.342 + 0.109*sl t f 0.212 0.143 + 0.035*sl 0.137 + 0.036*sl 0.126 + 0.038*sl t plh 0.278 0.182 + 0.048*sl 0.185 + 0.047*sl 0.187 + 0.047*sl t phl 0.163 0.123 + 0.020*sl 0.124 + 0.020*sl 0.126 + 0.020*sl d to y t r 0.569 0.356 + 0.107*sl 0.349 + 0.109*sl 0.342 + 0.109*sl t f 0.242 0.172 + 0.035*sl 0.167 + 0.036*sl 0.156 + 0.037*sl t plh 0.307 0.211 + 0.048*sl 0.213 + 0.047*sl 0.216 + 0.047*sl t phl 0.176 0.135 + 0.021*sl 0.137 + 0.020*sl 0.141 + 0.020*sl e to y t r 0.568 0.354 + 0.107*sl 0.348 + 0.109*sl 0.342 + 0.109*sl t f 0.270 0.199 + 0.035*sl 0.195 + 0.037*sl 0.186 + 0.038*sl t plh 0.319 0.222 + 0.048*sl 0.225 + 0.047*sl 0.228 + 0.047*sl t phl 0.183 0.140 + 0.022*sl 0.144 + 0.021*sl 0.151 + 0.020*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-96 samsung asic ao2111/ao2111d2 2-and into 4-nor with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao2111d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.088 0.063 + 0.013*sl 0.060 + 0.013*sl 0.049 + 0.014*sl t f 0.073 0.049 + 0.012*sl 0.050 + 0.012*sl 0.043 + 0.012*sl t plh 0.282 0.265 + 0.008*sl 0.271 + 0.007*sl 0.279 + 0.006*sl t phl 0.222 0.204 + 0.009*sl 0.211 + 0.007*sl 0.221 + 0.006*sl b to y t r 0.091 0.065 + 0.013*sl 0.065 + 0.013*sl 0.050 + 0.014*sl t f 0.071 0.046 + 0.013*sl 0.050 + 0.012*sl 0.043 + 0.012*sl t plh 0.309 0.292 + 0.008*sl 0.299 + 0.007*sl 0.306 + 0.006*sl t phl 0.216 0.199 + 0.009*sl 0.206 + 0.007*sl 0.215 + 0.006*sl c to y t r 0.092 0.066 + 0.013*sl 0.066 + 0.013*sl 0.050 + 0.014*sl t f 0.071 0.045 + 0.013*sl 0.050 + 0.012*sl 0.043 + 0.012*sl t plh 0.382 0.365 + 0.008*sl 0.371 + 0.007*sl 0.379 + 0.006*sl t phl 0.266 0.248 + 0.009*sl 0.255 + 0.007*sl 0.265 + 0.006*sl d to y t r 0.091 0.067 + 0.012*sl 0.064 + 0.013*sl 0.051 + 0.014*sl t f 0.072 0.046 + 0.013*sl 0.052 + 0.012*sl 0.043 + 0.012*sl t plh 0.411 0.394 + 0.008*sl 0.401 + 0.007*sl 0.408 + 0.006*sl t phl 0.284 0.266 + 0.009*sl 0.273 + 0.007*sl 0.283 + 0.006*sl e to y t r 0.092 0.065 + 0.013*sl 0.066 + 0.013*sl 0.050 + 0.014*sl t f 0.073 0.048 + 0.013*sl 0.052 + 0.012*sl 0.044 + 0.012*sl t plh 0.423 0.406 + 0.008*sl 0.413 + 0.007*sl 0.420 + 0.006*sl t phl 0.295 0.277 + 0.009*sl 0.284 + 0.007*sl 0.294 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-97 STD111 ao22dh/ao22/ao22d2/ao22d2b/ao22d4 two 2-ands into 2-nor with 0.5x/1x/2x/2x(buffered)/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao22dh input load (sl) ao22dh ao22 ao22d2 ao22d2b ao22d4 abcdabcdabcdabcdabcd 0.5 0.5 0.5 0.5 1.0 1.1 1.0 1.1 2.1 2.1 2.1 2.1 1.1 1.1 1.1 1.2 1.1 1.1 1.1 1.2 gate count ao22dh ao22 ao22d2 ao22d2b ao22d4 1.67 1.67 2.67 2.67 3.00 c d a b y path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.395 0.162 + 0.116*sl 0.147 + 0.120*sl 0.143 + 0.121*sl t f 0.254 0.116 + 0.069*sl 0.098 + 0.074*sl 0.082 + 0.075*sl t plh 0.197 0.094 + 0.051*sl 0.093 + 0.052*sl 0.093 + 0.052*sl t phl 0.146 0.073 + 0.036*sl 0.075 + 0.036*sl 0.075 + 0.036*sl b to y t r 0.416 0.185 + 0.115*sl 0.171 + 0.119*sl 0.166 + 0.119*sl t f 0.248 0.106 + 0.071*sl 0.094 + 0.074*sl 0.082 + 0.075*sl t plh 0.210 0.109 + 0.050*sl 0.107 + 0.051*sl 0.106 + 0.051*sl t phl 0.141 0.067 + 0.037*sl 0.070 + 0.036*sl 0.070 + 0.036*sl c to y t r 0.391 0.159 + 0.116*sl 0.148 + 0.119*sl 0.144 + 0.119*sl t f 0.299 0.159 + 0.070*sl 0.144 + 0.074*sl 0.131 + 0.075*sl t plh 0.228 0.124 + 0.052*sl 0.126 + 0.051*sl 0.128 + 0.051*sl t phl 0.187 0.113 + 0.037*sl 0.116 + 0.036*sl 0.118 + 0.036*sl d to y t r 0.415 0.182 + 0.116*sl 0.173 + 0.119*sl 0.168 + 0.119*sl t f 0.294 0.151 + 0.072*sl 0.141 + 0.074*sl 0.132 + 0.075*sl t plh 0.243 0.141 + 0.051*sl 0.141 + 0.051*sl 0.142 + 0.051*sl t phl 0.181 0.107 + 0.037*sl 0.110 + 0.036*sl 0.113 + 0.036*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table abcdy 11xx0 xx110 0x0x1 0xx01 x0x01 x00x1
STD111 3-98 samsung asic ao22dh/ao22/ao22d2/ao22d2b/ao22d4 two 2-ands into 2-nor with 0.5x/1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao22 ao22d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.257 0.151 + 0.053*sl 0.144 + 0.055*sl 0.130 + 0.057*sl t f 0.178 0.117 + 0.031*sl 0.104 + 0.034*sl 0.089 + 0.036*sl t plh 0.137 0.089 + 0.024*sl 0.088 + 0.024*sl 0.088 + 0.024*sl t phl 0.103 0.065 + 0.019*sl 0.072 + 0.017*sl 0.072 + 0.017*sl b to y t r 0.281 0.176 + 0.052*sl 0.167 + 0.055*sl 0.153 + 0.056*sl t f 0.170 0.108 + 0.031*sl 0.096 + 0.035*sl 0.084 + 0.036*sl t plh 0.151 0.104 + 0.023*sl 0.102 + 0.024*sl 0.101 + 0.024*sl t phl 0.097 0.059 + 0.019*sl 0.065 + 0.017*sl 0.066 + 0.017*sl c to y t r 0.253 0.146 + 0.053*sl 0.139 + 0.055*sl 0.131 + 0.056*sl t f 0.216 0.151 + 0.033*sl 0.144 + 0.034*sl 0.131 + 0.036*sl t plh 0.162 0.113 + 0.025*sl 0.114 + 0.024*sl 0.116 + 0.024*sl t phl 0.143 0.107 + 0.018*sl 0.108 + 0.017*sl 0.110 + 0.017*sl d to y t r 0.275 0.167 + 0.054*sl 0.162 + 0.055*sl 0.155 + 0.056*sl t f 0.210 0.143 + 0.033*sl 0.137 + 0.035*sl 0.129 + 0.036*sl t plh 0.177 0.128 + 0.024*sl 0.129 + 0.024*sl 0.129 + 0.024*sl t phl 0.136 0.100 + 0.018*sl 0.102 + 0.018*sl 0.104 + 0.017*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.206 0.154 + 0.026*sl 0.149 + 0.027*sl 0.133 + 0.028*sl t f 0.150 0.121 + 0.014*sl 0.112 + 0.017*sl 0.094 + 0.018*sl t plh 0.115 0.090 + 0.012*sl 0.091 + 0.012*sl 0.090 + 0.012*sl t phl 0.086 0.065 + 0.011*sl 0.072 + 0.009*sl 0.073 + 0.009*sl b to y t r 0.230 0.178 + 0.026*sl 0.173 + 0.028*sl 0.158 + 0.028*sl t f 0.142 0.114 + 0.014*sl 0.102 + 0.017*sl 0.089 + 0.018*sl t plh 0.130 0.107 + 0.012*sl 0.106 + 0.012*sl 0.104 + 0.012*sl t phl 0.080 0.060 + 0.010*sl 0.065 + 0.009*sl 0.067 + 0.009*sl c to y t r 0.201 0.148 + 0.027*sl 0.144 + 0.028*sl 0.134 + 0.028*sl t f 0.184 0.151 + 0.016*sl 0.148 + 0.017*sl 0.133 + 0.018*sl t plh 0.136 0.110 + 0.013*sl 0.113 + 0.012*sl 0.114 + 0.012*sl t phl 0.125 0.106 + 0.009*sl 0.108 + 0.009*sl 0.109 + 0.009*sl d to y t r 0.224 0.170 + 0.027*sl 0.167 + 0.028*sl 0.158 + 0.029*sl t f 0.177 0.143 + 0.017*sl 0.141 + 0.018*sl 0.129 + 0.018*sl t plh 0.152 0.127 + 0.012*sl 0.127 + 0.012*sl 0.128 + 0.012*sl t phl 0.118 0.099 + 0.010*sl 0.101 + 0.009*sl 0.103 + 0.009*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-99 STD111 ao22dh/ao22/ao22d2/ao22d2b/ao22d4 two 2-ands into 2-nor with 0.5x/1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao22d2b ao22d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.080 0.053 + 0.013*sl 0.052 + 0.014*sl 0.042 + 0.014*sl t f 0.071 0.046 + 0.012*sl 0.049 + 0.012*sl 0.042 + 0.012*sl t plh 0.249 0.233 + 0.008*sl 0.238 + 0.007*sl 0.244 + 0.006*sl t phl 0.209 0.192 + 0.009*sl 0.199 + 0.007*sl 0.208 + 0.006*sl b to y t r 0.080 0.053 + 0.013*sl 0.053 + 0.013*sl 0.042 + 0.014*sl t f 0.071 0.047 + 0.012*sl 0.048 + 0.012*sl 0.042 + 0.012*sl t plh 0.266 0.250 + 0.008*sl 0.255 + 0.007*sl 0.261 + 0.006*sl t phl 0.204 0.186 + 0.009*sl 0.193 + 0.007*sl 0.202 + 0.006*sl c to y t r 0.080 0.053 + 0.013*sl 0.053 + 0.013*sl 0.041 + 0.014*sl t f 0.071 0.046 + 0.013*sl 0.050 + 0.012*sl 0.042 + 0.012*sl t plh 0.266 0.249 + 0.008*sl 0.255 + 0.007*sl 0.261 + 0.006*sl t phl 0.248 0.230 + 0.009*sl 0.237 + 0.007*sl 0.247 + 0.006*sl d to y t r 0.080 0.054 + 0.013*sl 0.053 + 0.013*sl 0.042 + 0.014*sl t f 0.071 0.045 + 0.013*sl 0.050 + 0.012*sl 0.042 + 0.012*sl t plh 0.285 0.269 + 0.008*sl 0.274 + 0.007*sl 0.280 + 0.006*sl t phl 0.241 0.223 + 0.009*sl 0.230 + 0.007*sl 0.240 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.074 0.060 + 0.007*sl 0.061 + 0.007*sl 0.050 + 0.007*sl t f 0.066 0.053 + 0.007*sl 0.057 + 0.006*sl 0.051 + 0.006*sl t plh 0.268 0.258 + 0.005*sl 0.263 + 0.003*sl 0.273 + 0.003*sl t phl 0.225 0.215 + 0.005*sl 0.220 + 0.004*sl 0.235 + 0.003*sl b to y t r 0.075 0.061 + 0.007*sl 0.062 + 0.007*sl 0.050 + 0.007*sl t f 0.066 0.054 + 0.006*sl 0.055 + 0.006*sl 0.052 + 0.006*sl t plh 0.284 0.275 + 0.005*sl 0.279 + 0.003*sl 0.290 + 0.003*sl t phl 0.219 0.209 + 0.005*sl 0.214 + 0.004*sl 0.229 + 0.003*sl c to y t r 0.074 0.060 + 0.007*sl 0.062 + 0.007*sl 0.050 + 0.007*sl t f 0.067 0.054 + 0.006*sl 0.056 + 0.006*sl 0.053 + 0.006*sl t plh 0.284 0.275 + 0.005*sl 0.279 + 0.003*sl 0.290 + 0.003*sl t phl 0.263 0.253 + 0.005*sl 0.258 + 0.004*sl 0.274 + 0.003*sl d to y t r 0.075 0.062 + 0.007*sl 0.062 + 0.007*sl 0.051 + 0.007*sl t f 0.067 0.055 + 0.006*sl 0.055 + 0.006*sl 0.052 + 0.006*sl t plh 0.301 0.292 + 0.005*sl 0.297 + 0.003*sl 0.307 + 0.003*sl t phl 0.257 0.246 + 0.005*sl 0.251 + 0.004*sl 0.267 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-100 samsung asic ao22dha/ao22a/ao22d2a/ao22d4a 2-and and 2-nor into 2-nor with 0.5x/1x/2x/4x drive logic symbol cell data input load (sl) ao22dha ao22a ao22d2a ao22d4a abcdabcdabcdabcd 0.5 0.6 0.5 0.5 1.0 1.1 0.9 0.9 2.1 2.1 0.9 0.9 1.1 1.1 0.9 0.9 gate count ao22dha ao22a ao22d2a ao22d4a 2.33 2.67 3.67 4.00 c d a b y truth table abcdy 11xx0 xx000 other states 1
samsung asic 3-101 STD111 ao22dha/ao22a/ao22d2a/ao22d4a 2-and and 2-nor into 2-nor with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao22dha ao22a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.383 0.153 + 0.115*sl 0.138 + 0.119*sl 0.133 + 0.119*sl t f 0.252 0.114 + 0.069*sl 0.096 + 0.074*sl 0.080 + 0.075*sl t plh 0.195 0.094 + 0.051*sl 0.093 + 0.051*sl 0.093 + 0.051*sl t phl 0.144 0.071 + 0.036*sl 0.073 + 0.036*sl 0.074 + 0.036*sl b to y t r 0.405 0.177 + 0.114*sl 0.161 + 0.118*sl 0.156 + 0.119*sl t f 0.246 0.104 + 0.071*sl 0.091 + 0.074*sl 0.080 + 0.075*sl t plh 0.209 0.108 + 0.050*sl 0.106 + 0.051*sl 0.105 + 0.051*sl t phl 0.138 0.064 + 0.037*sl 0.067 + 0.036*sl 0.068 + 0.036*sl c to y t r 0.382 0.144 + 0.119*sl 0.138 + 0.121*sl 0.136 + 0.121*sl t f 0.277 0.130 + 0.073*sl 0.124 + 0.075*sl 0.120 + 0.075*sl t plh 0.305 0.200 + 0.053*sl 0.203 + 0.052*sl 0.205 + 0.052*sl t phl 0.228 0.154 + 0.037*sl 0.157 + 0.036*sl 0.159 + 0.036*sl d to y t r 0.399 0.165 + 0.117*sl 0.160 + 0.118*sl 0.158 + 0.119*sl t f 0.276 0.128 + 0.074*sl 0.124 + 0.075*sl 0.120 + 0.075*sl t plh 0.321 0.218 + 0.051*sl 0.220 + 0.051*sl 0.221 + 0.051*sl t phl 0.232 0.157 + 0.037*sl 0.161 + 0.036*sl 0.164 + 0.036*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.258 0.152 + 0.053*sl 0.145 + 0.055*sl 0.130 + 0.057*sl t f 0.178 0.117 + 0.031*sl 0.105 + 0.034*sl 0.089 + 0.036*sl t plh 0.137 0.089 + 0.024*sl 0.088 + 0.024*sl 0.087 + 0.024*sl t phl 0.103 0.065 + 0.019*sl 0.072 + 0.017*sl 0.072 + 0.017*sl b to y t r 0.282 0.177 + 0.052*sl 0.168 + 0.055*sl 0.154 + 0.056*sl t f 0.171 0.108 + 0.032*sl 0.096 + 0.035*sl 0.084 + 0.036*sl t plh 0.151 0.104 + 0.023*sl 0.102 + 0.024*sl 0.101 + 0.024*sl t phl 0.097 0.059 + 0.019*sl 0.065 + 0.017*sl 0.066 + 0.017*sl c to y t r 0.248 0.138 + 0.055*sl 0.134 + 0.056*sl 0.130 + 0.056*sl t f 0.202 0.133 + 0.035*sl 0.130 + 0.035*sl 0.125 + 0.036*sl t plh 0.244 0.194 + 0.025*sl 0.196 + 0.024*sl 0.198 + 0.024*sl t phl 0.183 0.146 + 0.018*sl 0.149 + 0.018*sl 0.152 + 0.017*sl d to y t r 0.271 0.161 + 0.055*sl 0.157 + 0.056*sl 0.153 + 0.056*sl t f 0.200 0.130 + 0.035*sl 0.128 + 0.036*sl 0.124 + 0.036*sl t plh 0.254 0.204 + 0.025*sl 0.206 + 0.024*sl 0.208 + 0.024*sl t phl 0.183 0.146 + 0.018*sl 0.149 + 0.018*sl 0.152 + 0.017*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-102 samsung asic ao22dha/ao22a/ao22d2a/ao22d4a 2-and and 2-nor into 2-nor with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao22d2a ao22d4a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.208 0.155 + 0.026*sl 0.151 + 0.027*sl 0.135 + 0.028*sl t f 0.150 0.121 + 0.015*sl 0.112 + 0.017*sl 0.094 + 0.018*sl t plh 0.114 0.090 + 0.012*sl 0.090 + 0.012*sl 0.089 + 0.012*sl t phl 0.086 0.064 + 0.011*sl 0.071 + 0.009*sl 0.073 + 0.009*sl b to y t r 0.232 0.180 + 0.026*sl 0.175 + 0.027*sl 0.159 + 0.028*sl t f 0.142 0.113 + 0.015*sl 0.103 + 0.017*sl 0.090 + 0.018*sl t plh 0.130 0.106 + 0.012*sl 0.105 + 0.012*sl 0.103 + 0.012*sl t phl 0.079 0.059 + 0.010*sl 0.064 + 0.009*sl 0.067 + 0.009*sl c to y t r 0.198 0.144 + 0.027*sl 0.140 + 0.028*sl 0.134 + 0.028*sl t f 0.173 0.138 + 0.017*sl 0.136 + 0.018*sl 0.130 + 0.018*sl t plh 0.238 0.212 + 0.013*sl 0.214 + 0.012*sl 0.217 + 0.012*sl t phl 0.187 0.168 + 0.010*sl 0.170 + 0.009*sl 0.173 + 0.009*sl d to y t r 0.223 0.168 + 0.027*sl 0.165 + 0.028*sl 0.159 + 0.029*sl t f 0.170 0.134 + 0.018*sl 0.134 + 0.018*sl 0.129 + 0.018*sl t plh 0.252 0.227 + 0.013*sl 0.228 + 0.012*sl 0.230 + 0.012*sl t phl 0.189 0.170 + 0.010*sl 0.172 + 0.009*sl 0.176 + 0.009*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.074 0.060 + 0.007*sl 0.061 + 0.007*sl 0.049 + 0.007*sl t f 0.066 0.052 + 0.007*sl 0.056 + 0.006*sl 0.051 + 0.006*sl t plh 0.267 0.258 + 0.005*sl 0.263 + 0.003*sl 0.273 + 0.003*sl t phl 0.225 0.214 + 0.005*sl 0.220 + 0.004*sl 0.235 + 0.003*sl b to y t r 0.074 0.061 + 0.007*sl 0.061 + 0.007*sl 0.050 + 0.007*sl t f 0.067 0.056 + 0.006*sl 0.055 + 0.006*sl 0.051 + 0.006*sl t plh 0.284 0.274 + 0.005*sl 0.279 + 0.003*sl 0.290 + 0.003*sl t phl 0.219 0.208 + 0.005*sl 0.214 + 0.004*sl 0.229 + 0.003*sl c to y t r 0.074 0.061 + 0.007*sl 0.060 + 0.007*sl 0.050 + 0.007*sl t f 0.066 0.053 + 0.007*sl 0.056 + 0.006*sl 0.052 + 0.006*sl t plh 0.367 0.358 + 0.005*sl 0.363 + 0.004*sl 0.373 + 0.003*sl t phl 0.306 0.295 + 0.005*sl 0.301 + 0.004*sl 0.316 + 0.003*sl d to y t r 0.075 0.062 + 0.006*sl 0.061 + 0.007*sl 0.050 + 0.007*sl t f 0.066 0.053 + 0.007*sl 0.057 + 0.006*sl 0.052 + 0.006*sl t plh 0.382 0.372 + 0.005*sl 0.377 + 0.004*sl 0.388 + 0.003*sl t phl 0.307 0.297 + 0.005*sl 0.302 + 0.004*sl 0.318 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-103 STD111 ao221/ao221d2/ao221d4 two 2-ands into 3-nor with 1x/2x/4x drive logic symbol cell data input load (sl) ao221 ao221d2 ao221d4 abcdeabcdeabcde 1.0 1.0 1.0 1.1 1.0 1.0 1.0 1.0 1.1 1.0 1.0 1.0 1.0 1.0 1.0 gate count ao221 ao221d2 ao221d4 2.00 3.00 3.67 c d a b y e truth table abcdey 11xxx0 xx11x0 xxxx10 other states 1
STD111 3-104 samsung asic ao221/ao221d2/ao221d4 two 2-ands into 3-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao221 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.398 0.235 + 0.081*sl 0.226 + 0.084*sl 0.217 + 0.085*sl t f 0.199 0.124 + 0.038*sl 0.114 + 0.040*sl 0.099 + 0.042*sl t plh 0.173 0.103 + 0.035*sl 0.100 + 0.036*sl 0.100 + 0.036*sl t phl 0.120 0.078 + 0.021*sl 0.081 + 0.020*sl 0.081 + 0.020*sl b to y t r 0.430 0.267 + 0.082*sl 0.257 + 0.084*sl 0.248 + 0.085*sl t f 0.193 0.116 + 0.038*sl 0.106 + 0.041*sl 0.097 + 0.042*sl t plh 0.192 0.121 + 0.035*sl 0.118 + 0.036*sl 0.117 + 0.036*sl t phl 0.114 0.071 + 0.021*sl 0.075 + 0.020*sl 0.076 + 0.020*sl c to y t r 0.405 0.244 + 0.081*sl 0.237 + 0.082*sl 0.229 + 0.083*sl t f 0.238 0.160 + 0.039*sl 0.153 + 0.041*sl 0.140 + 0.042*sl t plh 0.222 0.149 + 0.037*sl 0.151 + 0.036*sl 0.154 + 0.036*sl t phl 0.160 0.119 + 0.021*sl 0.120 + 0.020*sl 0.121 + 0.020*sl d to y t r 0.440 0.275 + 0.082*sl 0.269 + 0.084*sl 0.263 + 0.085*sl t f 0.233 0.153 + 0.040*sl 0.149 + 0.041*sl 0.140 + 0.042*sl t plh 0.245 0.171 + 0.037*sl 0.172 + 0.036*sl 0.174 + 0.036*sl t phl 0.154 0.113 + 0.021*sl 0.114 + 0.020*sl 0.116 + 0.020*sl e to y t r 0.438 0.273 + 0.083*sl 0.268 + 0.084*sl 0.262 + 0.085*sl t f 0.210 0.160 + 0.025*sl 0.156 + 0.026*sl 0.146 + 0.027*sl t plh 0.269 0.195 + 0.037*sl 0.196 + 0.037*sl 0.199 + 0.036*sl t phl 0.144 0.113 + 0.016*sl 0.115 + 0.015*sl 0.120 + 0.015*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-105 STD111 ao221/ao221d2/ao221d4 two 2-ands into 3-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao221d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.085 0.059 + 0.013*sl 0.057 + 0.013*sl 0.046 + 0.014*sl t f 0.072 0.046 + 0.013*sl 0.051 + 0.011*sl 0.043 + 0.012*sl t plh 0.290 0.273 + 0.008*sl 0.280 + 0.007*sl 0.287 + 0.006*sl t phl 0.227 0.209 + 0.009*sl 0.216 + 0.007*sl 0.226 + 0.006*sl b to y t r 0.087 0.061 + 0.013*sl 0.060 + 0.013*sl 0.047 + 0.014*sl t f 0.072 0.049 + 0.012*sl 0.050 + 0.012*sl 0.043 + 0.012*sl t plh 0.313 0.297 + 0.008*sl 0.303 + 0.007*sl 0.310 + 0.006*sl t phl 0.221 0.203 + 0.009*sl 0.210 + 0.007*sl 0.220 + 0.006*sl c to y t r 0.086 0.060 + 0.013*sl 0.060 + 0.013*sl 0.046 + 0.014*sl t f 0.073 0.050 + 0.012*sl 0.050 + 0.012*sl 0.044 + 0.012*sl t plh 0.338 0.321 + 0.008*sl 0.327 + 0.007*sl 0.334 + 0.006*sl t phl 0.272 0.254 + 0.009*sl 0.262 + 0.007*sl 0.271 + 0.006*sl d to y t r 0.087 0.061 + 0.013*sl 0.061 + 0.013*sl 0.047 + 0.014*sl t f 0.072 0.046 + 0.013*sl 0.052 + 0.011*sl 0.043 + 0.012*sl t plh 0.364 0.347 + 0.008*sl 0.354 + 0.007*sl 0.361 + 0.006*sl t phl 0.266 0.248 + 0.009*sl 0.255 + 0.007*sl 0.265 + 0.006*sl e to y t r 0.087 0.062 + 0.012*sl 0.059 + 0.013*sl 0.047 + 0.014*sl t f 0.071 0.045 + 0.013*sl 0.051 + 0.011*sl 0.043 + 0.012*sl t plh 0.390 0.374 + 0.008*sl 0.380 + 0.007*sl 0.387 + 0.006*sl t phl 0.258 0.240 + 0.009*sl 0.247 + 0.007*sl 0.257 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-106 samsung asic ao221/ao221d2/ao221d4 two 2-ands into 3-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao221d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.082 0.068 + 0.007*sl 0.069 + 0.006*sl 0.056 + 0.007*sl t f 0.067 0.055 + 0.006*sl 0.057 + 0.006*sl 0.053 + 0.006*sl t plh 0.316 0.306 + 0.005*sl 0.312 + 0.004*sl 0.323 + 0.003*sl t phl 0.245 0.234 + 0.005*sl 0.240 + 0.004*sl 0.255 + 0.003*sl b to y t r 0.084 0.071 + 0.007*sl 0.071 + 0.006*sl 0.057 + 0.007*sl t f 0.068 0.057 + 0.006*sl 0.057 + 0.006*sl 0.052 + 0.006*sl t plh 0.340 0.330 + 0.005*sl 0.335 + 0.004*sl 0.347 + 0.003*sl t phl 0.239 0.228 + 0.005*sl 0.234 + 0.004*sl 0.249 + 0.003*sl c to y t r 0.082 0.070 + 0.006*sl 0.069 + 0.006*sl 0.056 + 0.007*sl t f 0.068 0.055 + 0.006*sl 0.058 + 0.006*sl 0.053 + 0.006*sl t plh 0.364 0.355 + 0.005*sl 0.360 + 0.004*sl 0.372 + 0.003*sl t phl 0.290 0.280 + 0.005*sl 0.285 + 0.004*sl 0.301 + 0.003*sl d to y t r 0.083 0.071 + 0.006*sl 0.070 + 0.006*sl 0.058 + 0.007*sl t f 0.069 0.057 + 0.006*sl 0.058 + 0.006*sl 0.053 + 0.006*sl t plh 0.391 0.381 + 0.005*sl 0.387 + 0.004*sl 0.399 + 0.003*sl t phl 0.284 0.274 + 0.005*sl 0.279 + 0.004*sl 0.295 + 0.003*sl e to y t r 0.083 0.070 + 0.007*sl 0.071 + 0.006*sl 0.057 + 0.007*sl t f 0.067 0.055 + 0.006*sl 0.055 + 0.006*sl 0.053 + 0.006*sl t plh 0.417 0.408 + 0.005*sl 0.413 + 0.004*sl 0.425 + 0.003*sl t phl 0.273 0.263 + 0.005*sl 0.268 + 0.004*sl 0.284 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-107 STD111 ao222/ao222d2/ao222d2b/ao222d4 three 2-ands into 3-nor with 1x/2x/2x(buffered)/4x drive logic symbol cell data input load (sl) gate count ao222 ao222d2 ao222 ao222d2 abcdefabcdef 1.0 1.0 1.0 1.0 1.0 1.1 1.9 2.0 1.9 2.1 2.0 2.1 2.33 4.00 ao222d2b ao222d4 ao22d2b ao222d4 abcdefabcdef 1.0 1.0 1.0 1.0 1.0 1.1 1.0 1.0 1.0 1.0 1.0 1.1 3.33 4.67 c d a b y e f truth table abcdefy 11xxxx0 xx11xx0 xxxx110 other states 1
STD111 3-108 samsung asic ao222/ao222d2/ao222d2b/ao222d4 three 2-ands into 3-nor with 1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao222 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.451 0.285 + 0.083*sl 0.279 + 0.085*sl 0.272 + 0.085*sl t f 0.216 0.146 + 0.035*sl 0.137 + 0.037*sl 0.123 + 0.039*sl t plh 0.197 0.126 + 0.035*sl 0.123 + 0.036*sl 0.123 + 0.036*sl t phl 0.123 0.083 + 0.020*sl 0.086 + 0.019*sl 0.087 + 0.019*sl b to y t r 0.482 0.317 + 0.083*sl 0.311 + 0.084*sl 0.303 + 0.085*sl t f 0.210 0.138 + 0.036*sl 0.130 + 0.038*sl 0.120 + 0.039*sl t plh 0.215 0.144 + 0.035*sl 0.142 + 0.036*sl 0.141 + 0.036*sl t phl 0.116 0.076 + 0.020*sl 0.080 + 0.019*sl 0.081 + 0.019*sl c to y t r 0.460 0.298 + 0.081*sl 0.292 + 0.082*sl 0.287 + 0.083*sl t f 0.265 0.191 + 0.037*sl 0.185 + 0.038*sl 0.173 + 0.039*sl t plh 0.262 0.189 + 0.037*sl 0.191 + 0.036*sl 0.194 + 0.036*sl t phl 0.168 0.129 + 0.020*sl 0.131 + 0.019*sl 0.132 + 0.019*sl d to y t r 0.499 0.334 + 0.082*sl 0.329 + 0.084*sl 0.324 + 0.084*sl t f 0.261 0.186 + 0.037*sl 0.181 + 0.039*sl 0.172 + 0.039*sl t plh 0.286 0.212 + 0.037*sl 0.214 + 0.036*sl 0.216 + 0.036*sl t phl 0.163 0.124 + 0.020*sl 0.126 + 0.019*sl 0.128 + 0.019*sl e to y t r 0.462 0.299 + 0.082*sl 0.294 + 0.083*sl 0.289 + 0.083*sl t f 0.304 0.231 + 0.036*sl 0.226 + 0.038*sl 0.214 + 0.039*sl t plh 0.291 0.216 + 0.037*sl 0.219 + 0.036*sl 0.223 + 0.036*sl t phl 0.188 0.146 + 0.021*sl 0.151 + 0.020*sl 0.157 + 0.019*sl f to y t r 0.498 0.333 + 0.083*sl 0.329 + 0.084*sl 0.324 + 0.084*sl t f 0.300 0.225 + 0.037*sl 0.222 + 0.038*sl 0.215 + 0.039*sl t plh 0.313 0.239 + 0.037*sl 0.241 + 0.036*sl 0.243 + 0.036*sl t phl 0.182 0.140 + 0.021*sl 0.145 + 0.020*sl 0.151 + 0.019*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-109 STD111 ao222/ao222d2/ao222d2b/ao222d4 three 2-ands into 3-nor with 1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao222d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.362 0.280 + 0.041*sl 0.277 + 0.042*sl 0.266 + 0.042*sl t f 0.184 0.150 + 0.017*sl 0.144 + 0.018*sl 0.127 + 0.019*sl t plh 0.166 0.132 + 0.017*sl 0.129 + 0.018*sl 0.128 + 0.018*sl t phl 0.104 0.082 + 0.011*sl 0.087 + 0.009*sl 0.088 + 0.009*sl b to y t r 0.393 0.311 + 0.041*sl 0.308 + 0.042*sl 0.298 + 0.042*sl t f 0.176 0.142 + 0.017*sl 0.136 + 0.019*sl 0.123 + 0.020*sl t plh 0.185 0.150 + 0.017*sl 0.148 + 0.018*sl 0.147 + 0.018*sl t phl 0.097 0.076 + 0.011*sl 0.079 + 0.010*sl 0.082 + 0.009*sl c to y t r 0.376 0.295 + 0.041*sl 0.291 + 0.042*sl 0.283 + 0.042*sl t f 0.217 0.182 + 0.017*sl 0.176 + 0.019*sl 0.164 + 0.020*sl t plh 0.217 0.179 + 0.019*sl 0.180 + 0.018*sl 0.184 + 0.018*sl t phl 0.141 0.122 + 0.010*sl 0.123 + 0.010*sl 0.124 + 0.009*sl d to y t r 0.404 0.323 + 0.041*sl 0.320 + 0.041*sl 0.313 + 0.042*sl t f 0.211 0.174 + 0.018*sl 0.171 + 0.019*sl 0.162 + 0.020*sl t plh 0.236 0.199 + 0.018*sl 0.200 + 0.018*sl 0.202 + 0.018*sl t phl 0.135 0.115 + 0.010*sl 0.117 + 0.010*sl 0.119 + 0.009*sl e to y t r 0.375 0.294 + 0.041*sl 0.290 + 0.042*sl 0.284 + 0.042*sl t f 0.271 0.236 + 0.017*sl 0.232 + 0.018*sl 0.218 + 0.019*sl t plh 0.249 0.212 + 0.019*sl 0.213 + 0.018*sl 0.217 + 0.018*sl t phl 0.164 0.143 + 0.011*sl 0.145 + 0.010*sl 0.153 + 0.010*sl f to y t r 0.403 0.321 + 0.041*sl 0.318 + 0.042*sl 0.313 + 0.042*sl t f 0.264 0.228 + 0.018*sl 0.224 + 0.019*sl 0.216 + 0.019*sl t plh 0.269 0.233 + 0.018*sl 0.233 + 0.018*sl 0.236 + 0.018*sl t phl 0.158 0.137 + 0.011*sl 0.139 + 0.010*sl 0.147 + 0.010*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-110 samsung asic ao222/ao222d2/ao222d2b/ao222d4 three 2-ands into 3-nor with 1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao222d2b path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.089 0.062 + 0.013*sl 0.062 + 0.013*sl 0.048 + 0.014*sl t f 0.073 0.050 + 0.012*sl 0.051 + 0.011*sl 0.044 + 0.012*sl t plh 0.321 0.305 + 0.008*sl 0.311 + 0.007*sl 0.318 + 0.006*sl t phl 0.235 0.217 + 0.009*sl 0.224 + 0.007*sl 0.234 + 0.006*sl b to y t r 0.090 0.064 + 0.013*sl 0.063 + 0.013*sl 0.049 + 0.014*sl t f 0.072 0.047 + 0.013*sl 0.052 + 0.011*sl 0.044 + 0.012*sl t plh 0.345 0.328 + 0.008*sl 0.335 + 0.007*sl 0.342 + 0.006*sl t phl 0.229 0.211 + 0.009*sl 0.218 + 0.007*sl 0.228 + 0.006*sl c to y t r 0.089 0.062 + 0.013*sl 0.062 + 0.013*sl 0.048 + 0.014*sl t f 0.073 0.047 + 0.013*sl 0.053 + 0.011*sl 0.044 + 0.012*sl t plh 0.385 0.368 + 0.008*sl 0.375 + 0.007*sl 0.381 + 0.006*sl t phl 0.285 0.267 + 0.009*sl 0.274 + 0.007*sl 0.284 + 0.006*sl d to y t r 0.089 0.063 + 0.013*sl 0.063 + 0.013*sl 0.048 + 0.014*sl t f 0.073 0.048 + 0.013*sl 0.053 + 0.011*sl 0.044 + 0.012*sl t plh 0.414 0.398 + 0.008*sl 0.404 + 0.007*sl 0.411 + 0.006*sl t phl 0.279 0.261 + 0.009*sl 0.269 + 0.007*sl 0.278 + 0.006*sl e to y t r 0.089 0.063 + 0.013*sl 0.061 + 0.013*sl 0.048 + 0.014*sl t f 0.074 0.050 + 0.012*sl 0.054 + 0.011*sl 0.045 + 0.012*sl t plh 0.412 0.396 + 0.008*sl 0.402 + 0.007*sl 0.409 + 0.006*sl t phl 0.311 0.293 + 0.009*sl 0.300 + 0.007*sl 0.311 + 0.006*sl f to y t r 0.090 0.065 + 0.013*sl 0.064 + 0.013*sl 0.049 + 0.014*sl t f 0.075 0.050 + 0.012*sl 0.053 + 0.011*sl 0.046 + 0.012*sl t plh 0.440 0.423 + 0.008*sl 0.430 + 0.007*sl 0.437 + 0.006*sl t phl 0.305 0.287 + 0.009*sl 0.294 + 0.007*sl 0.305 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-111 STD111 ao222/ao222d2/ao222d2b/ao222d4 three 2-ands into 3-nor with 1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao222d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.083 0.070 + 0.007*sl 0.071 + 0.006*sl 0.057 + 0.007*sl t f 0.068 0.057 + 0.006*sl 0.057 + 0.006*sl 0.053 + 0.006*sl t plh 0.346 0.336 + 0.005*sl 0.342 + 0.004*sl 0.354 + 0.003*sl t phl 0.253 0.242 + 0.005*sl 0.248 + 0.004*sl 0.264 + 0.003*sl b to y t r 0.086 0.074 + 0.006*sl 0.072 + 0.006*sl 0.058 + 0.007*sl t f 0.068 0.055 + 0.006*sl 0.058 + 0.006*sl 0.054 + 0.006*sl t plh 0.370 0.360 + 0.005*sl 0.366 + 0.004*sl 0.378 + 0.003*sl t phl 0.247 0.236 + 0.005*sl 0.242 + 0.004*sl 0.258 + 0.003*sl c to y t r 0.084 0.072 + 0.006*sl 0.070 + 0.006*sl 0.057 + 0.007*sl t f 0.069 0.057 + 0.006*sl 0.058 + 0.006*sl 0.054 + 0.006*sl t plh 0.410 0.400 + 0.005*sl 0.406 + 0.004*sl 0.418 + 0.003*sl t phl 0.303 0.293 + 0.005*sl 0.298 + 0.004*sl 0.314 + 0.003*sl d to y t r 0.085 0.071 + 0.007*sl 0.073 + 0.006*sl 0.058 + 0.007*sl t f 0.068 0.056 + 0.006*sl 0.058 + 0.006*sl 0.055 + 0.006*sl t plh 0.440 0.430 + 0.005*sl 0.435 + 0.004*sl 0.448 + 0.003*sl t phl 0.297 0.287 + 0.005*sl 0.292 + 0.004*sl 0.308 + 0.003*sl e to y t r 0.083 0.070 + 0.007*sl 0.071 + 0.006*sl 0.057 + 0.007*sl t f 0.071 0.058 + 0.007*sl 0.061 + 0.006*sl 0.056 + 0.006*sl t plh 0.438 0.428 + 0.005*sl 0.433 + 0.004*sl 0.445 + 0.003*sl t phl 0.330 0.320 + 0.005*sl 0.326 + 0.004*sl 0.342 + 0.003*sl f to y t r 0.085 0.073 + 0.006*sl 0.072 + 0.006*sl 0.058 + 0.007*sl t f 0.070 0.057 + 0.006*sl 0.061 + 0.006*sl 0.055 + 0.006*sl t plh 0.466 0.456 + 0.005*sl 0.461 + 0.004*sl 0.473 + 0.003*sl t phl 0.324 0.314 + 0.005*sl 0.319 + 0.004*sl 0.336 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-112 samsung asic ao222a/ao222d2a/ao222d4a inverting 2-of-3 majority with 1x/2x/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao222a input load (sl) gate count ao222a ao222d2a ao222d4a ao222a ao222d2a ao222d4a abcabcabc 1.8 2.0 2.0 1.8 2.0 2.0 1.8 2.0 2.0 2.00 3.00 3.67 a b y c path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.366 0.259 + 0.053*sl 0.253 + 0.055*sl 0.242 + 0.056*sl t f 0.227 0.150 + 0.038*sl 0.146 + 0.039*sl 0.137 + 0.040*sl t plh 0.163 0.115 + 0.024*sl 0.115 + 0.024*sl 0.116 + 0.024*sl t phl 0.157 0.117 + 0.020*sl 0.119 + 0.019*sl 0.120 + 0.019*sl b to y t r 0.366 0.259 + 0.053*sl 0.253 + 0.055*sl 0.244 + 0.056*sl t f 0.237 0.162 + 0.038*sl 0.156 + 0.039*sl 0.147 + 0.040*sl t plh 0.177 0.129 + 0.024*sl 0.129 + 0.024*sl 0.129 + 0.024*sl t phl 0.174 0.135 + 0.020*sl 0.136 + 0.019*sl 0.137 + 0.019*sl c to y t r 0.340 0.234 + 0.053*sl 0.228 + 0.055*sl 0.218 + 0.056*sl t f 0.240 0.165 + 0.038*sl 0.160 + 0.039*sl 0.151 + 0.040*sl t plh 0.169 0.121 + 0.024*sl 0.120 + 0.024*sl 0.120 + 0.024*sl t phl 0.154 0.115 + 0.020*sl 0.116 + 0.019*sl 0.117 + 0.019*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table abcy 11x0 1x10 x110 00x1 0x01 x001
samsung asic 3-113 STD111 ao222a/ao222d2a/ao222d4a inverting 2-of-3 majority with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao222d2a ao222d4a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.085 0.059 + 0.013*sl 0.060 + 0.013*sl 0.045 + 0.014*sl t f 0.072 0.046 + 0.013*sl 0.052 + 0.011*sl 0.043 + 0.012*sl t plh 0.287 0.270 + 0.008*sl 0.276 + 0.007*sl 0.283 + 0.006*sl t phl 0.269 0.251 + 0.009*sl 0.259 + 0.007*sl 0.269 + 0.006*sl b to y t r 0.085 0.059 + 0.013*sl 0.059 + 0.013*sl 0.045 + 0.014*sl t f 0.072 0.046 + 0.013*sl 0.052 + 0.011*sl 0.043 + 0.012*sl t plh 0.292 0.276 + 0.008*sl 0.282 + 0.007*sl 0.288 + 0.006*sl t phl 0.286 0.268 + 0.009*sl 0.276 + 0.007*sl 0.285 + 0.006*sl c to y t r 0.083 0.057 + 0.013*sl 0.055 + 0.013*sl 0.044 + 0.014*sl t f 0.071 0.045 + 0.013*sl 0.051 + 0.012*sl 0.043 + 0.012*sl t plh 0.287 0.271 + 0.008*sl 0.277 + 0.007*sl 0.283 + 0.006*sl t phl 0.266 0.248 + 0.009*sl 0.256 + 0.007*sl 0.266 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.081 0.068 + 0.006*sl 0.068 + 0.007*sl 0.055 + 0.007*sl t f 0.069 0.056 + 0.007*sl 0.058 + 0.006*sl 0.053 + 0.006*sl t plh 0.310 0.300 + 0.005*sl 0.306 + 0.004*sl 0.318 + 0.003*sl t phl 0.289 0.278 + 0.005*sl 0.284 + 0.004*sl 0.300 + 0.003*sl b to y t r 0.082 0.069 + 0.007*sl 0.069 + 0.006*sl 0.055 + 0.007*sl t f 0.069 0.057 + 0.006*sl 0.057 + 0.006*sl 0.054 + 0.006*sl t plh 0.316 0.306 + 0.005*sl 0.311 + 0.004*sl 0.322 + 0.003*sl t phl 0.307 0.297 + 0.005*sl 0.302 + 0.004*sl 0.318 + 0.003*sl c to y t r 0.079 0.066 + 0.006*sl 0.066 + 0.007*sl 0.053 + 0.007*sl t f 0.068 0.055 + 0.007*sl 0.058 + 0.006*sl 0.054 + 0.006*sl t plh 0.311 0.301 + 0.005*sl 0.307 + 0.004*sl 0.318 + 0.003*sl t phl 0.287 0.277 + 0.005*sl 0.282 + 0.004*sl 0.298 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-114 samsung asic ao2222/ao2222d2/ao2222d4 four 2-ands into 4-nor with 1x/2x/4x drive logic symbol cell data input load (sl) gate count ao2222 ao2222 abcdefgh 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.1 3.00 ao2222d2 ao2222d2 abcdefgh 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.1 4.00 ao2222d4 ao2222d4 abcdefgh 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.1 4.67 y c d a b e f g h truth table abcdefghy 11xxxxxx0 xx11xxxx0 xxxx11xx0 xxxxxx110 other states 1
samsung asic 3-115 STD111 ao2222/ao2222d2/ao2222d4 four 2-ands into 4-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao2222 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.626 0.399 + 0.113*sl 0.395 + 0.114*sl 0.394 + 0.115*sl t f 0.245 0.172 + 0.037*sl 0.163 + 0.039*sl 0.148 + 0.041*sl t plh 0.223 0.130 + 0.046*sl 0.122 + 0.048*sl 0.122 + 0.048*sl t phl 0.133 0.093 + 0.020*sl 0.095 + 0.020*sl 0.095 + 0.020*sl b to y t r 0.668 0.442 + 0.113*sl 0.437 + 0.114*sl 0.435 + 0.114*sl t f 0.238 0.163 + 0.038*sl 0.155 + 0.040*sl 0.146 + 0.041*sl t plh 0.246 0.153 + 0.047*sl 0.147 + 0.048*sl 0.147 + 0.048*sl t phl 0.127 0.086 + 0.020*sl 0.089 + 0.020*sl 0.090 + 0.020*sl c to y t r 0.674 0.453 + 0.111*sl 0.448 + 0.112*sl 0.444 + 0.112*sl t f 0.292 0.216 + 0.038*sl 0.210 + 0.040*sl 0.198 + 0.041*sl t plh 0.330 0.230 + 0.050*sl 0.234 + 0.049*sl 0.239 + 0.048*sl t phl 0.180 0.140 + 0.020*sl 0.141 + 0.020*sl 0.143 + 0.020*sl d to y t r 0.714 0.492 + 0.111*sl 0.488 + 0.112*sl 0.485 + 0.112*sl t f 0.289 0.212 + 0.039*sl 0.206 + 0.040*sl 0.198 + 0.041*sl t plh 0.356 0.257 + 0.049*sl 0.259 + 0.049*sl 0.263 + 0.048*sl t phl 0.174 0.133 + 0.020*sl 0.135 + 0.020*sl 0.137 + 0.020*sl e to y t r 0.719 0.499 + 0.110*sl 0.494 + 0.111*sl 0.487 + 0.112*sl t f 0.350 0.274 + 0.038*sl 0.268 + 0.040*sl 0.257 + 0.041*sl t plh 0.426 0.327 + 0.050*sl 0.330 + 0.049*sl 0.335 + 0.048*sl t phl 0.205 0.162 + 0.021*sl 0.165 + 0.021*sl 0.171 + 0.020*sl f to y t r 0.753 0.533 + 0.110*sl 0.529 + 0.111*sl 0.524 + 0.111*sl t f 0.347 0.269 + 0.039*sl 0.265 + 0.040*sl 0.257 + 0.041*sl t plh 0.450 0.352 + 0.049*sl 0.354 + 0.048*sl 0.357 + 0.048*sl t phl 0.199 0.156 + 0.021*sl 0.160 + 0.021*sl 0.165 + 0.020*sl g to y t r 0.718 0.498 + 0.110*sl 0.493 + 0.111*sl 0.487 + 0.112*sl t f 0.402 0.324 + 0.039*sl 0.321 + 0.040*sl 0.311 + 0.041*sl t plh 0.456 0.356 + 0.050*sl 0.360 + 0.049*sl 0.365 + 0.048*sl t phl 0.217 0.171 + 0.023*sl 0.176 + 0.021*sl 0.186 + 0.020*sl h to y t r 0.752 0.533 + 0.110*sl 0.529 + 0.111*sl 0.523 + 0.111*sl t f 0.398 0.319 + 0.040*sl 0.316 + 0.040*sl 0.312 + 0.041*sl t plh 0.480 0.382 + 0.049*sl 0.384 + 0.048*sl 0.388 + 0.048*sl t phl 0.211 0.165 + 0.023*sl 0.170 + 0.022*sl 0.180 + 0.020*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-116 samsung asic ao2222/ao2222d2/ao2222d4 four 2-ands into 4-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao2222d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.095 0.072 + 0.012*sl 0.066 + 0.013*sl 0.054 + 0.014*sl t f 0.074 0.050 + 0.012*sl 0.052 + 0.011*sl 0.044 + 0.012*sl t plh 0.353 0.336 + 0.009*sl 0.343 + 0.007*sl 0.351 + 0.006*sl t phl 0.250 0.232 + 0.009*sl 0.240 + 0.007*sl 0.250 + 0.006*sl b to y t r 0.098 0.073 + 0.013*sl 0.072 + 0.013*sl 0.055 + 0.014*sl t f 0.074 0.051 + 0.011*sl 0.051 + 0.011*sl 0.044 + 0.012*sl t plh 0.383 0.365 + 0.009*sl 0.373 + 0.007*sl 0.381 + 0.006*sl t phl 0.244 0.226 + 0.009*sl 0.234 + 0.007*sl 0.244 + 0.006*sl c to y t r 0.096 0.070 + 0.013*sl 0.071 + 0.013*sl 0.053 + 0.014*sl t f 0.074 0.049 + 0.012*sl 0.052 + 0.011*sl 0.045 + 0.012*sl t plh 0.460 0.443 + 0.009*sl 0.450 + 0.007*sl 0.458 + 0.006*sl t phl 0.303 0.285 + 0.009*sl 0.293 + 0.007*sl 0.303 + 0.006*sl d to y t r 0.099 0.075 + 0.012*sl 0.073 + 0.013*sl 0.057 + 0.014*sl t f 0.074 0.048 + 0.013*sl 0.054 + 0.011*sl 0.045 + 0.012*sl t plh 0.492 0.474 + 0.009*sl 0.482 + 0.007*sl 0.490 + 0.006*sl t phl 0.297 0.279 + 0.009*sl 0.287 + 0.007*sl 0.297 + 0.006*sl e to y t r 0.099 0.074 + 0.012*sl 0.072 + 0.013*sl 0.057 + 0.014*sl t f 0.077 0.053 + 0.012*sl 0.055 + 0.011*sl 0.047 + 0.012*sl t plh 0.560 0.543 + 0.009*sl 0.550 + 0.007*sl 0.559 + 0.006*sl t phl 0.334 0.316 + 0.009*sl 0.323 + 0.007*sl 0.334 + 0.006*sl f to y t r 0.101 0.075 + 0.013*sl 0.076 + 0.013*sl 0.058 + 0.014*sl t f 0.076 0.052 + 0.012*sl 0.055 + 0.011*sl 0.047 + 0.012*sl t plh 0.589 0.571 + 0.009*sl 0.579 + 0.007*sl 0.588 + 0.006*sl t phl 0.328 0.310 + 0.009*sl 0.317 + 0.007*sl 0.328 + 0.006*sl g to y t r 0.099 0.075 + 0.012*sl 0.072 + 0.013*sl 0.057 + 0.014*sl t f 0.078 0.054 + 0.012*sl 0.057 + 0.011*sl 0.049 + 0.012*sl t plh 0.590 0.572 + 0.009*sl 0.580 + 0.007*sl 0.589 + 0.006*sl t phl 0.352 0.334 + 0.009*sl 0.341 + 0.007*sl 0.352 + 0.006*sl h to y t r 0.101 0.076 + 0.013*sl 0.075 + 0.013*sl 0.058 + 0.014*sl t f 0.079 0.056 + 0.012*sl 0.057 + 0.011*sl 0.049 + 0.012*sl t plh 0.620 0.602 + 0.009*sl 0.610 + 0.007*sl 0.620 + 0.006*sl t phl 0.346 0.328 + 0.009*sl 0.336 + 0.007*sl 0.347 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-117 STD111 ao2222/ao2222d2/ao2222d4 four 2-ands into 4-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao2222d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.093 0.082 + 0.006*sl 0.079 + 0.006*sl 0.066 + 0.007*sl t f 0.070 0.058 + 0.006*sl 0.060 + 0.006*sl 0.054 + 0.006*sl t plh 0.388 0.377 + 0.005*sl 0.383 + 0.004*sl 0.397 + 0.003*sl t phl 0.270 0.259 + 0.005*sl 0.265 + 0.004*sl 0.281 + 0.003*sl b to y t r 0.095 0.083 + 0.006*sl 0.082 + 0.006*sl 0.069 + 0.007*sl t f 0.070 0.057 + 0.006*sl 0.060 + 0.006*sl 0.055 + 0.006*sl t plh 0.417 0.407 + 0.005*sl 0.413 + 0.004*sl 0.427 + 0.003*sl t phl 0.263 0.253 + 0.005*sl 0.259 + 0.004*sl 0.274 + 0.003*sl c to y t r 0.095 0.083 + 0.006*sl 0.081 + 0.006*sl 0.068 + 0.007*sl t f 0.071 0.060 + 0.006*sl 0.060 + 0.006*sl 0.057 + 0.006*sl t plh 0.496 0.486 + 0.005*sl 0.492 + 0.004*sl 0.506 + 0.003*sl t phl 0.323 0.313 + 0.005*sl 0.318 + 0.004*sl 0.334 + 0.003*sl d to y t r 0.097 0.084 + 0.006*sl 0.084 + 0.006*sl 0.068 + 0.007*sl t f 0.071 0.060 + 0.006*sl 0.060 + 0.006*sl 0.056 + 0.006*sl t plh 0.528 0.517 + 0.005*sl 0.524 + 0.004*sl 0.538 + 0.003*sl t phl 0.317 0.306 + 0.005*sl 0.312 + 0.004*sl 0.328 + 0.003*sl e to y t r 0.097 0.086 + 0.006*sl 0.084 + 0.006*sl 0.070 + 0.007*sl t f 0.073 0.060 + 0.006*sl 0.063 + 0.006*sl 0.057 + 0.006*sl t plh 0.596 0.586 + 0.005*sl 0.592 + 0.004*sl 0.607 + 0.003*sl t phl 0.355 0.344 + 0.005*sl 0.350 + 0.004*sl 0.366 + 0.003*sl f to y t r 0.099 0.087 + 0.006*sl 0.086 + 0.006*sl 0.070 + 0.007*sl t f 0.073 0.061 + 0.006*sl 0.062 + 0.006*sl 0.058 + 0.006*sl t plh 0.625 0.614 + 0.005*sl 0.621 + 0.004*sl 0.636 + 0.003*sl t phl 0.349 0.338 + 0.005*sl 0.344 + 0.004*sl 0.360 + 0.003*sl g to y t r 0.096 0.084 + 0.006*sl 0.084 + 0.006*sl 0.068 + 0.007*sl t f 0.076 0.063 + 0.006*sl 0.065 + 0.006*sl 0.060 + 0.006*sl t plh 0.625 0.614 + 0.005*sl 0.621 + 0.004*sl 0.635 + 0.003*sl t phl 0.374 0.363 + 0.005*sl 0.369 + 0.004*sl 0.386 + 0.003*sl h to y t r 0.099 0.087 + 0.006*sl 0.085 + 0.006*sl 0.071 + 0.007*sl t f 0.076 0.064 + 0.006*sl 0.065 + 0.006*sl 0.061 + 0.006*sl t plh 0.657 0.646 + 0.005*sl 0.653 + 0.004*sl 0.668 + 0.003*sl t phl 0.369 0.358 + 0.005*sl 0.364 + 0.004*sl 0.381 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-118 samsung asic ao31dh/ao31/ao31d2/ao31d4 3-and into 2-nor with 0.5x/1x/2x/4x drive logic symbol cell data input load (sl) ao31dh ao31 ao31d2 ao31d4 abcdabcdabcdabcd 0.5 0.5 0.5 0.5 1.0 1.0 1.0 1.0 2.0 2.1 2.2 2.0 1.0 1.0 1.1 1.1 gate count ao31dh ao31 ao31d2 ao31d4 1.67 1.67 2.67 3.00 y d a b c truth table abcdy 111x0 xxx10 other states 1
samsung asic 3-119 STD111 ao31dh/ao31/ao31d2/ao31d4 3-and into 2-nor with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao31dh ao31 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.401 0.165 + 0.118*sl 0.149 + 0.122*sl 0.145 + 0.122*sl t f 0.322 0.134 + 0.094*sl 0.119 + 0.098*sl 0.109 + 0.099*sl t plh 0.198 0.093 + 0.052*sl 0.092 + 0.052*sl 0.092 + 0.052*sl t phl 0.178 0.087 + 0.045*sl 0.086 + 0.046*sl 0.085 + 0.046*sl b to y t r 0.430 0.193 + 0.119*sl 0.177 + 0.123*sl 0.173 + 0.123*sl t f 0.320 0.130 + 0.095*sl 0.118 + 0.098*sl 0.110 + 0.099*sl t plh 0.216 0.111 + 0.052*sl 0.110 + 0.053*sl 0.109 + 0.053*sl t phl 0.181 0.089 + 0.046*sl 0.090 + 0.046*sl 0.090 + 0.046*sl c to y t r 0.459 0.222 + 0.118*sl 0.205 + 0.123*sl 0.201 + 0.123*sl t f 0.316 0.124 + 0.096*sl 0.116 + 0.098*sl 0.109 + 0.099*sl t plh 0.231 0.125 + 0.053*sl 0.125 + 0.053*sl 0.125 + 0.053*sl t phl 0.179 0.087 + 0.046*sl 0.088 + 0.046*sl 0.089 + 0.046*sl d to y t r 0.455 0.214 + 0.120*sl 0.206 + 0.123*sl 0.201 + 0.123*sl t f 0.209 0.123 + 0.043*sl 0.113 + 0.046*sl 0.096 + 0.048*sl t plh 0.252 0.145 + 0.053*sl 0.147 + 0.053*sl 0.148 + 0.053*sl t phl 0.150 0.100 + 0.025*sl 0.100 + 0.025*sl 0.101 + 0.025*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.261 0.155 + 0.053*sl 0.145 + 0.056*sl 0.131 + 0.057*sl t f 0.215 0.128 + 0.044*sl 0.119 + 0.046*sl 0.105 + 0.047*sl t plh 0.135 0.086 + 0.024*sl 0.086 + 0.024*sl 0.085 + 0.024*sl t phl 0.125 0.080 + 0.022*sl 0.082 + 0.022*sl 0.081 + 0.022*sl b to y t r 0.289 0.181 + 0.054*sl 0.172 + 0.056*sl 0.158 + 0.058*sl t f 0.211 0.123 + 0.044*sl 0.115 + 0.046*sl 0.106 + 0.047*sl t plh 0.152 0.104 + 0.024*sl 0.103 + 0.025*sl 0.102 + 0.025*sl t phl 0.127 0.081 + 0.023*sl 0.084 + 0.022*sl 0.084 + 0.022*sl c to y t r 0.317 0.211 + 0.053*sl 0.200 + 0.056*sl 0.185 + 0.058*sl t f 0.207 0.117 + 0.045*sl 0.111 + 0.047*sl 0.104 + 0.047*sl t plh 0.166 0.117 + 0.025*sl 0.117 + 0.025*sl 0.116 + 0.025*sl t phl 0.124 0.079 + 0.023*sl 0.082 + 0.022*sl 0.082 + 0.022*sl d to y t r 0.309 0.197 + 0.056*sl 0.193 + 0.057*sl 0.186 + 0.058*sl t f 0.161 0.122 + 0.020*sl 0.117 + 0.021*sl 0.106 + 0.022*sl t plh 0.185 0.134 + 0.025*sl 0.136 + 0.025*sl 0.137 + 0.025*sl t phl 0.120 0.095 + 0.012*sl 0.097 + 0.012*sl 0.097 + 0.012*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-120 samsung asic ao31dh/ao31/ao31d2/ao31d4 3-and into 2-nor with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao31d2 ao31d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.201 0.148 + 0.027*sl 0.143 + 0.028*sl 0.126 + 0.029*sl t f 0.165 0.123 + 0.021*sl 0.118 + 0.023*sl 0.101 + 0.024*sl t plh 0.106 0.080 + 0.013*sl 0.083 + 0.012*sl 0.081 + 0.012*sl t phl 0.097 0.073 + 0.012*sl 0.078 + 0.011*sl 0.077 + 0.011*sl b to y t r 0.227 0.175 + 0.026*sl 0.168 + 0.028*sl 0.151 + 0.029*sl t f 0.161 0.119 + 0.021*sl 0.113 + 0.023*sl 0.100 + 0.024*sl t plh 0.123 0.098 + 0.012*sl 0.098 + 0.012*sl 0.097 + 0.012*sl t phl 0.099 0.074 + 0.012*sl 0.079 + 0.011*sl 0.079 + 0.011*sl c to y t r 0.255 0.204 + 0.026*sl 0.197 + 0.027*sl 0.178 + 0.029*sl t f 0.156 0.113 + 0.021*sl 0.106 + 0.023*sl 0.098 + 0.024*sl t plh 0.136 0.112 + 0.012*sl 0.112 + 0.012*sl 0.111 + 0.012*sl t phl 0.097 0.073 + 0.012*sl 0.077 + 0.011*sl 0.078 + 0.011*sl d to y t r 0.244 0.189 + 0.027*sl 0.187 + 0.028*sl 0.177 + 0.029*sl t f 0.154 0.135 + 0.010*sl 0.133 + 0.010*sl 0.117 + 0.011*sl t plh 0.159 0.134 + 0.013*sl 0.135 + 0.012*sl 0.136 + 0.012*sl t phl 0.109 0.095 + 0.007*sl 0.097 + 0.006*sl 0.098 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.074 0.060 + 0.007*sl 0.062 + 0.007*sl 0.050 + 0.007*sl t f 0.067 0.054 + 0.007*sl 0.058 + 0.006*sl 0.052 + 0.006*sl t plh 0.264 0.254 + 0.005*sl 0.259 + 0.004*sl 0.270 + 0.003*sl t phl 0.249 0.239 + 0.005*sl 0.244 + 0.004*sl 0.260 + 0.003*sl b to y t r 0.076 0.063 + 0.006*sl 0.062 + 0.007*sl 0.051 + 0.007*sl t f 0.067 0.055 + 0.006*sl 0.056 + 0.006*sl 0.054 + 0.006*sl t plh 0.287 0.277 + 0.005*sl 0.282 + 0.004*sl 0.293 + 0.003*sl t phl 0.251 0.240 + 0.005*sl 0.246 + 0.004*sl 0.262 + 0.003*sl c to y t r 0.077 0.063 + 0.007*sl 0.064 + 0.007*sl 0.052 + 0.007*sl t f 0.068 0.054 + 0.007*sl 0.058 + 0.006*sl 0.052 + 0.006*sl t plh 0.303 0.294 + 0.005*sl 0.299 + 0.004*sl 0.310 + 0.003*sl t phl 0.249 0.238 + 0.005*sl 0.244 + 0.004*sl 0.259 + 0.003*sl d to y t r 0.077 0.063 + 0.007*sl 0.064 + 0.007*sl 0.052 + 0.007*sl t f 0.066 0.054 + 0.006*sl 0.054 + 0.006*sl 0.050 + 0.006*sl t plh 0.323 0.314 + 0.005*sl 0.319 + 0.004*sl 0.330 + 0.003*sl t phl 0.242 0.232 + 0.005*sl 0.237 + 0.004*sl 0.252 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-121 STD111 ao311/ao311d2/ao311d4 3-and into 3-nor with 1x/2x/4x drive logic symbol cell data input load (sl) ao311 ao311d2 ao311d4 abcdeabcdeabcde 1.0 1.0 1.0 0.9 0.9 1.0 1.0 1.0 0.9 1.0 1.0 1.0 1.0 0.9 1.0 gate count ao311 ao311d2 ao311d4 2.00 3.00 3.33 y d e a b c truth table abcdey 111xx0 xxx1x0 xxxx10 other states 1
STD111 3-122 samsung asic ao311/ao311d2/ao311d4 3-and into 3-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao311 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.406 0.245 + 0.081*sl 0.235 + 0.083*sl 0.227 + 0.084*sl t f 0.241 0.142 + 0.050*sl 0.132 + 0.052*sl 0.121 + 0.053*sl t plh 0.170 0.100 + 0.035*sl 0.096 + 0.036*sl 0.096 + 0.036*sl t phl 0.144 0.095 + 0.025*sl 0.094 + 0.025*sl 0.094 + 0.025*sl b to y t r 0.440 0.278 + 0.081*sl 0.268 + 0.084*sl 0.260 + 0.084*sl t f 0.239 0.138 + 0.051*sl 0.131 + 0.053*sl 0.122 + 0.053*sl t plh 0.190 0.120 + 0.035*sl 0.117 + 0.036*sl 0.117 + 0.036*sl t phl 0.145 0.095 + 0.025*sl 0.096 + 0.025*sl 0.096 + 0.025*sl c to y t r 0.473 0.314 + 0.080*sl 0.302 + 0.083*sl 0.293 + 0.084*sl t f 0.235 0.132 + 0.051*sl 0.127 + 0.053*sl 0.121 + 0.053*sl t plh 0.207 0.136 + 0.035*sl 0.135 + 0.036*sl 0.134 + 0.036*sl t phl 0.142 0.092 + 0.025*sl 0.093 + 0.025*sl 0.094 + 0.025*sl d to y t r 0.480 0.318 + 0.081*sl 0.312 + 0.083*sl 0.305 + 0.083*sl t f 0.207 0.148 + 0.030*sl 0.144 + 0.031*sl 0.134 + 0.032*sl t plh 0.264 0.191 + 0.037*sl 0.193 + 0.036*sl 0.195 + 0.036*sl t phl 0.161 0.127 + 0.017*sl 0.128 + 0.017*sl 0.129 + 0.017*sl e to y t r 0.478 0.316 + 0.081*sl 0.310 + 0.083*sl 0.305 + 0.083*sl t f 0.233 0.174 + 0.030*sl 0.171 + 0.031*sl 0.159 + 0.032*sl t plh 0.270 0.197 + 0.037*sl 0.199 + 0.036*sl 0.201 + 0.036*sl t phl 0.171 0.136 + 0.017*sl 0.138 + 0.017*sl 0.140 + 0.017*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-123 STD111 ao311/ao311d2/ao311d4 3-and into 3-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao311d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.085 0.059 + 0.013*sl 0.058 + 0.013*sl 0.046 + 0.014*sl t f 0.072 0.047 + 0.013*sl 0.052 + 0.011*sl 0.044 + 0.012*sl t plh 0.284 0.268 + 0.008*sl 0.274 + 0.007*sl 0.281 + 0.006*sl t phl 0.250 0.232 + 0.009*sl 0.239 + 0.007*sl 0.249 + 0.006*sl b to y t r 0.086 0.061 + 0.012*sl 0.058 + 0.013*sl 0.047 + 0.014*sl t f 0.072 0.048 + 0.012*sl 0.051 + 0.011*sl 0.044 + 0.012*sl t plh 0.310 0.294 + 0.008*sl 0.300 + 0.007*sl 0.307 + 0.006*sl t phl 0.251 0.233 + 0.009*sl 0.241 + 0.007*sl 0.251 + 0.006*sl c to y t r 0.088 0.064 + 0.012*sl 0.060 + 0.013*sl 0.048 + 0.014*sl t f 0.072 0.047 + 0.013*sl 0.052 + 0.011*sl 0.044 + 0.012*sl t plh 0.331 0.315 + 0.008*sl 0.321 + 0.007*sl 0.328 + 0.006*sl t phl 0.248 0.230 + 0.009*sl 0.238 + 0.007*sl 0.248 + 0.006*sl d to y t r 0.089 0.063 + 0.013*sl 0.062 + 0.013*sl 0.048 + 0.014*sl t f 0.071 0.047 + 0.012*sl 0.049 + 0.011*sl 0.042 + 0.012*sl t plh 0.386 0.370 + 0.008*sl 0.376 + 0.007*sl 0.383 + 0.006*sl t phl 0.270 0.252 + 0.009*sl 0.259 + 0.007*sl 0.269 + 0.006*sl e to y t r 0.089 0.064 + 0.013*sl 0.061 + 0.013*sl 0.048 + 0.014*sl t f 0.071 0.045 + 0.013*sl 0.050 + 0.011*sl 0.042 + 0.012*sl t plh 0.394 0.377 + 0.008*sl 0.384 + 0.007*sl 0.391 + 0.006*sl t phl 0.279 0.261 + 0.009*sl 0.268 + 0.007*sl 0.278 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-124 samsung asic ao311/ao311d2/ao311d4 3-and into 3-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao311d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.082 0.069 + 0.006*sl 0.069 + 0.006*sl 0.056 + 0.007*sl t f 0.069 0.056 + 0.006*sl 0.058 + 0.006*sl 0.055 + 0.006*sl t plh 0.313 0.303 + 0.005*sl 0.308 + 0.004*sl 0.320 + 0.003*sl t phl 0.272 0.261 + 0.005*sl 0.267 + 0.004*sl 0.283 + 0.003*sl b to y t r 0.084 0.071 + 0.007*sl 0.071 + 0.006*sl 0.057 + 0.007*sl t f 0.068 0.055 + 0.006*sl 0.058 + 0.006*sl 0.055 + 0.006*sl t plh 0.340 0.330 + 0.005*sl 0.335 + 0.004*sl 0.348 + 0.003*sl t phl 0.274 0.263 + 0.005*sl 0.269 + 0.004*sl 0.285 + 0.003*sl c to y t r 0.085 0.072 + 0.007*sl 0.073 + 0.006*sl 0.058 + 0.007*sl t f 0.069 0.056 + 0.006*sl 0.058 + 0.006*sl 0.055 + 0.006*sl t plh 0.361 0.351 + 0.005*sl 0.357 + 0.004*sl 0.369 + 0.003*sl t phl 0.271 0.261 + 0.005*sl 0.267 + 0.004*sl 0.282 + 0.003*sl d to y t r 0.085 0.072 + 0.006*sl 0.072 + 0.006*sl 0.058 + 0.007*sl t f 0.066 0.052 + 0.007*sl 0.056 + 0.006*sl 0.051 + 0.006*sl t plh 0.417 0.407 + 0.005*sl 0.413 + 0.004*sl 0.425 + 0.003*sl t phl 0.287 0.276 + 0.005*sl 0.282 + 0.004*sl 0.297 + 0.003*sl e to y t r 0.085 0.073 + 0.006*sl 0.072 + 0.006*sl 0.058 + 0.007*sl t f 0.068 0.055 + 0.006*sl 0.057 + 0.006*sl 0.051 + 0.006*sl t plh 0.425 0.415 + 0.005*sl 0.421 + 0.004*sl 0.433 + 0.003*sl t phl 0.302 0.291 + 0.005*sl 0.297 + 0.004*sl 0.312 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-125 STD111 ao3111/ao3111d2 3-and into 4-nor with 1x/2x drive logic symbol cell data input load (sl) gate count ao3111 ao3111d2 ao3111 ao3111 d2 abcdefabcdef 0.9 1.0 1.0 0.8 0.9 0.9 1.0 1.0 1.0 0.8 0.9 0.9 2.33 3.00 y d e a b c f truth table abcdefy 111xxx0 xxx1xx0 xxxx1x0 xxxxx10 other states 1
STD111 3-126 samsung asic ao3111/ao3111d2 3-and into 4-nor with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao3111 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.551 0.335 + 0.108*sl 0.326 + 0.111*sl 0.324 + 0.111*sl t f 0.259 0.148 + 0.055*sl 0.141 + 0.057*sl 0.129 + 0.058*sl t plh 0.193 0.103 + 0.045*sl 0.094 + 0.047*sl 0.095 + 0.047*sl t phl 0.155 0.101 + 0.027*sl 0.101 + 0.027*sl 0.100 + 0.027*sl b to y t r 0.595 0.377 + 0.109*sl 0.368 + 0.111*sl 0.366 + 0.111*sl t f 0.257 0.146 + 0.056*sl 0.138 + 0.058*sl 0.131 + 0.058*sl t plh 0.217 0.125 + 0.046*sl 0.121 + 0.047*sl 0.121 + 0.047*sl t phl 0.157 0.103 + 0.027*sl 0.103 + 0.027*sl 0.103 + 0.027*sl c to y t r 0.637 0.422 + 0.108*sl 0.410 + 0.111*sl 0.408 + 0.111*sl t f 0.254 0.141 + 0.056*sl 0.136 + 0.058*sl 0.130 + 0.058*sl t plh 0.239 0.146 + 0.047*sl 0.144 + 0.047*sl 0.144 + 0.047*sl t phl 0.155 0.100 + 0.027*sl 0.101 + 0.027*sl 0.102 + 0.027*sl d to y t r 0.663 0.447 + 0.108*sl 0.442 + 0.109*sl 0.436 + 0.110*sl t f 0.244 0.170 + 0.037*sl 0.166 + 0.038*sl 0.157 + 0.039*sl t plh 0.331 0.234 + 0.048*sl 0.237 + 0.048*sl 0.240 + 0.047*sl t phl 0.191 0.149 + 0.021*sl 0.150 + 0.020*sl 0.151 + 0.020*sl e to y t r 0.664 0.449 + 0.107*sl 0.442 + 0.109*sl 0.436 + 0.110*sl t f 0.274 0.200 + 0.037*sl 0.196 + 0.038*sl 0.187 + 0.039*sl t plh 0.358 0.262 + 0.048*sl 0.264 + 0.048*sl 0.268 + 0.047*sl t phl 0.206 0.163 + 0.021*sl 0.165 + 0.021*sl 0.168 + 0.020*sl f to y t r 0.663 0.448 + 0.108*sl 0.442 + 0.109*sl 0.436 + 0.110*sl t f 0.308 0.234 + 0.037*sl 0.230 + 0.038*sl 0.220 + 0.039*sl t plh 0.369 0.272 + 0.048*sl 0.275 + 0.048*sl 0.278 + 0.047*sl t phl 0.216 0.172 + 0.022*sl 0.175 + 0.021*sl 0.180 + 0.021*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-127 STD111 ao3111/ao3111d2 3-and into 4-nor with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao3111d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.091 0.067 + 0.012*sl 0.063 + 0.013*sl 0.051 + 0.014*sl t f 0.075 0.051 + 0.012*sl 0.051 + 0.012*sl 0.044 + 0.012*sl t plh 0.311 0.294 + 0.008*sl 0.301 + 0.007*sl 0.308 + 0.006*sl t phl 0.261 0.243 + 0.009*sl 0.251 + 0.007*sl 0.261 + 0.006*sl b to y t r 0.094 0.071 + 0.012*sl 0.065 + 0.013*sl 0.053 + 0.014*sl t f 0.074 0.050 + 0.012*sl 0.053 + 0.012*sl 0.045 + 0.012*sl t plh 0.342 0.325 + 0.009*sl 0.332 + 0.007*sl 0.340 + 0.006*sl t phl 0.263 0.245 + 0.009*sl 0.252 + 0.007*sl 0.263 + 0.006*sl c to y t r 0.096 0.071 + 0.013*sl 0.070 + 0.013*sl 0.054 + 0.014*sl t f 0.074 0.051 + 0.012*sl 0.051 + 0.012*sl 0.044 + 0.012*sl t plh 0.369 0.352 + 0.009*sl 0.359 + 0.007*sl 0.367 + 0.006*sl t phl 0.260 0.242 + 0.009*sl 0.250 + 0.007*sl 0.260 + 0.006*sl d to y t r 0.096 0.071 + 0.013*sl 0.070 + 0.013*sl 0.055 + 0.014*sl t f 0.072 0.047 + 0.012*sl 0.050 + 0.012*sl 0.043 + 0.012*sl t plh 0.459 0.441 + 0.009*sl 0.449 + 0.007*sl 0.457 + 0.006*sl t phl 0.302 0.284 + 0.009*sl 0.292 + 0.007*sl 0.301 + 0.006*sl e to y t r 0.097 0.072 + 0.013*sl 0.071 + 0.013*sl 0.055 + 0.014*sl t f 0.073 0.047 + 0.013*sl 0.052 + 0.012*sl 0.044 + 0.012*sl t plh 0.487 0.469 + 0.009*sl 0.477 + 0.007*sl 0.485 + 0.006*sl t phl 0.321 0.303 + 0.009*sl 0.311 + 0.007*sl 0.321 + 0.006*sl f to y t r 0.097 0.072 + 0.012*sl 0.069 + 0.013*sl 0.055 + 0.014*sl t f 0.074 0.049 + 0.013*sl 0.053 + 0.012*sl 0.045 + 0.012*sl t plh 0.498 0.480 + 0.009*sl 0.488 + 0.007*sl 0.496 + 0.006*sl t phl 0.335 0.317 + 0.009*sl 0.324 + 0.007*sl 0.334 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-128 samsung asic ao32/ao32d2/ao32d4 3-and and 2-and into 2-nor with 1x/2x/4x drive logic symbol cell data input load (sl) ao32 ao32d2 ao32d4 abcdeabcdeabcde 0.9 1.0 1.0 0.9 1.0 1.0 1.0 1.0 0.9 1.0 1.0 1.0 1.0 0.9 1.0 gate count ao32 ao32d2 ao32d4 2.00 3.00 3.67 y a b c d e truth table abcdey 111xx0 xxx110 other states 1
samsung asic 3-129 STD111 ao32/ao32d2/ao32d4 3-and and 2-and into 2-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao32 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.335 0.199 + 0.068*sl 0.192 + 0.070*sl 0.181 + 0.071*sl t f 0.242 0.156 + 0.043*sl 0.146 + 0.046*sl 0.131 + 0.047*sl t plh 0.173 0.113 + 0.030*sl 0.112 + 0.030*sl 0.112 + 0.030*sl t phl 0.127 0.083 + 0.022*sl 0.085 + 0.022*sl 0.084 + 0.022*sl b to y t r 0.366 0.231 + 0.068*sl 0.223 + 0.070*sl 0.213 + 0.071*sl t f 0.238 0.150 + 0.044*sl 0.140 + 0.046*sl 0.132 + 0.047*sl t plh 0.193 0.133 + 0.030*sl 0.132 + 0.030*sl 0.132 + 0.030*sl t phl 0.130 0.084 + 0.023*sl 0.087 + 0.022*sl 0.088 + 0.022*sl c to y t r 0.399 0.264 + 0.068*sl 0.256 + 0.070*sl 0.245 + 0.071*sl t f 0.233 0.144 + 0.045*sl 0.137 + 0.047*sl 0.130 + 0.047*sl t plh 0.210 0.150 + 0.030*sl 0.150 + 0.030*sl 0.150 + 0.030*sl t phl 0.127 0.082 + 0.023*sl 0.085 + 0.022*sl 0.086 + 0.022*sl d to y t r 0.367 0.230 + 0.069*sl 0.225 + 0.070*sl 0.219 + 0.071*sl t f 0.215 0.155 + 0.030*sl 0.148 + 0.032*sl 0.137 + 0.033*sl t plh 0.227 0.164 + 0.031*sl 0.166 + 0.031*sl 0.169 + 0.030*sl t phl 0.142 0.109 + 0.016*sl 0.110 + 0.016*sl 0.111 + 0.016*sl e to y t r 0.398 0.260 + 0.069*sl 0.255 + 0.070*sl 0.250 + 0.071*sl t f 0.208 0.146 + 0.031*sl 0.142 + 0.032*sl 0.134 + 0.033*sl t plh 0.247 0.185 + 0.031*sl 0.187 + 0.031*sl 0.188 + 0.030*sl t phl 0.136 0.102 + 0.017*sl 0.104 + 0.016*sl 0.105 + 0.016*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-130 samsung asic ao32/ao32d2/ao32d4 3-and and 2-and into 2-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao32d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.082 0.056 + 0.013*sl 0.055 + 0.013*sl 0.043 + 0.014*sl t f 0.074 0.050 + 0.012*sl 0.050 + 0.012*sl 0.043 + 0.012*sl t plh 0.284 0.267 + 0.008*sl 0.273 + 0.007*sl 0.279 + 0.006*sl t phl 0.237 0.219 + 0.009*sl 0.226 + 0.007*sl 0.236 + 0.006*sl b to y t r 0.083 0.057 + 0.013*sl 0.056 + 0.013*sl 0.044 + 0.014*sl t f 0.074 0.050 + 0.012*sl 0.051 + 0.012*sl 0.044 + 0.012*sl t plh 0.309 0.293 + 0.008*sl 0.299 + 0.007*sl 0.305 + 0.006*sl t phl 0.239 0.221 + 0.009*sl 0.228 + 0.007*sl 0.238 + 0.006*sl c to y t r 0.084 0.058 + 0.013*sl 0.057 + 0.013*sl 0.045 + 0.014*sl t f 0.073 0.048 + 0.012*sl 0.051 + 0.012*sl 0.044 + 0.012*sl t plh 0.331 0.314 + 0.008*sl 0.320 + 0.007*sl 0.327 + 0.006*sl t phl 0.237 0.219 + 0.009*sl 0.226 + 0.007*sl 0.236 + 0.006*sl d to y t r 0.083 0.057 + 0.013*sl 0.056 + 0.013*sl 0.044 + 0.014*sl t f 0.072 0.046 + 0.013*sl 0.051 + 0.011*sl 0.042 + 0.012*sl t plh 0.340 0.324 + 0.008*sl 0.330 + 0.007*sl 0.336 + 0.006*sl t phl 0.253 0.235 + 0.009*sl 0.243 + 0.007*sl 0.253 + 0.006*sl e to y t r 0.084 0.058 + 0.013*sl 0.056 + 0.013*sl 0.045 + 0.014*sl t f 0.072 0.046 + 0.013*sl 0.051 + 0.012*sl 0.043 + 0.012*sl t plh 0.366 0.349 + 0.008*sl 0.355 + 0.007*sl 0.362 + 0.006*sl t phl 0.247 0.229 + 0.009*sl 0.236 + 0.007*sl 0.246 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-131 STD111 ao32/ao32d2/ao32d4 3-and and 2-and into 2-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao32d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.078 0.065 + 0.006*sl 0.064 + 0.007*sl 0.053 + 0.007*sl t f 0.069 0.057 + 0.006*sl 0.058 + 0.006*sl 0.054 + 0.006*sl t plh 0.308 0.298 + 0.005*sl 0.303 + 0.004*sl 0.314 + 0.003*sl t phl 0.257 0.246 + 0.005*sl 0.252 + 0.004*sl 0.268 + 0.003*sl b to y t r 0.079 0.066 + 0.006*sl 0.066 + 0.007*sl 0.053 + 0.007*sl t f 0.069 0.056 + 0.007*sl 0.059 + 0.006*sl 0.053 + 0.006*sl t plh 0.333 0.323 + 0.005*sl 0.328 + 0.004*sl 0.340 + 0.003*sl t phl 0.259 0.248 + 0.005*sl 0.254 + 0.004*sl 0.270 + 0.003*sl c to y t r 0.080 0.067 + 0.007*sl 0.068 + 0.006*sl 0.054 + 0.007*sl t f 0.069 0.056 + 0.006*sl 0.058 + 0.006*sl 0.054 + 0.006*sl t plh 0.355 0.345 + 0.005*sl 0.351 + 0.004*sl 0.362 + 0.003*sl t phl 0.257 0.246 + 0.005*sl 0.252 + 0.004*sl 0.268 + 0.003*sl d to y t r 0.080 0.068 + 0.006*sl 0.065 + 0.007*sl 0.054 + 0.007*sl t f 0.067 0.056 + 0.006*sl 0.056 + 0.006*sl 0.053 + 0.006*sl t plh 0.365 0.356 + 0.005*sl 0.361 + 0.004*sl 0.372 + 0.003*sl t phl 0.270 0.260 + 0.005*sl 0.265 + 0.004*sl 0.281 + 0.003*sl e to y t r 0.080 0.068 + 0.006*sl 0.067 + 0.006*sl 0.054 + 0.007*sl t f 0.067 0.055 + 0.006*sl 0.056 + 0.006*sl 0.051 + 0.006*sl t plh 0.391 0.381 + 0.005*sl 0.386 + 0.004*sl 0.398 + 0.003*sl t phl 0.264 0.253 + 0.005*sl 0.259 + 0.004*sl 0.274 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-132 samsung asic ao321/ao321d2/ao321d4 3-and and 2-and into 3-nor with 1x/2x/4x drive logic symbol cell data input load (sl) ao321 ao321d2 ao321d4 abcdefabcdefabcdef 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.1 1.0 1.0 1.0 1.0 1.0 1.1 1.0 1.0 1.0 gate count ao321 ao321d2 ao321d4 2.33 3.33 4.00 a b c d e y f truth table abcdefy 111xxx0 xxx11x0 xxxxx10 other states 1
samsung asic 3-133 STD111 ao321/ao321d2/ao321d4 3-and and 2-and into 3-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao321 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.458 0.294 + 0.082*sl 0.287 + 0.084*sl 0.281 + 0.085*sl t f 0.262 0.171 + 0.046*sl 0.163 + 0.048*sl 0.150 + 0.049*sl t plh 0.190 0.120 + 0.035*sl 0.117 + 0.036*sl 0.117 + 0.036*sl t phl 0.144 0.098 + 0.023*sl 0.099 + 0.023*sl 0.099 + 0.023*sl b to y t r 0.496 0.331 + 0.082*sl 0.324 + 0.084*sl 0.318 + 0.085*sl t f 0.259 0.166 + 0.047*sl 0.160 + 0.048*sl 0.151 + 0.049*sl t plh 0.213 0.142 + 0.035*sl 0.140 + 0.036*sl 0.140 + 0.036*sl t phl 0.146 0.100 + 0.023*sl 0.101 + 0.023*sl 0.102 + 0.023*sl c to y t r 0.536 0.371 + 0.082*sl 0.364 + 0.084*sl 0.356 + 0.085*sl t f 0.255 0.160 + 0.047*sl 0.155 + 0.049*sl 0.149 + 0.049*sl t plh 0.234 0.162 + 0.036*sl 0.162 + 0.036*sl 0.162 + 0.036*sl t phl 0.144 0.097 + 0.023*sl 0.099 + 0.023*sl 0.100 + 0.023*sl d to y t r 0.513 0.350 + 0.081*sl 0.345 + 0.082*sl 0.339 + 0.083*sl t f 0.267 0.193 + 0.037*sl 0.188 + 0.038*sl 0.179 + 0.039*sl t plh 0.286 0.213 + 0.037*sl 0.215 + 0.036*sl 0.219 + 0.036*sl t phl 0.184 0.145 + 0.019*sl 0.146 + 0.019*sl 0.148 + 0.019*sl e to y t r 0.550 0.386 + 0.082*sl 0.381 + 0.084*sl 0.376 + 0.084*sl t f 0.263 0.188 + 0.038*sl 0.185 + 0.039*sl 0.179 + 0.039*sl t plh 0.310 0.236 + 0.037*sl 0.238 + 0.036*sl 0.241 + 0.036*sl t phl 0.178 0.139 + 0.019*sl 0.140 + 0.019*sl 0.142 + 0.019*sl f to y t r 0.550 0.385 + 0.083*sl 0.381 + 0.084*sl 0.376 + 0.084*sl t f 0.255 0.207 + 0.024*sl 0.202 + 0.026*sl 0.192 + 0.027*sl t plh 0.333 0.259 + 0.037*sl 0.261 + 0.037*sl 0.264 + 0.036*sl t phl 0.162 0.132 + 0.015*sl 0.134 + 0.015*sl 0.138 + 0.014*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-134 samsung asic ao321/ao321d2/ao321d4 3-and and 2-and into 3-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao321d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.088 0.062 + 0.013*sl 0.062 + 0.013*sl 0.048 + 0.014*sl t f 0.074 0.049 + 0.012*sl 0.053 + 0.011*sl 0.044 + 0.012*sl t plh 0.315 0.298 + 0.008*sl 0.305 + 0.007*sl 0.312 + 0.006*sl t phl 0.259 0.241 + 0.009*sl 0.249 + 0.007*sl 0.259 + 0.006*sl b to y t r 0.090 0.064 + 0.013*sl 0.063 + 0.013*sl 0.049 + 0.014*sl t f 0.075 0.051 + 0.012*sl 0.052 + 0.011*sl 0.045 + 0.012*sl t plh 0.343 0.327 + 0.008*sl 0.333 + 0.007*sl 0.341 + 0.006*sl t phl 0.261 0.243 + 0.009*sl 0.251 + 0.007*sl 0.261 + 0.006*sl c to y t r 0.092 0.067 + 0.012*sl 0.065 + 0.013*sl 0.051 + 0.014*sl t f 0.074 0.049 + 0.012*sl 0.053 + 0.011*sl 0.044 + 0.012*sl t plh 0.368 0.352 + 0.008*sl 0.358 + 0.007*sl 0.365 + 0.006*sl t phl 0.259 0.241 + 0.009*sl 0.249 + 0.007*sl 0.259 + 0.006*sl d to y t r 0.091 0.065 + 0.013*sl 0.064 + 0.013*sl 0.049 + 0.014*sl t f 0.072 0.047 + 0.012*sl 0.051 + 0.011*sl 0.044 + 0.012*sl t plh 0.418 0.401 + 0.008*sl 0.408 + 0.007*sl 0.415 + 0.006*sl t phl 0.304 0.286 + 0.009*sl 0.293 + 0.007*sl 0.303 + 0.006*sl e to y t r 0.093 0.067 + 0.013*sl 0.067 + 0.013*sl 0.051 + 0.014*sl t f 0.072 0.047 + 0.013*sl 0.052 + 0.011*sl 0.044 + 0.012*sl t plh 0.446 0.429 + 0.008*sl 0.436 + 0.007*sl 0.443 + 0.006*sl t phl 0.298 0.280 + 0.009*sl 0.288 + 0.007*sl 0.297 + 0.006*sl f to y t r 0.093 0.066 + 0.013*sl 0.067 + 0.013*sl 0.050 + 0.014*sl t f 0.072 0.047 + 0.013*sl 0.052 + 0.011*sl 0.043 + 0.012*sl t plh 0.469 0.452 + 0.008*sl 0.459 + 0.007*sl 0.466 + 0.006*sl t phl 0.280 0.262 + 0.009*sl 0.270 + 0.007*sl 0.280 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-135 STD111 ao321/ao321d2/ao321d4 3-and and 2-and into 3-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao321d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.085 0.073 + 0.006*sl 0.072 + 0.006*sl 0.059 + 0.007*sl t f 0.070 0.058 + 0.006*sl 0.060 + 0.006*sl 0.055 + 0.006*sl t plh 0.342 0.332 + 0.005*sl 0.338 + 0.004*sl 0.350 + 0.003*sl t phl 0.280 0.270 + 0.005*sl 0.276 + 0.004*sl 0.291 + 0.003*sl b to y t r 0.088 0.076 + 0.006*sl 0.074 + 0.006*sl 0.060 + 0.007*sl t f 0.070 0.058 + 0.006*sl 0.060 + 0.006*sl 0.055 + 0.006*sl t plh 0.371 0.361 + 0.005*sl 0.366 + 0.004*sl 0.379 + 0.003*sl t phl 0.282 0.272 + 0.005*sl 0.277 + 0.004*sl 0.293 + 0.003*sl c to y t r 0.089 0.077 + 0.006*sl 0.075 + 0.006*sl 0.062 + 0.007*sl t f 0.070 0.058 + 0.006*sl 0.060 + 0.006*sl 0.056 + 0.006*sl t plh 0.396 0.386 + 0.005*sl 0.392 + 0.004*sl 0.404 + 0.003*sl t phl 0.280 0.269 + 0.005*sl 0.275 + 0.004*sl 0.291 + 0.003*sl d to y t r 0.087 0.076 + 0.006*sl 0.073 + 0.006*sl 0.060 + 0.007*sl t f 0.069 0.056 + 0.006*sl 0.059 + 0.006*sl 0.054 + 0.006*sl t plh 0.446 0.435 + 0.005*sl 0.441 + 0.004*sl 0.454 + 0.003*sl t phl 0.323 0.312 + 0.005*sl 0.318 + 0.004*sl 0.333 + 0.003*sl e to y t r 0.089 0.076 + 0.006*sl 0.075 + 0.006*sl 0.062 + 0.007*sl t f 0.069 0.055 + 0.007*sl 0.059 + 0.006*sl 0.055 + 0.006*sl t plh 0.474 0.463 + 0.005*sl 0.469 + 0.004*sl 0.482 + 0.003*sl t phl 0.317 0.306 + 0.005*sl 0.312 + 0.004*sl 0.327 + 0.003*sl f to y t r 0.090 0.078 + 0.006*sl 0.076 + 0.006*sl 0.062 + 0.007*sl t f 0.068 0.054 + 0.007*sl 0.059 + 0.006*sl 0.053 + 0.006*sl t plh 0.496 0.486 + 0.005*sl 0.492 + 0.004*sl 0.505 + 0.003*sl t phl 0.297 0.286 + 0.005*sl 0.292 + 0.004*sl 0.307 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-136 samsung asic ao322/ao322d2/ao322d4 3-and and two 2-ands into 3-nor with 1x/2x/4x drive logic symbol cell data input load (sl) gate count ao322 ao322 abcdefg 1.0 1.0 1.1 1.1 1.1 1.1 1.1 2.67 ao322d2 ao322d2 abcdefg 1.0 1.1 1.0 1.1 1.1 1.1 1.1 4.00 ao322d4 ao322d4 abcdefg 1.0 1.0 1.1 1.1 1.1 1.1 1.1 4.33 a b c d e y f g truth table abcdefgy 111xxxx0 xxx11xx0 xxxxx110 other states 1
samsung asic 3-137 STD111 ao322/ao322d2/ao322d4 3-and and two 2-ands into 3-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao322 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.512 0.343 + 0.084*sl 0.338 + 0.086*sl 0.334 + 0.086*sl t f 0.294 0.207 + 0.044*sl 0.199 + 0.046*sl 0.185 + 0.047*sl t plh 0.226 0.153 + 0.036*sl 0.152 + 0.037*sl 0.153 + 0.037*sl t phl 0.149 0.105 + 0.022*sl 0.105 + 0.022*sl 0.106 + 0.022*sl b to y t r 0.551 0.382 + 0.085*sl 0.377 + 0.086*sl 0.374 + 0.086*sl t f 0.291 0.202 + 0.045*sl 0.195 + 0.046*sl 0.186 + 0.047*sl t plh 0.250 0.177 + 0.036*sl 0.177 + 0.037*sl 0.177 + 0.037*sl t phl 0.151 0.107 + 0.022*sl 0.108 + 0.022*sl 0.109 + 0.022*sl c to y t r 0.593 0.424 + 0.085*sl 0.418 + 0.086*sl 0.415 + 0.087*sl t f 0.286 0.195 + 0.046*sl 0.190 + 0.047*sl 0.185 + 0.047*sl t plh 0.274 0.200 + 0.037*sl 0.200 + 0.037*sl 0.201 + 0.037*sl t phl 0.149 0.104 + 0.023*sl 0.105 + 0.022*sl 0.107 + 0.022*sl d to y t r 0.570 0.402 + 0.084*sl 0.399 + 0.085*sl 0.394 + 0.085*sl t f 0.275 0.215 + 0.030*sl 0.209 + 0.032*sl 0.196 + 0.033*sl t plh 0.324 0.249 + 0.038*sl 0.251 + 0.037*sl 0.254 + 0.037*sl t phl 0.163 0.130 + 0.017*sl 0.131 + 0.016*sl 0.133 + 0.016*sl e to y t r 0.609 0.440 + 0.085*sl 0.437 + 0.085*sl 0.433 + 0.086*sl t f 0.269 0.207 + 0.031*sl 0.201 + 0.032*sl 0.195 + 0.033*sl t plh 0.350 0.275 + 0.038*sl 0.276 + 0.037*sl 0.278 + 0.037*sl t phl 0.157 0.124 + 0.017*sl 0.125 + 0.016*sl 0.127 + 0.016*sl f to y t r 0.571 0.402 + 0.084*sl 0.399 + 0.085*sl 0.394 + 0.086*sl t f 0.331 0.270 + 0.031*sl 0.264 + 0.032*sl 0.254 + 0.033*sl t plh 0.362 0.286 + 0.038*sl 0.288 + 0.037*sl 0.292 + 0.037*sl t phl 0.184 0.148 + 0.018*sl 0.151 + 0.017*sl 0.156 + 0.016*sl g to y t r 0.610 0.440 + 0.085*sl 0.438 + 0.085*sl 0.434 + 0.086*sl t f 0.325 0.262 + 0.032*sl 0.258 + 0.033*sl 0.252 + 0.033*sl t plh 0.387 0.312 + 0.038*sl 0.314 + 0.037*sl 0.316 + 0.037*sl t phl 0.178 0.143 + 0.018*sl 0.146 + 0.017*sl 0.151 + 0.016*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-138 samsung asic ao322/ao322d2/ao322d4 3-and and two 2-ands into 3-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao322d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.090 0.066 + 0.012*sl 0.061 + 0.013*sl 0.049 + 0.014*sl t f 0.076 0.053 + 0.012*sl 0.053 + 0.011*sl 0.045 + 0.012*sl t plh 0.352 0.335 + 0.008*sl 0.342 + 0.007*sl 0.350 + 0.006*sl t phl 0.268 0.250 + 0.009*sl 0.258 + 0.007*sl 0.268 + 0.006*sl b to y t r 0.093 0.067 + 0.013*sl 0.067 + 0.013*sl 0.050 + 0.014*sl t f 0.076 0.053 + 0.011*sl 0.053 + 0.012*sl 0.045 + 0.012*sl t plh 0.382 0.365 + 0.008*sl 0.372 + 0.007*sl 0.380 + 0.006*sl t phl 0.270 0.252 + 0.009*sl 0.260 + 0.007*sl 0.270 + 0.006*sl c to y t r 0.095 0.071 + 0.012*sl 0.067 + 0.013*sl 0.053 + 0.014*sl t f 0.075 0.050 + 0.013*sl 0.054 + 0.011*sl 0.045 + 0.012*sl t plh 0.411 0.394 + 0.009*sl 0.401 + 0.007*sl 0.408 + 0.006*sl t phl 0.268 0.250 + 0.009*sl 0.258 + 0.007*sl 0.268 + 0.006*sl d to y t r 0.093 0.070 + 0.012*sl 0.064 + 0.013*sl 0.051 + 0.014*sl t f 0.074 0.049 + 0.012*sl 0.052 + 0.012*sl 0.044 + 0.012*sl t plh 0.454 0.437 + 0.009*sl 0.444 + 0.007*sl 0.452 + 0.006*sl t phl 0.286 0.268 + 0.009*sl 0.275 + 0.007*sl 0.285 + 0.006*sl e to y t r 0.095 0.069 + 0.013*sl 0.069 + 0.013*sl 0.052 + 0.014*sl t f 0.074 0.050 + 0.012*sl 0.052 + 0.012*sl 0.044 + 0.012*sl t plh 0.486 0.468 + 0.009*sl 0.476 + 0.007*sl 0.483 + 0.006*sl t phl 0.279 0.261 + 0.009*sl 0.269 + 0.007*sl 0.279 + 0.006*sl f to y t r 0.093 0.068 + 0.012*sl 0.064 + 0.013*sl 0.051 + 0.014*sl t f 0.077 0.053 + 0.012*sl 0.054 + 0.011*sl 0.046 + 0.012*sl t plh 0.490 0.473 + 0.009*sl 0.480 + 0.007*sl 0.487 + 0.006*sl t phl 0.314 0.296 + 0.009*sl 0.304 + 0.007*sl 0.314 + 0.006*sl g to y t r 0.095 0.069 + 0.013*sl 0.069 + 0.013*sl 0.052 + 0.014*sl t f 0.076 0.052 + 0.012*sl 0.055 + 0.011*sl 0.046 + 0.012*sl t plh 0.523 0.506 + 0.009*sl 0.513 + 0.007*sl 0.520 + 0.006*sl t phl 0.309 0.291 + 0.009*sl 0.298 + 0.007*sl 0.309 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-139 STD111 ao322/ao322d2/ao322d4 3-and and two 2-ands into 3-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao322d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.087 0.074 + 0.006*sl 0.074 + 0.006*sl 0.059 + 0.007*sl t f 0.072 0.059 + 0.006*sl 0.061 + 0.006*sl 0.056 + 0.006*sl t plh 0.377 0.367 + 0.005*sl 0.373 + 0.004*sl 0.385 + 0.003*sl t phl 0.287 0.277 + 0.005*sl 0.283 + 0.004*sl 0.299 + 0.003*sl b to y t r 0.089 0.077 + 0.006*sl 0.075 + 0.006*sl 0.061 + 0.007*sl t f 0.072 0.058 + 0.007*sl 0.062 + 0.006*sl 0.055 + 0.006*sl t plh 0.407 0.396 + 0.005*sl 0.402 + 0.004*sl 0.415 + 0.003*sl t phl 0.289 0.278 + 0.005*sl 0.285 + 0.004*sl 0.301 + 0.003*sl c to y t r 0.091 0.079 + 0.006*sl 0.077 + 0.006*sl 0.063 + 0.007*sl t f 0.072 0.060 + 0.006*sl 0.060 + 0.006*sl 0.057 + 0.006*sl t plh 0.434 0.424 + 0.005*sl 0.430 + 0.004*sl 0.443 + 0.003*sl t phl 0.288 0.277 + 0.005*sl 0.283 + 0.004*sl 0.299 + 0.003*sl d to y t r 0.089 0.077 + 0.006*sl 0.076 + 0.006*sl 0.061 + 0.007*sl t f 0.069 0.055 + 0.007*sl 0.060 + 0.006*sl 0.054 + 0.006*sl t plh 0.479 0.468 + 0.005*sl 0.474 + 0.004*sl 0.487 + 0.003*sl t phl 0.301 0.291 + 0.005*sl 0.297 + 0.004*sl 0.312 + 0.003*sl e to y t r 0.091 0.080 + 0.006*sl 0.077 + 0.006*sl 0.063 + 0.007*sl t f 0.070 0.057 + 0.007*sl 0.060 + 0.006*sl 0.054 + 0.006*sl t plh 0.509 0.498 + 0.005*sl 0.504 + 0.004*sl 0.518 + 0.003*sl t phl 0.295 0.285 + 0.005*sl 0.291 + 0.004*sl 0.306 + 0.003*sl f to y t r 0.088 0.076 + 0.006*sl 0.075 + 0.006*sl 0.062 + 0.007*sl t f 0.072 0.059 + 0.007*sl 0.062 + 0.006*sl 0.056 + 0.006*sl t plh 0.514 0.504 + 0.005*sl 0.510 + 0.004*sl 0.523 + 0.003*sl t phl 0.332 0.321 + 0.005*sl 0.327 + 0.004*sl 0.343 + 0.003*sl g to y t r 0.091 0.079 + 0.006*sl 0.077 + 0.006*sl 0.063 + 0.007*sl t f 0.072 0.060 + 0.006*sl 0.062 + 0.006*sl 0.057 + 0.006*sl t plh 0.546 0.536 + 0.005*sl 0.542 + 0.004*sl 0.555 + 0.003*sl t phl 0.326 0.316 + 0.005*sl 0.322 + 0.004*sl 0.338 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-140 samsung asic ao33/ao33d2/ao33d4 two 3-ands into 2-nor with 1x/2x/4x drive logic symbol cell data input load (sl) ao33 ao33d2 ao33d4 abcdefabcdefabcdef 0.9 0.9 1.0 0.9 1.0 1.0 0.9 0.9 1.0 0.9 1.0 1.0 0.9 0.9 1.0 0.9 1.0 1.0 gate count ao33 ao33d2 ao33d4 2.33 3.00 3.67 y a b c d e f truth table abcdefy 111xxx0 xxx1110 other states 1
samsung asic 3-141 STD111 ao33/ao33d2/ao33d4 two 3-ands into 2-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao33 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.372 0.232 + 0.070*sl 0.225 + 0.072*sl 0.217 + 0.073*sl t f 0.275 0.190 + 0.043*sl 0.179 + 0.046*sl 0.163 + 0.047*sl t plh 0.197 0.134 + 0.031*sl 0.135 + 0.031*sl 0.136 + 0.031*sl t phl 0.128 0.082 + 0.023*sl 0.084 + 0.022*sl 0.086 + 0.022*sl b to y t r 0.404 0.264 + 0.070*sl 0.256 + 0.072*sl 0.249 + 0.073*sl t f 0.271 0.184 + 0.044*sl 0.174 + 0.046*sl 0.164 + 0.047*sl t plh 0.218 0.156 + 0.031*sl 0.156 + 0.031*sl 0.156 + 0.031*sl t phl 0.130 0.083 + 0.023*sl 0.086 + 0.023*sl 0.089 + 0.022*sl c to y t r 0.437 0.297 + 0.070*sl 0.290 + 0.072*sl 0.282 + 0.073*sl t f 0.266 0.177 + 0.045*sl 0.169 + 0.047*sl 0.161 + 0.047*sl t plh 0.236 0.174 + 0.031*sl 0.174 + 0.031*sl 0.175 + 0.031*sl t phl 0.127 0.081 + 0.023*sl 0.084 + 0.023*sl 0.087 + 0.022*sl d to y t r 0.372 0.231 + 0.070*sl 0.225 + 0.072*sl 0.219 + 0.073*sl t f 0.292 0.203 + 0.044*sl 0.196 + 0.046*sl 0.185 + 0.047*sl t plh 0.233 0.168 + 0.032*sl 0.171 + 0.032*sl 0.174 + 0.031*sl t phl 0.178 0.133 + 0.022*sl 0.134 + 0.022*sl 0.136 + 0.022*sl e to y t r 0.404 0.262 + 0.071*sl 0.257 + 0.072*sl 0.252 + 0.073*sl t f 0.290 0.199 + 0.045*sl 0.194 + 0.047*sl 0.186 + 0.047*sl t plh 0.255 0.191 + 0.032*sl 0.193 + 0.031*sl 0.195 + 0.031*sl t phl 0.181 0.136 + 0.023*sl 0.138 + 0.022*sl 0.139 + 0.022*sl f to y t r 0.438 0.295 + 0.071*sl 0.292 + 0.072*sl 0.286 + 0.073*sl t f 0.286 0.195 + 0.046*sl 0.190 + 0.047*sl 0.185 + 0.047*sl t plh 0.275 0.211 + 0.032*sl 0.213 + 0.031*sl 0.215 + 0.031*sl t phl 0.179 0.134 + 0.023*sl 0.136 + 0.022*sl 0.138 + 0.022*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-142 samsung asic ao33/ao33d2/ao33d4 two 3-ands into 2-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao33d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.085 0.059 + 0.013*sl 0.058 + 0.013*sl 0.045 + 0.014*sl t f 0.076 0.051 + 0.012*sl 0.054 + 0.012*sl 0.046 + 0.012*sl t plh 0.315 0.299 + 0.008*sl 0.305 + 0.007*sl 0.311 + 0.006*sl t phl 0.250 0.232 + 0.009*sl 0.240 + 0.007*sl 0.250 + 0.006*sl b to y t r 0.086 0.060 + 0.013*sl 0.059 + 0.013*sl 0.046 + 0.014*sl t f 0.077 0.053 + 0.012*sl 0.054 + 0.012*sl 0.046 + 0.012*sl t plh 0.341 0.325 + 0.008*sl 0.331 + 0.007*sl 0.337 + 0.006*sl t phl 0.253 0.235 + 0.009*sl 0.242 + 0.007*sl 0.252 + 0.006*sl c to y t r 0.087 0.061 + 0.013*sl 0.061 + 0.013*sl 0.047 + 0.014*sl t f 0.076 0.052 + 0.012*sl 0.054 + 0.012*sl 0.045 + 0.012*sl t plh 0.363 0.346 + 0.008*sl 0.352 + 0.007*sl 0.359 + 0.006*sl t phl 0.251 0.232 + 0.009*sl 0.240 + 0.007*sl 0.250 + 0.006*sl d to y t r 0.084 0.058 + 0.013*sl 0.057 + 0.013*sl 0.045 + 0.014*sl t f 0.076 0.052 + 0.012*sl 0.055 + 0.011*sl 0.046 + 0.012*sl t plh 0.349 0.333 + 0.008*sl 0.339 + 0.007*sl 0.345 + 0.006*sl t phl 0.302 0.283 + 0.009*sl 0.291 + 0.007*sl 0.301 + 0.006*sl e to y t r 0.086 0.059 + 0.013*sl 0.060 + 0.013*sl 0.046 + 0.014*sl t f 0.076 0.051 + 0.012*sl 0.054 + 0.012*sl 0.046 + 0.012*sl t plh 0.378 0.362 + 0.008*sl 0.368 + 0.007*sl 0.375 + 0.006*sl t phl 0.304 0.286 + 0.009*sl 0.294 + 0.007*sl 0.304 + 0.006*sl f to y t r 0.088 0.061 + 0.013*sl 0.061 + 0.013*sl 0.047 + 0.014*sl t f 0.077 0.053 + 0.012*sl 0.054 + 0.012*sl 0.046 + 0.012*sl t plh 0.401 0.384 + 0.008*sl 0.390 + 0.007*sl 0.397 + 0.006*sl t phl 0.303 0.285 + 0.009*sl 0.292 + 0.007*sl 0.303 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-143 STD111 ao33/ao33d2/ao33d4 two 3-ands into 2-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao33d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.080 0.067 + 0.007*sl 0.067 + 0.007*sl 0.054 + 0.007*sl t f 0.072 0.060 + 0.006*sl 0.062 + 0.006*sl 0.056 + 0.006*sl t plh 0.340 0.330 + 0.005*sl 0.335 + 0.004*sl 0.346 + 0.003*sl t phl 0.271 0.260 + 0.005*sl 0.266 + 0.004*sl 0.282 + 0.003*sl b to y t r 0.081 0.069 + 0.006*sl 0.068 + 0.006*sl 0.055 + 0.007*sl t f 0.072 0.060 + 0.006*sl 0.062 + 0.006*sl 0.056 + 0.006*sl t plh 0.366 0.356 + 0.005*sl 0.361 + 0.004*sl 0.373 + 0.003*sl t phl 0.273 0.262 + 0.005*sl 0.268 + 0.004*sl 0.284 + 0.003*sl c to y t r 0.083 0.071 + 0.006*sl 0.069 + 0.006*sl 0.056 + 0.007*sl t f 0.072 0.061 + 0.006*sl 0.061 + 0.006*sl 0.057 + 0.006*sl t plh 0.387 0.377 + 0.005*sl 0.383 + 0.004*sl 0.394 + 0.003*sl t phl 0.271 0.260 + 0.005*sl 0.265 + 0.004*sl 0.282 + 0.003*sl d to y t r 0.080 0.067 + 0.006*sl 0.067 + 0.007*sl 0.054 + 0.007*sl t f 0.073 0.061 + 0.006*sl 0.061 + 0.006*sl 0.057 + 0.006*sl t plh 0.374 0.364 + 0.005*sl 0.369 + 0.004*sl 0.381 + 0.003*sl t phl 0.322 0.311 + 0.005*sl 0.317 + 0.004*sl 0.333 + 0.003*sl e to y t r 0.081 0.069 + 0.006*sl 0.068 + 0.006*sl 0.055 + 0.007*sl t f 0.072 0.060 + 0.006*sl 0.061 + 0.006*sl 0.057 + 0.006*sl t plh 0.403 0.393 + 0.005*sl 0.399 + 0.004*sl 0.410 + 0.003*sl t phl 0.324 0.314 + 0.005*sl 0.320 + 0.004*sl 0.335 + 0.003*sl f to y t r 0.083 0.071 + 0.006*sl 0.069 + 0.006*sl 0.056 + 0.007*sl t f 0.073 0.061 + 0.006*sl 0.061 + 0.006*sl 0.057 + 0.006*sl t plh 0.425 0.415 + 0.005*sl 0.421 + 0.004*sl 0.432 + 0.003*sl t phl 0.323 0.313 + 0.005*sl 0.318 + 0.004*sl 0.334 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-144 samsung asic ao331/ao331d2/ao331d4 two 3-ands into 3-nor with 1x/2x/4x drive logic symbol cell data input load (sl) gate count ao331 ao331 abcdefg 1.0 1.0 1.0 1.0 1.0 1.0 1.0 2.67 ao331d2 ao331d2 abcdefg 1.0 1.0 1.0 1.0 1.0 1.1 1.0 3.33 ao331d4 ao331d4 abcdefg 1.0 1.0 1.0 1.0 1.0 1.1 1.0 4.00 a b c y g d e f truth table abcdefgy 111xxxx0 xxx111x0 xxxxxx10 other states 1
samsung asic 3-145 STD111 ao331/ao331d2/ao331d4 two 3-ands into 3-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao331 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.527 0.355 + 0.086*sl 0.349 + 0.088*sl 0.346 + 0.088*sl t f 0.296 0.209 + 0.043*sl 0.200 + 0.046*sl 0.186 + 0.047*sl t plh 0.228 0.153 + 0.037*sl 0.152 + 0.038*sl 0.154 + 0.037*sl t phl 0.143 0.098 + 0.022*sl 0.099 + 0.022*sl 0.101 + 0.022*sl b to y t r 0.565 0.393 + 0.086*sl 0.387 + 0.088*sl 0.384 + 0.088*sl t f 0.293 0.204 + 0.044*sl 0.196 + 0.046*sl 0.187 + 0.047*sl t plh 0.252 0.177 + 0.037*sl 0.177 + 0.037*sl 0.177 + 0.037*sl t phl 0.145 0.099 + 0.023*sl 0.101 + 0.023*sl 0.104 + 0.022*sl c to y t r 0.602 0.431 + 0.085*sl 0.425 + 0.087*sl 0.421 + 0.087*sl t f 0.288 0.197 + 0.045*sl 0.192 + 0.047*sl 0.186 + 0.047*sl t plh 0.272 0.198 + 0.037*sl 0.198 + 0.037*sl 0.198 + 0.037*sl t phl 0.142 0.097 + 0.023*sl 0.098 + 0.023*sl 0.101 + 0.022*sl d to y t r 0.540 0.371 + 0.084*sl 0.366 + 0.086*sl 0.360 + 0.086*sl t f 0.329 0.238 + 0.046*sl 0.234 + 0.047*sl 0.225 + 0.048*sl t plh 0.305 0.228 + 0.038*sl 0.230 + 0.038*sl 0.235 + 0.037*sl t phl 0.207 0.162 + 0.023*sl 0.163 + 0.022*sl 0.165 + 0.022*sl e to y t r 0.583 0.411 + 0.086*sl 0.408 + 0.087*sl 0.403 + 0.087*sl t f 0.328 0.236 + 0.046*sl 0.233 + 0.047*sl 0.227 + 0.047*sl t plh 0.334 0.257 + 0.038*sl 0.260 + 0.038*sl 0.263 + 0.038*sl t phl 0.211 0.165 + 0.023*sl 0.167 + 0.022*sl 0.169 + 0.022*sl f to y t r 0.620 0.449 + 0.085*sl 0.446 + 0.086*sl 0.441 + 0.086*sl t f 0.326 0.232 + 0.047*sl 0.231 + 0.047*sl 0.226 + 0.048*sl t plh 0.356 0.280 + 0.038*sl 0.282 + 0.038*sl 0.285 + 0.037*sl t phl 0.209 0.163 + 0.023*sl 0.165 + 0.022*sl 0.167 + 0.022*sl g to y t r 0.619 0.449 + 0.085*sl 0.446 + 0.086*sl 0.441 + 0.086*sl t f 0.249 0.205 + 0.022*sl 0.200 + 0.023*sl 0.190 + 0.024*sl t plh 0.383 0.307 + 0.038*sl 0.309 + 0.038*sl 0.312 + 0.037*sl t phl 0.150 0.121 + 0.014*sl 0.123 + 0.014*sl 0.128 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-146 samsung asic ao331/ao331d2/ao331d4 two 3-ands into 3-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao331d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.092 0.066 + 0.013*sl 0.065 + 0.013*sl 0.050 + 0.014*sl t f 0.077 0.054 + 0.012*sl 0.054 + 0.012*sl 0.047 + 0.012*sl t plh 0.358 0.341 + 0.008*sl 0.348 + 0.007*sl 0.355 + 0.006*sl t phl 0.268 0.250 + 0.009*sl 0.258 + 0.007*sl 0.268 + 0.006*sl b to y t r 0.094 0.069 + 0.013*sl 0.068 + 0.013*sl 0.052 + 0.014*sl t f 0.077 0.054 + 0.012*sl 0.054 + 0.012*sl 0.047 + 0.012*sl t plh 0.388 0.371 + 0.009*sl 0.378 + 0.007*sl 0.385 + 0.006*sl t phl 0.270 0.252 + 0.009*sl 0.260 + 0.007*sl 0.270 + 0.006*sl c to y t r 0.096 0.073 + 0.012*sl 0.067 + 0.013*sl 0.054 + 0.014*sl t f 0.077 0.053 + 0.012*sl 0.055 + 0.011*sl 0.046 + 0.012*sl t plh 0.413 0.396 + 0.009*sl 0.403 + 0.007*sl 0.411 + 0.006*sl t phl 0.268 0.250 + 0.009*sl 0.257 + 0.007*sl 0.268 + 0.006*sl d to y t r 0.092 0.069 + 0.012*sl 0.063 + 0.013*sl 0.050 + 0.014*sl t f 0.075 0.050 + 0.013*sl 0.055 + 0.011*sl 0.046 + 0.012*sl t plh 0.433 0.417 + 0.008*sl 0.423 + 0.007*sl 0.431 + 0.006*sl t phl 0.333 0.315 + 0.009*sl 0.322 + 0.007*sl 0.333 + 0.006*sl e to y t r 0.094 0.069 + 0.013*sl 0.068 + 0.013*sl 0.052 + 0.014*sl t f 0.077 0.053 + 0.012*sl 0.054 + 0.012*sl 0.047 + 0.012*sl t plh 0.468 0.451 + 0.009*sl 0.458 + 0.007*sl 0.466 + 0.006*sl t phl 0.336 0.318 + 0.009*sl 0.325 + 0.007*sl 0.336 + 0.006*sl f to y t r 0.096 0.073 + 0.012*sl 0.067 + 0.013*sl 0.054 + 0.014*sl t f 0.076 0.051 + 0.012*sl 0.055 + 0.011*sl 0.046 + 0.012*sl t plh 0.496 0.479 + 0.009*sl 0.486 + 0.007*sl 0.494 + 0.006*sl t phl 0.334 0.316 + 0.009*sl 0.324 + 0.007*sl 0.334 + 0.006*sl g to y t r 0.096 0.073 + 0.012*sl 0.068 + 0.013*sl 0.054 + 0.014*sl t f 0.076 0.052 + 0.012*sl 0.054 + 0.011*sl 0.045 + 0.012*sl t plh 0.522 0.505 + 0.009*sl 0.512 + 0.007*sl 0.520 + 0.006*sl t phl 0.279 0.261 + 0.009*sl 0.268 + 0.007*sl 0.278 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-147 STD111 ao331/ao331d2/ao331d4 two 3-ands into 3-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao331d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.088 0.076 + 0.006*sl 0.074 + 0.006*sl 0.061 + 0.007*sl t f 0.072 0.060 + 0.006*sl 0.062 + 0.006*sl 0.057 + 0.006*sl t plh 0.386 0.376 + 0.005*sl 0.382 + 0.004*sl 0.395 + 0.003*sl t phl 0.289 0.278 + 0.005*sl 0.284 + 0.004*sl 0.300 + 0.003*sl b to y t r 0.090 0.078 + 0.006*sl 0.076 + 0.006*sl 0.062 + 0.007*sl t f 0.073 0.061 + 0.006*sl 0.062 + 0.006*sl 0.058 + 0.006*sl t plh 0.417 0.406 + 0.005*sl 0.412 + 0.004*sl 0.425 + 0.003*sl t phl 0.291 0.280 + 0.005*sl 0.286 + 0.004*sl 0.302 + 0.003*sl c to y t r 0.091 0.079 + 0.006*sl 0.079 + 0.006*sl 0.063 + 0.007*sl t f 0.073 0.061 + 0.006*sl 0.062 + 0.006*sl 0.057 + 0.006*sl t plh 0.442 0.431 + 0.005*sl 0.437 + 0.004*sl 0.451 + 0.003*sl t phl 0.289 0.278 + 0.005*sl 0.284 + 0.004*sl 0.300 + 0.003*sl d to y t r 0.088 0.075 + 0.007*sl 0.075 + 0.006*sl 0.060 + 0.007*sl t f 0.073 0.060 + 0.006*sl 0.063 + 0.006*sl 0.057 + 0.006*sl t plh 0.463 0.452 + 0.005*sl 0.458 + 0.004*sl 0.471 + 0.003*sl t phl 0.354 0.343 + 0.005*sl 0.349 + 0.004*sl 0.365 + 0.003*sl e to y t r 0.090 0.078 + 0.006*sl 0.076 + 0.006*sl 0.063 + 0.007*sl t f 0.074 0.061 + 0.006*sl 0.063 + 0.006*sl 0.057 + 0.006*sl t plh 0.497 0.487 + 0.005*sl 0.493 + 0.004*sl 0.506 + 0.003*sl t phl 0.357 0.346 + 0.005*sl 0.352 + 0.004*sl 0.368 + 0.003*sl f to y t r 0.092 0.079 + 0.006*sl 0.079 + 0.006*sl 0.064 + 0.007*sl t f 0.073 0.060 + 0.007*sl 0.063 + 0.006*sl 0.057 + 0.006*sl t plh 0.525 0.514 + 0.005*sl 0.521 + 0.004*sl 0.534 + 0.003*sl t phl 0.355 0.344 + 0.005*sl 0.350 + 0.004*sl 0.366 + 0.003*sl g to y t r 0.092 0.080 + 0.006*sl 0.078 + 0.006*sl 0.064 + 0.007*sl t f 0.071 0.059 + 0.006*sl 0.060 + 0.006*sl 0.056 + 0.006*sl t plh 0.551 0.541 + 0.005*sl 0.547 + 0.004*sl 0.560 + 0.003*sl t phl 0.291 0.281 + 0.005*sl 0.286 + 0.004*sl 0.302 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-148 samsung asic ao332/ao332d2/ao332d4 two 3-ands and 2-and into 3-nor with 1x/2x/4x drive logic symbol cell data input load (sl) gate count ao332 ao332 abcdefgh 1.0 1.0 1.0 1.0 1.0 1.1 1.1 1.1 3.00 ao332d2 ao332d2 abcdefgh 1.0 1.0 1.0 1.0 1.0 1.1 1.1 1.1 4.00 ao332d4 ao332d4 abcdefgh 1.0 1.0 1.0 1.0 1.0 1.1 1.1 1.1 4.67 d f a c y g h e b truth table abcdefghy 111xxxxx0 xxx111xx0 xxxxxx110 other states 1
samsung asic 3-149 STD111 ao332/ao332d2/ao332d4 two 3-ands and 2-and into 3-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao332 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.529 0.356 + 0.086*sl 0.351 + 0.088*sl 0.348 + 0.088*sl t f 0.328 0.241 + 0.044*sl 0.233 + 0.046*sl 0.219 + 0.047*sl t plh 0.228 0.154 + 0.037*sl 0.153 + 0.037*sl 0.154 + 0.037*sl t phl 0.152 0.107 + 0.023*sl 0.108 + 0.022*sl 0.110 + 0.022*sl b to y t r 0.567 0.394 + 0.086*sl 0.389 + 0.088*sl 0.386 + 0.088*sl t f 0.325 0.236 + 0.044*sl 0.229 + 0.046*sl 0.220 + 0.047*sl t plh 0.252 0.177 + 0.037*sl 0.177 + 0.037*sl 0.177 + 0.037*sl t phl 0.154 0.109 + 0.023*sl 0.109 + 0.023*sl 0.113 + 0.022*sl c to y t r 0.608 0.435 + 0.086*sl 0.429 + 0.088*sl 0.426 + 0.088*sl t f 0.320 0.229 + 0.045*sl 0.225 + 0.047*sl 0.218 + 0.047*sl t plh 0.273 0.199 + 0.037*sl 0.199 + 0.037*sl 0.199 + 0.037*sl t phl 0.151 0.105 + 0.023*sl 0.107 + 0.023*sl 0.111 + 0.022*sl d to y t r 0.587 0.416 + 0.086*sl 0.413 + 0.087*sl 0.408 + 0.087*sl t f 0.383 0.294 + 0.045*sl 0.287 + 0.046*sl 0.277 + 0.047*sl t plh 0.335 0.258 + 0.039*sl 0.261 + 0.038*sl 0.264 + 0.038*sl t phl 0.213 0.168 + 0.023*sl 0.169 + 0.022*sl 0.170 + 0.022*sl e to y t r 0.626 0.454 + 0.086*sl 0.451 + 0.087*sl 0.448 + 0.087*sl t f 0.382 0.291 + 0.045*sl 0.286 + 0.047*sl 0.279 + 0.047*sl t plh 0.362 0.285 + 0.038*sl 0.287 + 0.038*sl 0.290 + 0.038*sl t phl 0.216 0.171 + 0.023*sl 0.172 + 0.022*sl 0.174 + 0.022*sl f to y t r 0.663 0.492 + 0.086*sl 0.489 + 0.086*sl 0.486 + 0.087*sl t f 0.380 0.288 + 0.046*sl 0.284 + 0.047*sl 0.278 + 0.047*sl t plh 0.384 0.308 + 0.038*sl 0.310 + 0.038*sl 0.312 + 0.037*sl t phl 0.214 0.169 + 0.023*sl 0.170 + 0.022*sl 0.173 + 0.022*sl g to y t r 0.626 0.456 + 0.085*sl 0.452 + 0.086*sl 0.448 + 0.086*sl t f 0.337 0.276 + 0.031*sl 0.271 + 0.032*sl 0.260 + 0.033*sl t plh 0.400 0.323 + 0.039*sl 0.326 + 0.038*sl 0.330 + 0.037*sl t phl 0.181 0.145 + 0.018*sl 0.148 + 0.017*sl 0.155 + 0.017*sl h to y t r 0.663 0.492 + 0.085*sl 0.490 + 0.086*sl 0.486 + 0.087*sl t f 0.331 0.268 + 0.031*sl 0.265 + 0.032*sl 0.258 + 0.033*sl t plh 0.425 0.349 + 0.038*sl 0.350 + 0.038*sl 0.353 + 0.037*sl t phl 0.175 0.139 + 0.018*sl 0.142 + 0.017*sl 0.150 + 0.017*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-150 samsung asic ao332/ao332d2/ao332d4 two 3-ands and 2-and into 3-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao332d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.090 0.066 + 0.012*sl 0.062 + 0.013*sl 0.049 + 0.014*sl t f 0.078 0.053 + 0.012*sl 0.056 + 0.011*sl 0.048 + 0.012*sl t plh 0.351 0.334 + 0.008*sl 0.341 + 0.007*sl 0.348 + 0.006*sl t phl 0.280 0.262 + 0.009*sl 0.270 + 0.007*sl 0.280 + 0.006*sl b to y t r 0.093 0.068 + 0.013*sl 0.066 + 0.013*sl 0.050 + 0.014*sl t f 0.078 0.054 + 0.012*sl 0.056 + 0.011*sl 0.048 + 0.012*sl t plh 0.379 0.362 + 0.008*sl 0.369 + 0.007*sl 0.377 + 0.006*sl t phl 0.281 0.263 + 0.009*sl 0.271 + 0.007*sl 0.281 + 0.006*sl c to y t r 0.095 0.069 + 0.013*sl 0.069 + 0.013*sl 0.052 + 0.014*sl t f 0.078 0.054 + 0.012*sl 0.056 + 0.011*sl 0.048 + 0.012*sl t plh 0.406 0.389 + 0.009*sl 0.396 + 0.007*sl 0.404 + 0.006*sl t phl 0.279 0.261 + 0.009*sl 0.268 + 0.007*sl 0.279 + 0.006*sl d to y t r 0.093 0.068 + 0.013*sl 0.067 + 0.013*sl 0.051 + 0.014*sl t f 0.079 0.055 + 0.012*sl 0.057 + 0.011*sl 0.049 + 0.012*sl t plh 0.460 0.443 + 0.008*sl 0.450 + 0.007*sl 0.458 + 0.006*sl t phl 0.345 0.326 + 0.009*sl 0.334 + 0.007*sl 0.345 + 0.006*sl e to y t r 0.095 0.072 + 0.012*sl 0.067 + 0.013*sl 0.053 + 0.014*sl t f 0.078 0.054 + 0.012*sl 0.057 + 0.011*sl 0.048 + 0.012*sl t plh 0.492 0.475 + 0.009*sl 0.483 + 0.007*sl 0.490 + 0.006*sl t phl 0.348 0.329 + 0.009*sl 0.337 + 0.007*sl 0.348 + 0.006*sl f to y t r 0.096 0.072 + 0.012*sl 0.070 + 0.013*sl 0.054 + 0.014*sl t f 0.079 0.055 + 0.012*sl 0.057 + 0.011*sl 0.049 + 0.012*sl t plh 0.519 0.502 + 0.009*sl 0.509 + 0.007*sl 0.517 + 0.006*sl t phl 0.346 0.328 + 0.009*sl 0.335 + 0.007*sl 0.346 + 0.006*sl g to y t r 0.095 0.071 + 0.012*sl 0.068 + 0.013*sl 0.053 + 0.014*sl t f 0.079 0.055 + 0.012*sl 0.058 + 0.011*sl 0.048 + 0.012*sl t plh 0.530 0.513 + 0.009*sl 0.520 + 0.007*sl 0.527 + 0.006*sl t phl 0.315 0.297 + 0.009*sl 0.304 + 0.007*sl 0.315 + 0.006*sl h to y t r 0.096 0.071 + 0.013*sl 0.070 + 0.013*sl 0.054 + 0.014*sl t f 0.080 0.056 + 0.012*sl 0.058 + 0.011*sl 0.049 + 0.012*sl t plh 0.559 0.542 + 0.009*sl 0.549 + 0.007*sl 0.557 + 0.006*sl t phl 0.308 0.290 + 0.009*sl 0.298 + 0.007*sl 0.309 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-151 STD111 ao332/ao332d2/ao332d4 two 3-ands and 2-and into 3-nor with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao332d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.086 0.074 + 0.006*sl 0.073 + 0.006*sl 0.059 + 0.007*sl t f 0.074 0.061 + 0.006*sl 0.063 + 0.006*sl 0.057 + 0.006*sl t plh 0.376 0.366 + 0.005*sl 0.372 + 0.004*sl 0.384 + 0.003*sl t phl 0.298 0.287 + 0.005*sl 0.293 + 0.004*sl 0.309 + 0.003*sl b to y t r 0.088 0.076 + 0.006*sl 0.075 + 0.006*sl 0.060 + 0.007*sl t f 0.074 0.062 + 0.006*sl 0.062 + 0.006*sl 0.058 + 0.006*sl t plh 0.405 0.395 + 0.005*sl 0.401 + 0.004*sl 0.413 + 0.003*sl t phl 0.299 0.288 + 0.005*sl 0.294 + 0.004*sl 0.310 + 0.003*sl c to y t r 0.091 0.080 + 0.006*sl 0.077 + 0.006*sl 0.063 + 0.007*sl t f 0.073 0.061 + 0.006*sl 0.062 + 0.006*sl 0.057 + 0.006*sl t plh 0.432 0.421 + 0.005*sl 0.427 + 0.004*sl 0.440 + 0.003*sl t phl 0.296 0.285 + 0.005*sl 0.291 + 0.004*sl 0.308 + 0.003*sl d to y t r 0.088 0.077 + 0.006*sl 0.075 + 0.006*sl 0.061 + 0.007*sl t f 0.075 0.063 + 0.006*sl 0.063 + 0.006*sl 0.059 + 0.006*sl t plh 0.486 0.476 + 0.005*sl 0.482 + 0.004*sl 0.495 + 0.003*sl t phl 0.362 0.352 + 0.005*sl 0.357 + 0.004*sl 0.374 + 0.003*sl e to y t r 0.091 0.079 + 0.006*sl 0.077 + 0.006*sl 0.063 + 0.007*sl t f 0.075 0.063 + 0.006*sl 0.064 + 0.006*sl 0.059 + 0.006*sl t plh 0.519 0.508 + 0.005*sl 0.514 + 0.004*sl 0.527 + 0.003*sl t phl 0.365 0.355 + 0.005*sl 0.360 + 0.004*sl 0.377 + 0.003*sl f to y t r 0.093 0.080 + 0.006*sl 0.080 + 0.006*sl 0.064 + 0.007*sl t f 0.075 0.063 + 0.006*sl 0.064 + 0.006*sl 0.059 + 0.006*sl t plh 0.546 0.535 + 0.005*sl 0.541 + 0.004*sl 0.555 + 0.003*sl t phl 0.364 0.353 + 0.005*sl 0.359 + 0.004*sl 0.375 + 0.003*sl g to y t r 0.090 0.078 + 0.006*sl 0.076 + 0.006*sl 0.063 + 0.007*sl t f 0.075 0.062 + 0.006*sl 0.065 + 0.006*sl 0.058 + 0.006*sl t plh 0.556 0.546 + 0.005*sl 0.552 + 0.004*sl 0.565 + 0.003*sl t phl 0.331 0.320 + 0.005*sl 0.326 + 0.004*sl 0.343 + 0.003*sl h to y t r 0.093 0.080 + 0.006*sl 0.080 + 0.006*sl 0.064 + 0.007*sl t f 0.076 0.064 + 0.006*sl 0.065 + 0.006*sl 0.059 + 0.006*sl t plh 0.586 0.575 + 0.005*sl 0.582 + 0.004*sl 0.595 + 0.003*sl t phl 0.324 0.314 + 0.005*sl 0.319 + 0.004*sl 0.336 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-152 samsung asic ao4111/ao4111d2 4-and into 4-nor with 1x/2x drive logic symbolcell data cell data input load (sl) gate count ao4111 ao4111 abcdefg 1.0 1.0 1.0 1.0 0.8 0.8 0.9 2.67 ao4111d2 ao4111d2 abcdefg 1.0 1.0 1.0 1.0 0.8 0.9 0.9 3.33 d f a c y g e b truth table abcdefgy 1111xxx0 xxxx1xx0 xxxxx1x0 xxxxxx10 other states 1
samsung asic 3-153 STD111 ao4111/ao4111d2 4-and into 4-nor with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao4111 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.595 0.376 + 0.110*sl 0.370 + 0.111*sl 0.368 + 0.111*sl t f 0.319 0.191 + 0.064*sl 0.184 + 0.066*sl 0.175 + 0.067*sl t plh 0.195 0.106 + 0.044*sl 0.095 + 0.047*sl 0.096 + 0.047*sl t phl 0.172 0.112 + 0.030*sl 0.112 + 0.030*sl 0.111 + 0.030*sl b to y t r 0.644 0.424 + 0.110*sl 0.418 + 0.112*sl 0.416 + 0.112*sl t f 0.320 0.191 + 0.065*sl 0.186 + 0.066*sl 0.178 + 0.067*sl t plh 0.222 0.130 + 0.046*sl 0.125 + 0.047*sl 0.126 + 0.047*sl t phl 0.182 0.121 + 0.030*sl 0.121 + 0.030*sl 0.122 + 0.030*sl c to y t r 0.692 0.474 + 0.109*sl 0.465 + 0.111*sl 0.463 + 0.112*sl t f 0.318 0.188 + 0.065*sl 0.185 + 0.066*sl 0.178 + 0.067*sl t plh 0.247 0.154 + 0.047*sl 0.152 + 0.047*sl 0.153 + 0.047*sl t phl 0.187 0.125 + 0.031*sl 0.126 + 0.030*sl 0.127 + 0.030*sl d to y t r 0.744 0.527 + 0.109*sl 0.516 + 0.111*sl 0.513 + 0.112*sl t f 0.316 0.185 + 0.066*sl 0.182 + 0.066*sl 0.177 + 0.067*sl t plh 0.273 0.177 + 0.048*sl 0.178 + 0.048*sl 0.180 + 0.047*sl t phl 0.189 0.127 + 0.031*sl 0.128 + 0.031*sl 0.130 + 0.030*sl e to y t r 0.780 0.564 + 0.108*sl 0.559 + 0.109*sl 0.553 + 0.110*sl t f 0.286 0.205 + 0.041*sl 0.201 + 0.042*sl 0.195 + 0.042*sl t plh 0.400 0.302 + 0.049*sl 0.305 + 0.048*sl 0.310 + 0.048*sl t phl 0.221 0.176 + 0.022*sl 0.177 + 0.022*sl 0.179 + 0.022*sl f to y t r 0.781 0.566 + 0.108*sl 0.560 + 0.109*sl 0.553 + 0.110*sl t f 0.318 0.237 + 0.041*sl 0.233 + 0.042*sl 0.228 + 0.042*sl t plh 0.427 0.329 + 0.049*sl 0.332 + 0.048*sl 0.337 + 0.048*sl t phl 0.238 0.192 + 0.023*sl 0.194 + 0.022*sl 0.197 + 0.022*sl g to y t r 0.781 0.565 + 0.108*sl 0.559 + 0.109*sl 0.553 + 0.110*sl t f 0.357 0.277 + 0.040*sl 0.272 + 0.041*sl 0.265 + 0.042*sl t plh 0.437 0.339 + 0.049*sl 0.343 + 0.048*sl 0.347 + 0.048*sl t phl 0.249 0.202 + 0.024*sl 0.205 + 0.023*sl 0.210 + 0.022*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-154 samsung asic ao4111/ao4111d2 4-and into 4-nor with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ao4111d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.093 0.068 + 0.013*sl 0.066 + 0.013*sl 0.051 + 0.014*sl t f 0.075 0.050 + 0.012*sl 0.054 + 0.012*sl 0.046 + 0.012*sl t plh 0.316 0.299 + 0.009*sl 0.306 + 0.007*sl 0.314 + 0.006*sl t phl 0.284 0.265 + 0.009*sl 0.273 + 0.007*sl 0.283 + 0.006*sl b to y t r 0.096 0.071 + 0.012*sl 0.068 + 0.013*sl 0.054 + 0.014*sl t f 0.076 0.051 + 0.012*sl 0.054 + 0.012*sl 0.046 + 0.012*sl t plh 0.351 0.334 + 0.009*sl 0.341 + 0.007*sl 0.349 + 0.006*sl t phl 0.293 0.274 + 0.009*sl 0.282 + 0.007*sl 0.292 + 0.006*sl c to y t r 0.098 0.073 + 0.013*sl 0.072 + 0.013*sl 0.055 + 0.014*sl t f 0.075 0.050 + 0.013*sl 0.054 + 0.012*sl 0.046 + 0.012*sl t plh 0.381 0.364 + 0.009*sl 0.371 + 0.007*sl 0.380 + 0.006*sl t phl 0.297 0.279 + 0.009*sl 0.287 + 0.007*sl 0.297 + 0.006*sl d to y t r 0.101 0.076 + 0.013*sl 0.075 + 0.013*sl 0.058 + 0.014*sl t f 0.075 0.050 + 0.013*sl 0.054 + 0.012*sl 0.046 + 0.012*sl t plh 0.410 0.392 + 0.009*sl 0.400 + 0.007*sl 0.410 + 0.006*sl t phl 0.298 0.280 + 0.009*sl 0.288 + 0.007*sl 0.298 + 0.006*sl e to y t r 0.101 0.079 + 0.011*sl 0.072 + 0.013*sl 0.059 + 0.014*sl t f 0.075 0.050 + 0.013*sl 0.054 + 0.011*sl 0.046 + 0.012*sl t plh 0.537 0.519 + 0.009*sl 0.527 + 0.007*sl 0.536 + 0.006*sl t phl 0.346 0.328 + 0.009*sl 0.336 + 0.007*sl 0.346 + 0.006*sl f to y t r 0.101 0.076 + 0.013*sl 0.076 + 0.013*sl 0.058 + 0.014*sl t f 0.077 0.052 + 0.012*sl 0.056 + 0.011*sl 0.047 + 0.012*sl t plh 0.564 0.546 + 0.009*sl 0.554 + 0.007*sl 0.564 + 0.006*sl t phl 0.366 0.348 + 0.009*sl 0.356 + 0.007*sl 0.366 + 0.006*sl g to y t r 0.100 0.074 + 0.013*sl 0.075 + 0.013*sl 0.057 + 0.014*sl t f 0.078 0.055 + 0.012*sl 0.056 + 0.011*sl 0.048 + 0.012*sl t plh 0.575 0.557 + 0.009*sl 0.565 + 0.007*sl 0.574 + 0.006*sl t phl 0.381 0.363 + 0.009*sl 0.371 + 0.007*sl 0.381 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-155 STD111 oa21dh/oa21/oa21d2/oa21d2b/oa21d4 2-or into 2-nand with 0.5x/1x/2x/2x(buffered)/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa21dh input load (sl) oa21dh oa21 oa21d2 oa21d2b oa21d4 abcabcabcabcabc 0.5 0.6 0.6 0.9 1.0 1.1 1.9 1.9 2.3 0.9 1.0 1.1 0.9 1.0 1.1 gate count oa21dh oa21 oa21d2 oa21d2b oa21d4 1.33 1.33 2.33 2.33 3.00 y c a b path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.347 0.125 + 0.111*sl 0.105 + 0.116*sl 0.094 + 0.117*sl t f 0.257 0.092 + 0.082*sl 0.073 + 0.087*sl 0.061 + 0.089*sl t plh 0.176 0.077 + 0.050*sl 0.076 + 0.050*sl 0.075 + 0.050*sl t phl 0.159 0.074 + 0.043*sl 0.074 + 0.043*sl 0.074 + 0.043*sl b to y t r 0.341 0.115 + 0.113*sl 0.103 + 0.116*sl 0.095 + 0.117*sl t f 0.292 0.127 + 0.082*sl 0.106 + 0.088*sl 0.093 + 0.089*sl t plh 0.177 0.076 + 0.050*sl 0.077 + 0.050*sl 0.077 + 0.050*sl t phl 0.179 0.093 + 0.043*sl 0.093 + 0.043*sl 0.093 + 0.043*sl c to y t r 0.250 0.142 + 0.054*sl 0.124 + 0.059*sl 0.101 + 0.061*sl t f 0.281 0.109 + 0.086*sl 0.101 + 0.088*sl 0.093 + 0.089*sl t plh 0.131 0.077 + 0.027*sl 0.079 + 0.027*sl 0.081 + 0.026*sl t phl 0.174 0.088 + 0.043*sl 0.089 + 0.043*sl 0.090 + 0.043*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table abcy 00x1 xx01 others states 0
STD111 3-156 samsung asic oa21dh/oa21/oa21d2/oa21d2b/oa21d4 2-or into 2-nand with 0.5x/1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa21 oa21d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.220 0.121 + 0.050*sl 0.108 + 0.053*sl 0.090 + 0.055*sl t f 0.166 0.090 + 0.038*sl 0.079 + 0.041*sl 0.062 + 0.043*sl t plh 0.116 0.067 + 0.025*sl 0.072 + 0.023*sl 0.070 + 0.024*sl t phl 0.110 0.066 + 0.022*sl 0.071 + 0.021*sl 0.071 + 0.021*sl b to y t r 0.212 0.109 + 0.052*sl 0.099 + 0.054*sl 0.090 + 0.055*sl t f 0.200 0.124 + 0.038*sl 0.113 + 0.041*sl 0.095 + 0.043*sl t plh 0.116 0.067 + 0.025*sl 0.071 + 0.024*sl 0.071 + 0.024*sl t phl 0.131 0.089 + 0.021*sl 0.090 + 0.021*sl 0.089 + 0.021*sl c to y t r 0.154 0.108 + 0.023*sl 0.096 + 0.026*sl 0.082 + 0.028*sl t f 0.188 0.108 + 0.040*sl 0.099 + 0.042*sl 0.092 + 0.043*sl t plh 0.096 0.068 + 0.014*sl 0.075 + 0.012*sl 0.075 + 0.012*sl t phl 0.122 0.079 + 0.022*sl 0.081 + 0.021*sl 0.082 + 0.021*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.173 0.126 + 0.023*sl 0.117 + 0.026*sl 0.096 + 0.027*sl t f 0.129 0.094 + 0.018*sl 0.086 + 0.020*sl 0.066 + 0.021*sl t plh 0.092 0.065 + 0.014*sl 0.072 + 0.012*sl 0.071 + 0.012*sl t phl 0.088 0.063 + 0.012*sl 0.072 + 0.010*sl 0.072 + 0.010*sl b to y t r 0.164 0.115 + 0.024*sl 0.106 + 0.027*sl 0.093 + 0.027*sl t f 0.165 0.129 + 0.018*sl 0.121 + 0.020*sl 0.100 + 0.022*sl t plh 0.092 0.066 + 0.013*sl 0.070 + 0.012*sl 0.071 + 0.012*sl t phl 0.110 0.088 + 0.011*sl 0.091 + 0.010*sl 0.090 + 0.011*sl c to y t r 0.129 0.107 + 0.011*sl 0.101 + 0.012*sl 0.082 + 0.014*sl t f 0.148 0.108 + 0.020*sl 0.105 + 0.021*sl 0.095 + 0.022*sl t plh 0.082 0.066 + 0.008*sl 0.072 + 0.006*sl 0.075 + 0.006*sl t phl 0.100 0.077 + 0.011*sl 0.081 + 0.011*sl 0.081 + 0.011*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-157 STD111 oa21dh/oa21/oa21d2/oa21d2b/oa21d4 2-or into 2-nand with 0.5x/1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa21d2b oa21d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.077 0.051 + 0.013*sl 0.049 + 0.014*sl 0.040 + 0.014*sl t f 0.069 0.044 + 0.013*sl 0.048 + 0.012*sl 0.040 + 0.012*sl t plh 0.219 0.203 + 0.008*sl 0.208 + 0.007*sl 0.214 + 0.006*sl t phl 0.206 0.188 + 0.009*sl 0.195 + 0.007*sl 0.205 + 0.006*sl b to y t r 0.077 0.051 + 0.013*sl 0.049 + 0.014*sl 0.040 + 0.014*sl t f 0.071 0.048 + 0.012*sl 0.048 + 0.012*sl 0.041 + 0.012*sl t plh 0.220 0.203 + 0.008*sl 0.209 + 0.007*sl 0.215 + 0.006*sl t phl 0.232 0.214 + 0.009*sl 0.222 + 0.007*sl 0.231 + 0.006*sl c to y t r 0.077 0.050 + 0.013*sl 0.050 + 0.014*sl 0.039 + 0.014*sl t f 0.070 0.045 + 0.013*sl 0.049 + 0.012*sl 0.041 + 0.012*sl t plh 0.207 0.191 + 0.008*sl 0.196 + 0.007*sl 0.202 + 0.006*sl t phl 0.223 0.205 + 0.009*sl 0.212 + 0.007*sl 0.222 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.073 0.060 + 0.007*sl 0.060 + 0.007*sl 0.049 + 0.007*sl t f 0.065 0.054 + 0.006*sl 0.053 + 0.006*sl 0.051 + 0.006*sl t plh 0.240 0.231 + 0.005*sl 0.236 + 0.003*sl 0.246 + 0.003*sl t phl 0.225 0.215 + 0.005*sl 0.220 + 0.004*sl 0.235 + 0.003*sl b to y t r 0.073 0.059 + 0.007*sl 0.059 + 0.007*sl 0.049 + 0.007*sl t f 0.066 0.052 + 0.007*sl 0.056 + 0.006*sl 0.051 + 0.006*sl t plh 0.241 0.231 + 0.005*sl 0.236 + 0.003*sl 0.246 + 0.003*sl t phl 0.251 0.241 + 0.005*sl 0.246 + 0.004*sl 0.262 + 0.003*sl c to y t r 0.071 0.058 + 0.007*sl 0.057 + 0.007*sl 0.047 + 0.007*sl t f 0.067 0.054 + 0.006*sl 0.056 + 0.006*sl 0.051 + 0.006*sl t plh 0.222 0.213 + 0.005*sl 0.217 + 0.003*sl 0.227 + 0.003*sl t phl 0.242 0.232 + 0.005*sl 0.237 + 0.004*sl 0.252 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-158 samsung asic oa211dh/oa211/oa211d2/oa211d2b/oa211d4 2-or into 3-nand with 0.5x/1x/2x/2x(buffered)/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa211dh input load (sl) oa211dh oa211 oa211d2 oa211d2b oa211d4 abcdabcdabcdabcdabcd 0.5 0.5 0.5 0.5 1.0 1.1 0.9 0.9 2.1 2.1 1.9 1.8 1.0 1.1 0.9 1.0 1.0 1.1 0.9 1.0 gate count oa211dh oa211 oa211d2 oa211d2b oa211d4 1.67 1.67 2.67 2.67 3.00 y c a b d path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.373 0.148 + 0.112*sl 0.132 + 0.116*sl 0.125 + 0.117*sl t f 0.329 0.134 + 0.098*sl 0.118 + 0.102*sl 0.110 + 0.103*sl t plh 0.191 0.091 + 0.050*sl 0.090 + 0.050*sl 0.090 + 0.050*sl t phl 0.179 0.085 + 0.047*sl 0.084 + 0.047*sl 0.083 + 0.047*sl b to y t r 0.370 0.142 + 0.114*sl 0.132 + 0.116*sl 0.125 + 0.117*sl t f 0.364 0.172 + 0.096*sl 0.154 + 0.101*sl 0.145 + 0.102*sl t plh 0.192 0.092 + 0.050*sl 0.092 + 0.050*sl 0.092 + 0.050*sl t phl 0.199 0.105 + 0.047*sl 0.104 + 0.047*sl 0.104 + 0.047*sl c to y t r 0.346 0.187 + 0.079*sl 0.170 + 0.084*sl 0.155 + 0.085*sl t f 0.360 0.163 + 0.099*sl 0.153 + 0.101*sl 0.146 + 0.102*sl t plh 0.182 0.107 + 0.037*sl 0.109 + 0.037*sl 0.111 + 0.037*sl t phl 0.211 0.116 + 0.048*sl 0.117 + 0.047*sl 0.118 + 0.047*sl d to y t r 0.368 0.210 + 0.079*sl 0.192 + 0.084*sl 0.176 + 0.085*sl t f 0.358 0.158 + 0.100*sl 0.151 + 0.101*sl 0.146 + 0.102*sl t plh 0.192 0.117 + 0.038*sl 0.119 + 0.037*sl 0.121 + 0.037*sl t phl 0.209 0.114 + 0.048*sl 0.115 + 0.047*sl 0.116 + 0.047*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table abcdy 00xx1 xx0x1 xxx01 other states 0
samsung asic 3-159 STD111 oa211dh/oa211/oa211d2/oa211d2b/oa211d4 2-or into 3-nand with 0.5x/1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa211 oa211d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.242 0.139 + 0.051*sl 0.129 + 0.054*sl 0.114 + 0.056*sl t f 0.218 0.126 + 0.046*sl 0.116 + 0.049*sl 0.101 + 0.050*sl t plh 0.130 0.081 + 0.024*sl 0.083 + 0.024*sl 0.082 + 0.024*sl t phl 0.126 0.079 + 0.024*sl 0.080 + 0.023*sl 0.079 + 0.023*sl b to y t r 0.236 0.130 + 0.053*sl 0.123 + 0.055*sl 0.114 + 0.056*sl t f 0.254 0.163 + 0.045*sl 0.153 + 0.048*sl 0.137 + 0.050*sl t plh 0.130 0.080 + 0.025*sl 0.083 + 0.024*sl 0.083 + 0.024*sl t phl 0.145 0.100 + 0.023*sl 0.099 + 0.023*sl 0.099 + 0.023*sl c to y t r 0.203 0.133 + 0.035*sl 0.125 + 0.037*sl 0.111 + 0.039*sl t f 0.246 0.152 + 0.047*sl 0.145 + 0.049*sl 0.138 + 0.050*sl t plh 0.132 0.097 + 0.017*sl 0.099 + 0.017*sl 0.098 + 0.017*sl t phl 0.153 0.106 + 0.024*sl 0.107 + 0.023*sl 0.108 + 0.023*sl d to y t r 0.222 0.152 + 0.035*sl 0.144 + 0.037*sl 0.129 + 0.039*sl t f 0.242 0.147 + 0.048*sl 0.141 + 0.049*sl 0.136 + 0.050*sl t plh 0.140 0.106 + 0.017*sl 0.107 + 0.017*sl 0.107 + 0.017*sl t phl 0.151 0.104 + 0.024*sl 0.105 + 0.023*sl 0.106 + 0.023*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.193 0.142 + 0.025*sl 0.137 + 0.026*sl 0.119 + 0.028*sl t f 0.173 0.128 + 0.023*sl 0.123 + 0.024*sl 0.107 + 0.025*sl t plh 0.106 0.080 + 0.013*sl 0.085 + 0.012*sl 0.084 + 0.012*sl t phl 0.103 0.078 + 0.012*sl 0.081 + 0.011*sl 0.080 + 0.012*sl b to y t r 0.185 0.135 + 0.025*sl 0.129 + 0.027*sl 0.118 + 0.028*sl t f 0.214 0.169 + 0.023*sl 0.163 + 0.024*sl 0.145 + 0.025*sl t plh 0.106 0.080 + 0.013*sl 0.084 + 0.012*sl 0.085 + 0.012*sl t phl 0.125 0.102 + 0.012*sl 0.102 + 0.012*sl 0.102 + 0.012*sl c to y t r 0.171 0.138 + 0.017*sl 0.131 + 0.018*sl 0.116 + 0.019*sl t f 0.205 0.158 + 0.023*sl 0.153 + 0.025*sl 0.144 + 0.025*sl t plh 0.115 0.098 + 0.009*sl 0.100 + 0.008*sl 0.099 + 0.008*sl t phl 0.132 0.108 + 0.012*sl 0.110 + 0.012*sl 0.111 + 0.012*sl d to y t r 0.190 0.157 + 0.017*sl 0.151 + 0.018*sl 0.136 + 0.019*sl t f 0.201 0.152 + 0.024*sl 0.149 + 0.025*sl 0.142 + 0.025*sl t plh 0.125 0.107 + 0.009*sl 0.108 + 0.008*sl 0.108 + 0.008*sl t phl 0.130 0.106 + 0.012*sl 0.107 + 0.012*sl 0.109 + 0.012*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-160 samsung asic oa211dh/oa211/oa211d2/oa211d2b/oa211d4 2-or into 3-nand with 0.5x/1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa211d2b oa211d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.080 0.054 + 0.013*sl 0.053 + 0.013*sl 0.042 + 0.014*sl t f 0.072 0.047 + 0.013*sl 0.051 + 0.011*sl 0.043 + 0.012*sl t plh 0.237 0.221 + 0.008*sl 0.227 + 0.007*sl 0.233 + 0.006*sl t phl 0.230 0.212 + 0.009*sl 0.219 + 0.007*sl 0.229 + 0.006*sl b to y t r 0.080 0.054 + 0.013*sl 0.052 + 0.013*sl 0.042 + 0.014*sl t f 0.073 0.048 + 0.012*sl 0.051 + 0.011*sl 0.044 + 0.012*sl t plh 0.238 0.222 + 0.008*sl 0.227 + 0.007*sl 0.233 + 0.006*sl t phl 0.256 0.238 + 0.009*sl 0.245 + 0.007*sl 0.255 + 0.006*sl c to y t r 0.081 0.054 + 0.013*sl 0.053 + 0.013*sl 0.042 + 0.014*sl t f 0.073 0.048 + 0.012*sl 0.053 + 0.011*sl 0.044 + 0.012*sl t plh 0.248 0.232 + 0.008*sl 0.238 + 0.007*sl 0.243 + 0.006*sl t phl 0.263 0.245 + 0.009*sl 0.252 + 0.007*sl 0.262 + 0.006*sl d to y t r 0.080 0.054 + 0.013*sl 0.052 + 0.013*sl 0.043 + 0.014*sl t f 0.074 0.051 + 0.012*sl 0.051 + 0.011*sl 0.044 + 0.012*sl t plh 0.258 0.242 + 0.008*sl 0.247 + 0.007*sl 0.253 + 0.006*sl t phl 0.261 0.243 + 0.009*sl 0.250 + 0.007*sl 0.260 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.073 0.059 + 0.007*sl 0.060 + 0.007*sl 0.050 + 0.007*sl t f 0.068 0.055 + 0.006*sl 0.058 + 0.006*sl 0.054 + 0.006*sl t plh 0.260 0.250 + 0.005*sl 0.255 + 0.003*sl 0.265 + 0.003*sl t phl 0.251 0.240 + 0.005*sl 0.246 + 0.004*sl 0.262 + 0.003*sl b to y t r 0.073 0.059 + 0.007*sl 0.061 + 0.007*sl 0.050 + 0.007*sl t f 0.068 0.056 + 0.006*sl 0.057 + 0.006*sl 0.055 + 0.006*sl t plh 0.260 0.250 + 0.005*sl 0.255 + 0.003*sl 0.266 + 0.003*sl t phl 0.277 0.266 + 0.005*sl 0.272 + 0.004*sl 0.287 + 0.003*sl c to y t r 0.073 0.059 + 0.007*sl 0.060 + 0.007*sl 0.049 + 0.007*sl t f 0.069 0.056 + 0.007*sl 0.059 + 0.006*sl 0.053 + 0.006*sl t plh 0.267 0.258 + 0.005*sl 0.262 + 0.003*sl 0.273 + 0.003*sl t phl 0.285 0.275 + 0.005*sl 0.281 + 0.004*sl 0.296 + 0.003*sl d to y t r 0.074 0.062 + 0.006*sl 0.061 + 0.007*sl 0.050 + 0.007*sl t f 0.069 0.055 + 0.007*sl 0.059 + 0.006*sl 0.053 + 0.006*sl t plh 0.279 0.269 + 0.005*sl 0.274 + 0.003*sl 0.285 + 0.003*sl t phl 0.284 0.273 + 0.005*sl 0.279 + 0.004*sl 0.294 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-161 STD111 oa2111/oa2111d2 2-or into 4-nand with 1x/2x drive logic symbol cell data input load (sl) gate count oa2111 oa2111d2 oa2111 oa2111d2 abcdeabcde 1.0 1.0 0.8 0.8 0.9 1.0 1.0 0.8 0.8 0.9 2.00 2.67 y c d a b e truth table abcdey 00xxx1 xx0xx1 xxx0x1 xxxx01 other states 0
STD111 3-162 samsung asic oa2111/oa2111d2 2-or into 4-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa2111 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.279 0.161 + 0.059*sl 0.151 + 0.062*sl 0.138 + 0.063*sl t f 0.291 0.172 + 0.059*sl 0.163 + 0.062*sl 0.150 + 0.063*sl t plh 0.150 0.096 + 0.027*sl 0.096 + 0.027*sl 0.096 + 0.027*sl t phl 0.146 0.091 + 0.028*sl 0.089 + 0.028*sl 0.088 + 0.028*sl b to y t r 0.274 0.154 + 0.060*sl 0.147 + 0.062*sl 0.140 + 0.063*sl t f 0.330 0.214 + 0.058*sl 0.203 + 0.061*sl 0.189 + 0.063*sl t plh 0.150 0.095 + 0.027*sl 0.097 + 0.027*sl 0.097 + 0.027*sl t phl 0.167 0.111 + 0.028*sl 0.110 + 0.028*sl 0.110 + 0.028*sl c to y t r 0.249 0.160 + 0.044*sl 0.153 + 0.046*sl 0.141 + 0.048*sl t f 0.328 0.207 + 0.060*sl 0.202 + 0.062*sl 0.194 + 0.062*sl t plh 0.159 0.118 + 0.021*sl 0.118 + 0.021*sl 0.118 + 0.021*sl t phl 0.188 0.130 + 0.029*sl 0.131 + 0.029*sl 0.132 + 0.028*sl d to y t r 0.271 0.182 + 0.044*sl 0.175 + 0.046*sl 0.163 + 0.048*sl t f 0.326 0.205 + 0.060*sl 0.201 + 0.062*sl 0.194 + 0.062*sl t plh 0.171 0.129 + 0.021*sl 0.130 + 0.021*sl 0.130 + 0.021*sl t phl 0.193 0.135 + 0.029*sl 0.136 + 0.029*sl 0.138 + 0.028*sl e to y t r 0.295 0.206 + 0.044*sl 0.199 + 0.046*sl 0.186 + 0.048*sl t f 0.323 0.202 + 0.061*sl 0.198 + 0.062*sl 0.193 + 0.062*sl t plh 0.180 0.138 + 0.021*sl 0.139 + 0.021*sl 0.141 + 0.021*sl t phl 0.195 0.137 + 0.029*sl 0.139 + 0.029*sl 0.141 + 0.028*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-163 STD111 oa2111/oa2111d2 2-or into 4-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa2111d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.080 0.052 + 0.014*sl 0.053 + 0.013*sl 0.041 + 0.014*sl t f 0.074 0.051 + 0.012*sl 0.053 + 0.011*sl 0.045 + 0.012*sl t plh 0.250 0.233 + 0.008*sl 0.239 + 0.007*sl 0.245 + 0.006*sl t phl 0.246 0.228 + 0.009*sl 0.235 + 0.007*sl 0.245 + 0.006*sl b to y t r 0.080 0.053 + 0.014*sl 0.053 + 0.013*sl 0.041 + 0.014*sl t f 0.075 0.049 + 0.013*sl 0.054 + 0.011*sl 0.046 + 0.012*sl t plh 0.250 0.233 + 0.008*sl 0.239 + 0.007*sl 0.245 + 0.006*sl t phl 0.276 0.258 + 0.009*sl 0.266 + 0.007*sl 0.276 + 0.006*sl c to y t r 0.080 0.054 + 0.013*sl 0.052 + 0.014*sl 0.042 + 0.014*sl t f 0.075 0.051 + 0.012*sl 0.054 + 0.011*sl 0.046 + 0.012*sl t plh 0.271 0.255 + 0.008*sl 0.261 + 0.007*sl 0.267 + 0.006*sl t phl 0.295 0.277 + 0.009*sl 0.285 + 0.007*sl 0.295 + 0.006*sl d to y t r 0.082 0.056 + 0.013*sl 0.055 + 0.013*sl 0.042 + 0.014*sl t f 0.075 0.050 + 0.012*sl 0.054 + 0.011*sl 0.046 + 0.012*sl t plh 0.283 0.267 + 0.008*sl 0.273 + 0.007*sl 0.279 + 0.006*sl t phl 0.300 0.282 + 0.009*sl 0.290 + 0.007*sl 0.300 + 0.006*sl e to y t r 0.082 0.056 + 0.013*sl 0.055 + 0.013*sl 0.043 + 0.014*sl t f 0.074 0.050 + 0.012*sl 0.054 + 0.011*sl 0.046 + 0.012*sl t plh 0.295 0.279 + 0.008*sl 0.284 + 0.007*sl 0.291 + 0.006*sl t phl 0.303 0.285 + 0.009*sl 0.293 + 0.007*sl 0.303 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-164 samsung asic oa22dh/oa22/oa22d2/oa22d2b/oa22d4 two 2-ors into 2-nand with 0.5x/1x/2x/2x(buffered)/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa22dh input load (sl) oa22dh oa22 oa22d2 oa22d2b oa22d4 abcdabcdabcdabcdabcd 0.5 0.5 0.5 0.5 0.9 1.0 0.9 1.0 1.8 1.9 1.8 1.9 0.9 1.0 1.0 1.0 0.9 1.0 1.0 1.0 gate count oa22dh oa22 oa22d2 oa22d2b oa22d4 1.67 1.67 3.00 2.67 3.00 c d y a b path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.411 0.191 + 0.110*sl 0.169 + 0.116*sl 0.158 + 0.117*sl t f 0.358 0.141 + 0.108*sl 0.127 + 0.112*sl 0.124 + 0.112*sl t plh 0.186 0.084 + 0.051*sl 0.086 + 0.050*sl 0.089 + 0.050*sl t phl 0.218 0.110 + 0.054*sl 0.111 + 0.054*sl 0.112 + 0.054*sl b to y t r 0.406 0.181 + 0.113*sl 0.167 + 0.116*sl 0.158 + 0.117*sl t f 0.398 0.182 + 0.108*sl 0.168 + 0.112*sl 0.164 + 0.112*sl t plh 0.187 0.084 + 0.052*sl 0.088 + 0.051*sl 0.091 + 0.050*sl t phl 0.242 0.134 + 0.054*sl 0.135 + 0.054*sl 0.136 + 0.054*sl c to y t r 0.460 0.240 + 0.110*sl 0.218 + 0.116*sl 0.207 + 0.117*sl t f 0.355 0.135 + 0.110*sl 0.127 + 0.112*sl 0.124 + 0.112*sl t plh 0.216 0.114 + 0.051*sl 0.117 + 0.050*sl 0.119 + 0.050*sl t phl 0.235 0.126 + 0.055*sl 0.129 + 0.054*sl 0.131 + 0.054*sl d to y t r 0.455 0.230 + 0.113*sl 0.217 + 0.116*sl 0.207 + 0.117*sl t f 0.395 0.175 + 0.110*sl 0.167 + 0.112*sl 0.164 + 0.112*sl t plh 0.218 0.115 + 0.052*sl 0.119 + 0.051*sl 0.122 + 0.050*sl t phl 0.259 0.151 + 0.054*sl 0.153 + 0.054*sl 0.155 + 0.054*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table abcdy 00xx1 xx001 other states 0
samsung asic 3-165 STD111 oa22dh/oa22/oa22d2/oa22d2b/oa22d4 two 2-ors into 2-nand with 0.5x/1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa22 oa22d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.283 0.185 + 0.049*sl 0.171 + 0.053*sl 0.152 + 0.055*sl t f 0.236 0.133 + 0.052*sl 0.126 + 0.054*sl 0.113 + 0.055*sl t plh 0.125 0.075 + 0.025*sl 0.079 + 0.024*sl 0.081 + 0.024*sl t phl 0.160 0.107 + 0.026*sl 0.107 + 0.026*sl 0.108 + 0.026*sl b to y t r 0.274 0.172 + 0.051*sl 0.161 + 0.054*sl 0.152 + 0.055*sl t f 0.275 0.173 + 0.051*sl 0.165 + 0.053*sl 0.152 + 0.055*sl t plh 0.125 0.075 + 0.025*sl 0.079 + 0.024*sl 0.082 + 0.024*sl t phl 0.182 0.130 + 0.026*sl 0.130 + 0.026*sl 0.131 + 0.026*sl c to y t r 0.315 0.216 + 0.050*sl 0.204 + 0.053*sl 0.184 + 0.055*sl t f 0.231 0.127 + 0.052*sl 0.121 + 0.054*sl 0.113 + 0.055*sl t plh 0.147 0.098 + 0.024*sl 0.100 + 0.024*sl 0.102 + 0.024*sl t phl 0.164 0.110 + 0.027*sl 0.112 + 0.026*sl 0.114 + 0.026*sl d to y t r 0.307 0.203 + 0.052*sl 0.195 + 0.054*sl 0.184 + 0.055*sl t f 0.270 0.166 + 0.052*sl 0.160 + 0.054*sl 0.153 + 0.054*sl t plh 0.147 0.098 + 0.025*sl 0.100 + 0.024*sl 0.103 + 0.024*sl t phl 0.187 0.134 + 0.027*sl 0.136 + 0.026*sl 0.137 + 0.026*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.236 0.189 + 0.024*sl 0.180 + 0.026*sl 0.158 + 0.027*sl t f 0.189 0.138 + 0.026*sl 0.132 + 0.027*sl 0.118 + 0.028*sl t plh 0.100 0.072 + 0.014*sl 0.078 + 0.012*sl 0.081 + 0.012*sl t phl 0.135 0.108 + 0.014*sl 0.109 + 0.013*sl 0.110 + 0.013*sl b to y t r 0.226 0.176 + 0.025*sl 0.169 + 0.027*sl 0.156 + 0.028*sl t f 0.228 0.177 + 0.025*sl 0.172 + 0.027*sl 0.157 + 0.028*sl t plh 0.100 0.073 + 0.013*sl 0.078 + 0.012*sl 0.082 + 0.012*sl t phl 0.158 0.131 + 0.013*sl 0.132 + 0.013*sl 0.133 + 0.013*sl c to y t r 0.265 0.218 + 0.024*sl 0.209 + 0.026*sl 0.186 + 0.027*sl t f 0.183 0.130 + 0.026*sl 0.126 + 0.027*sl 0.117 + 0.028*sl t plh 0.120 0.094 + 0.013*sl 0.097 + 0.012*sl 0.099 + 0.012*sl t phl 0.137 0.109 + 0.014*sl 0.111 + 0.013*sl 0.114 + 0.013*sl d to y t r 0.254 0.204 + 0.025*sl 0.198 + 0.027*sl 0.184 + 0.028*sl t f 0.221 0.169 + 0.026*sl 0.165 + 0.027*sl 0.157 + 0.028*sl t plh 0.120 0.094 + 0.013*sl 0.097 + 0.012*sl 0.100 + 0.012*sl t phl 0.161 0.134 + 0.014*sl 0.135 + 0.013*sl 0.138 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-166 samsung asic oa22dh/oa22/oa22d2/oa22d2b/oa22d4 two 2-ors into 2-nand with 0.5x/1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa22d2b oa22d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.081 0.056 + 0.013*sl 0.054 + 0.013*sl 0.044 + 0.014*sl t f 0.073 0.048 + 0.012*sl 0.051 + 0.011*sl 0.043 + 0.012*sl t plh 0.243 0.227 + 0.008*sl 0.232 + 0.007*sl 0.239 + 0.006*sl t phl 0.259 0.242 + 0.009*sl 0.249 + 0.007*sl 0.258 + 0.006*sl b to y t r 0.081 0.055 + 0.013*sl 0.053 + 0.013*sl 0.044 + 0.014*sl t f 0.073 0.047 + 0.013*sl 0.053 + 0.011*sl 0.044 + 0.012*sl t plh 0.244 0.227 + 0.008*sl 0.233 + 0.007*sl 0.239 + 0.006*sl t phl 0.290 0.272 + 0.009*sl 0.280 + 0.007*sl 0.289 + 0.006*sl c to y t r 0.084 0.058 + 0.013*sl 0.057 + 0.013*sl 0.044 + 0.014*sl t f 0.072 0.047 + 0.013*sl 0.051 + 0.011*sl 0.043 + 0.012*sl t plh 0.266 0.249 + 0.008*sl 0.255 + 0.007*sl 0.261 + 0.006*sl t phl 0.263 0.245 + 0.009*sl 0.253 + 0.007*sl 0.262 + 0.006*sl d to y t r 0.083 0.057 + 0.013*sl 0.056 + 0.013*sl 0.044 + 0.014*sl t f 0.073 0.048 + 0.013*sl 0.053 + 0.011*sl 0.044 + 0.012*sl t plh 0.266 0.250 + 0.008*sl 0.256 + 0.007*sl 0.262 + 0.006*sl t phl 0.291 0.273 + 0.009*sl 0.281 + 0.007*sl 0.291 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.076 0.062 + 0.007*sl 0.063 + 0.007*sl 0.051 + 0.007*sl t f 0.069 0.057 + 0.006*sl 0.058 + 0.006*sl 0.053 + 0.006*sl t plh 0.262 0.253 + 0.005*sl 0.258 + 0.004*sl 0.269 + 0.003*sl t phl 0.282 0.271 + 0.005*sl 0.277 + 0.004*sl 0.292 + 0.003*sl b to y t r 0.076 0.062 + 0.007*sl 0.063 + 0.007*sl 0.051 + 0.007*sl t f 0.070 0.058 + 0.006*sl 0.058 + 0.006*sl 0.054 + 0.006*sl t plh 0.263 0.254 + 0.005*sl 0.259 + 0.004*sl 0.270 + 0.003*sl t phl 0.313 0.302 + 0.005*sl 0.307 + 0.004*sl 0.323 + 0.003*sl c to y t r 0.077 0.064 + 0.006*sl 0.063 + 0.007*sl 0.052 + 0.007*sl t f 0.068 0.056 + 0.006*sl 0.057 + 0.006*sl 0.052 + 0.006*sl t plh 0.283 0.274 + 0.005*sl 0.279 + 0.004*sl 0.290 + 0.003*sl t phl 0.278 0.267 + 0.005*sl 0.273 + 0.004*sl 0.288 + 0.003*sl d to y t r 0.077 0.064 + 0.006*sl 0.064 + 0.007*sl 0.052 + 0.007*sl t f 0.069 0.056 + 0.007*sl 0.059 + 0.006*sl 0.055 + 0.006*sl t plh 0.285 0.275 + 0.005*sl 0.280 + 0.004*sl 0.291 + 0.003*sl t phl 0.316 0.305 + 0.005*sl 0.311 + 0.004*sl 0.326 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-167 STD111 oa22dha/oa22a/oa22d2a/oa22d4a 2-or and 2-nand into 2-nand with 0.5x/1x/2x/4x drive logic symbol cell data input load (sl) oa22dha oa22a oa22d2a oa22d4a abcdabcdabcdabcd 0.5 0.5 0.5 0.6 0.9 1.0 1.1 1.1 1.9 1.9 1.1 1.1 0.9 1.0 1.1 1.1 gate count oa22dha oa22a oa22d2a oa22d4a 2.00 2.00 2.67 3.67 c d y a b truth table abcdy 00xx1 xx111 other states 0
STD111 3-168 samsung asic oa22dha/oa22a/oa22d2a/oa22d4a 2-or and 2-nand into 2-nand with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa22dha oa22a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.349 0.127 + 0.111*sl 0.107 + 0.116*sl 0.097 + 0.117*sl t f 0.255 0.093 + 0.081*sl 0.074 + 0.086*sl 0.062 + 0.087*sl t plh 0.177 0.078 + 0.050*sl 0.077 + 0.050*sl 0.076 + 0.050*sl t phl 0.159 0.075 + 0.042*sl 0.075 + 0.042*sl 0.074 + 0.042*sl b to y t r 0.344 0.118 + 0.113*sl 0.106 + 0.116*sl 0.097 + 0.117*sl t f 0.289 0.127 + 0.081*sl 0.107 + 0.086*sl 0.094 + 0.088*sl t plh 0.178 0.077 + 0.050*sl 0.078 + 0.050*sl 0.077 + 0.050*sl t phl 0.177 0.093 + 0.042*sl 0.093 + 0.042*sl 0.093 + 0.042*sl c to y t r 0.237 0.122 + 0.058*sl 0.111 + 0.061*sl 0.103 + 0.061*sl t f 0.273 0.100 + 0.087*sl 0.097 + 0.087*sl 0.094 + 0.088*sl t plh 0.194 0.138 + 0.028*sl 0.142 + 0.027*sl 0.145 + 0.027*sl t phl 0.246 0.160 + 0.043*sl 0.163 + 0.043*sl 0.165 + 0.042*sl d to y t r 0.237 0.121 + 0.058*sl 0.111 + 0.061*sl 0.103 + 0.061*sl t f 0.274 0.102 + 0.086*sl 0.098 + 0.087*sl 0.095 + 0.088*sl t plh 0.190 0.133 + 0.028*sl 0.138 + 0.027*sl 0.141 + 0.027*sl t phl 0.259 0.172 + 0.043*sl 0.175 + 0.042*sl 0.177 + 0.042*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.222 0.122 + 0.050*sl 0.109 + 0.053*sl 0.092 + 0.055*sl t f 0.166 0.091 + 0.038*sl 0.080 + 0.041*sl 0.063 + 0.042*sl t plh 0.117 0.068 + 0.025*sl 0.072 + 0.023*sl 0.070 + 0.024*sl t phl 0.111 0.067 + 0.022*sl 0.072 + 0.021*sl 0.071 + 0.021*sl b to y t r 0.213 0.110 + 0.052*sl 0.101 + 0.054*sl 0.092 + 0.055*sl t f 0.200 0.124 + 0.038*sl 0.113 + 0.041*sl 0.096 + 0.043*sl t plh 0.117 0.067 + 0.025*sl 0.071 + 0.024*sl 0.071 + 0.024*sl t phl 0.130 0.088 + 0.021*sl 0.090 + 0.021*sl 0.089 + 0.021*sl c to y t r 0.133 0.079 + 0.027*sl 0.076 + 0.028*sl 0.070 + 0.028*sl t f 0.178 0.094 + 0.042*sl 0.091 + 0.043*sl 0.088 + 0.043*sl t plh 0.152 0.125 + 0.014*sl 0.129 + 0.013*sl 0.130 + 0.012*sl t phl 0.188 0.145 + 0.022*sl 0.147 + 0.021*sl 0.150 + 0.021*sl d to y t r 0.133 0.079 + 0.027*sl 0.075 + 0.028*sl 0.070 + 0.028*sl t f 0.178 0.094 + 0.042*sl 0.092 + 0.043*sl 0.089 + 0.043*sl t plh 0.147 0.120 + 0.014*sl 0.124 + 0.013*sl 0.126 + 0.012*sl t phl 0.201 0.157 + 0.022*sl 0.160 + 0.021*sl 0.162 + 0.021*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-169 STD111 oa22dha/oa22a/oa22d2a/oa22d4a 2-or and 2-nand into 2-nand with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa22d2a oa22d4a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.172 0.124 + 0.024*sl 0.115 + 0.026*sl 0.094 + 0.028*sl t f 0.128 0.093 + 0.018*sl 0.084 + 0.020*sl 0.066 + 0.021*sl t plh 0.092 0.065 + 0.014*sl 0.072 + 0.012*sl 0.071 + 0.012*sl t phl 0.088 0.063 + 0.013*sl 0.071 + 0.010*sl 0.071 + 0.010*sl b to y t r 0.163 0.114 + 0.025*sl 0.105 + 0.027*sl 0.092 + 0.028*sl t f 0.164 0.129 + 0.018*sl 0.120 + 0.020*sl 0.099 + 0.022*sl t plh 0.092 0.065 + 0.013*sl 0.070 + 0.012*sl 0.071 + 0.012*sl t phl 0.109 0.087 + 0.011*sl 0.090 + 0.010*sl 0.090 + 0.010*sl c to y t r 0.113 0.087 + 0.013*sl 0.085 + 0.014*sl 0.078 + 0.014*sl t f 0.138 0.096 + 0.021*sl 0.094 + 0.022*sl 0.090 + 0.022*sl t plh 0.167 0.152 + 0.008*sl 0.155 + 0.007*sl 0.161 + 0.006*sl t phl 0.181 0.158 + 0.011*sl 0.160 + 0.011*sl 0.163 + 0.011*sl d to y t r 0.113 0.086 + 0.013*sl 0.086 + 0.014*sl 0.078 + 0.014*sl t f 0.140 0.098 + 0.021*sl 0.096 + 0.021*sl 0.090 + 0.022*sl t plh 0.161 0.145 + 0.008*sl 0.149 + 0.007*sl 0.155 + 0.006*sl t phl 0.191 0.168 + 0.011*sl 0.170 + 0.011*sl 0.173 + 0.011*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.073 0.061 + 0.006*sl 0.059 + 0.007*sl 0.049 + 0.007*sl t f 0.066 0.053 + 0.006*sl 0.055 + 0.006*sl 0.052 + 0.006*sl t plh 0.243 0.234 + 0.005*sl 0.238 + 0.003*sl 0.249 + 0.003*sl t phl 0.229 0.218 + 0.005*sl 0.223 + 0.004*sl 0.239 + 0.003*sl b to y t r 0.073 0.059 + 0.007*sl 0.060 + 0.007*sl 0.050 + 0.007*sl t f 0.067 0.053 + 0.007*sl 0.057 + 0.006*sl 0.052 + 0.006*sl t plh 0.244 0.234 + 0.005*sl 0.239 + 0.003*sl 0.249 + 0.003*sl t phl 0.254 0.243 + 0.005*sl 0.249 + 0.004*sl 0.264 + 0.003*sl c to y t r 0.072 0.059 + 0.007*sl 0.058 + 0.007*sl 0.048 + 0.007*sl t f 0.067 0.054 + 0.006*sl 0.056 + 0.006*sl 0.053 + 0.006*sl t plh 0.283 0.274 + 0.005*sl 0.279 + 0.003*sl 0.289 + 0.003*sl t phl 0.311 0.301 + 0.005*sl 0.306 + 0.004*sl 0.321 + 0.003*sl d to y t r 0.072 0.058 + 0.007*sl 0.058 + 0.007*sl 0.048 + 0.007*sl t f 0.068 0.055 + 0.006*sl 0.057 + 0.006*sl 0.052 + 0.006*sl t plh 0.278 0.269 + 0.005*sl 0.274 + 0.003*sl 0.284 + 0.003*sl t phl 0.324 0.313 + 0.005*sl 0.319 + 0.004*sl 0.334 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-170 samsung asic oa221/oa221d2/oa221d4 two 2-ors into 3-nand with 1x/2x/4x drive logic symbol cell data input load (sl) oa221 oa221d2 oa221d4 abcdeabcdeabcde 1.0 1.0 1.0 1.1 1.0 1.0 1.0 1.0 1.1 1.0 1.0 1.0 1.0 1.1 1.0 gate count oa221 oa221d2 oa221d4 2.00 3.00 3.67 c d y a b e truth table abcdey 00xxx1 xx00x1 xxxx01 other states 0
samsung asic 3-171 STD111 oa221/oa221d2/oa221d4 two 2-ors into 3-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa221 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.317 0.215 + 0.051*sl 0.205 + 0.054*sl 0.189 + 0.055*sl t f 0.286 0.177 + 0.054*sl 0.171 + 0.056*sl 0.161 + 0.057*sl t plh 0.141 0.092 + 0.025*sl 0.093 + 0.024*sl 0.096 + 0.024*sl t phl 0.173 0.120 + 0.026*sl 0.121 + 0.026*sl 0.121 + 0.026*sl b to y t r 0.310 0.205 + 0.052*sl 0.198 + 0.054*sl 0.188 + 0.055*sl t f 0.333 0.224 + 0.054*sl 0.217 + 0.056*sl 0.206 + 0.057*sl t plh 0.144 0.094 + 0.025*sl 0.096 + 0.024*sl 0.100 + 0.024*sl t phl 0.200 0.147 + 0.027*sl 0.148 + 0.027*sl 0.148 + 0.026*sl c to y t r 0.351 0.250 + 0.051*sl 0.239 + 0.054*sl 0.223 + 0.055*sl t f 0.280 0.173 + 0.054*sl 0.168 + 0.055*sl 0.161 + 0.056*sl t plh 0.164 0.115 + 0.024*sl 0.116 + 0.024*sl 0.118 + 0.024*sl t phl 0.182 0.129 + 0.026*sl 0.130 + 0.026*sl 0.132 + 0.026*sl d to y t r 0.345 0.240 + 0.052*sl 0.233 + 0.054*sl 0.223 + 0.055*sl t f 0.330 0.219 + 0.056*sl 0.215 + 0.057*sl 0.208 + 0.057*sl t plh 0.166 0.117 + 0.025*sl 0.118 + 0.024*sl 0.121 + 0.024*sl t phl 0.213 0.159 + 0.027*sl 0.160 + 0.027*sl 0.162 + 0.027*sl e to y t r 0.283 0.228 + 0.027*sl 0.219 + 0.030*sl 0.200 + 0.032*sl t f 0.327 0.214 + 0.056*sl 0.212 + 0.057*sl 0.207 + 0.057*sl t plh 0.133 0.103 + 0.015*sl 0.104 + 0.015*sl 0.107 + 0.014*sl t phl 0.213 0.159 + 0.027*sl 0.161 + 0.027*sl 0.163 + 0.027*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-172 samsung asic oa221/oa221d2/oa221d4 two 2-ors into 3-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa221d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.084 0.058 + 0.013*sl 0.057 + 0.013*sl 0.045 + 0.014*sl t f 0.075 0.052 + 0.012*sl 0.053 + 0.011*sl 0.045 + 0.012*sl t plh 0.262 0.245 + 0.008*sl 0.251 + 0.007*sl 0.258 + 0.006*sl t phl 0.283 0.265 + 0.009*sl 0.273 + 0.007*sl 0.283 + 0.006*sl b to y t r 0.084 0.058 + 0.013*sl 0.058 + 0.013*sl 0.045 + 0.014*sl t f 0.076 0.051 + 0.012*sl 0.055 + 0.011*sl 0.047 + 0.012*sl t plh 0.265 0.248 + 0.008*sl 0.254 + 0.007*sl 0.260 + 0.006*sl t phl 0.317 0.300 + 0.009*sl 0.307 + 0.007*sl 0.317 + 0.006*sl c to y t r 0.085 0.059 + 0.013*sl 0.058 + 0.013*sl 0.046 + 0.014*sl t f 0.074 0.048 + 0.013*sl 0.054 + 0.011*sl 0.045 + 0.012*sl t plh 0.289 0.273 + 0.008*sl 0.279 + 0.007*sl 0.286 + 0.006*sl t phl 0.291 0.273 + 0.009*sl 0.281 + 0.007*sl 0.291 + 0.006*sl d to y t r 0.085 0.059 + 0.013*sl 0.059 + 0.013*sl 0.045 + 0.014*sl t f 0.076 0.053 + 0.012*sl 0.055 + 0.011*sl 0.047 + 0.012*sl t plh 0.291 0.275 + 0.008*sl 0.281 + 0.007*sl 0.287 + 0.006*sl t phl 0.329 0.311 + 0.009*sl 0.319 + 0.007*sl 0.329 + 0.006*sl e to y t r 0.082 0.056 + 0.013*sl 0.054 + 0.013*sl 0.044 + 0.014*sl t f 0.077 0.053 + 0.012*sl 0.055 + 0.011*sl 0.047 + 0.012*sl t plh 0.261 0.245 + 0.008*sl 0.250 + 0.007*sl 0.256 + 0.006*sl t phl 0.330 0.312 + 0.009*sl 0.319 + 0.007*sl 0.329 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-173 STD111 oa221/oa221d2/oa221d4 two 2-ors into 3-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa221d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.079 0.065 + 0.007*sl 0.066 + 0.007*sl 0.053 + 0.007*sl t f 0.071 0.058 + 0.007*sl 0.061 + 0.006*sl 0.055 + 0.006*sl t plh 0.285 0.275 + 0.005*sl 0.280 + 0.004*sl 0.291 + 0.003*sl t phl 0.309 0.298 + 0.005*sl 0.304 + 0.004*sl 0.320 + 0.003*sl b to y t r 0.079 0.066 + 0.006*sl 0.065 + 0.007*sl 0.053 + 0.007*sl t f 0.073 0.061 + 0.006*sl 0.062 + 0.006*sl 0.058 + 0.006*sl t plh 0.288 0.278 + 0.005*sl 0.283 + 0.004*sl 0.294 + 0.003*sl t phl 0.345 0.334 + 0.005*sl 0.340 + 0.004*sl 0.356 + 0.003*sl c to y t r 0.080 0.067 + 0.006*sl 0.067 + 0.006*sl 0.054 + 0.007*sl t f 0.070 0.057 + 0.007*sl 0.060 + 0.006*sl 0.057 + 0.006*sl t plh 0.314 0.304 + 0.005*sl 0.309 + 0.004*sl 0.320 + 0.003*sl t phl 0.319 0.308 + 0.005*sl 0.314 + 0.004*sl 0.330 + 0.003*sl d to y t r 0.080 0.067 + 0.006*sl 0.067 + 0.006*sl 0.054 + 0.007*sl t f 0.073 0.060 + 0.006*sl 0.063 + 0.006*sl 0.056 + 0.006*sl t plh 0.314 0.305 + 0.005*sl 0.310 + 0.004*sl 0.321 + 0.003*sl t phl 0.356 0.346 + 0.005*sl 0.351 + 0.004*sl 0.367 + 0.003*sl e to y t r 0.077 0.064 + 0.006*sl 0.063 + 0.007*sl 0.051 + 0.007*sl t f 0.073 0.061 + 0.006*sl 0.062 + 0.006*sl 0.057 + 0.006*sl t plh 0.279 0.269 + 0.005*sl 0.274 + 0.003*sl 0.284 + 0.003*sl t phl 0.358 0.348 + 0.005*sl 0.353 + 0.004*sl 0.369 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-174 samsung asic oa222/oa222d2/oa222d2b/oa222d4 three 2-ors into 3-nand with 1x/2x/2x(buffered)/4x drive logic symbol cell data input load (sl) gate count oa222 oa222d2 oa222 oa222d2 abcdefabcdef 0.9 1.0 0.9 1.0 0.9 1.0 1.8 2.0 1.8 2.0 1.8 2.0 2.67 4.33 oa222d2b oa222d4 oa222d2b oa222d4 abcdefabcdef 0.9 1.0 0.9 1.0 0.9 1.0 0.9 1.0 0.9 1.0 0.9 1.0 3.33 4.00 c d y a b e f truth table abcdefy 00xxxx1 xx00xx1 xxxx001 other states 0
samsung asic 3-175 STD111 oa222/oa222d2/oa222d2b/oa222d4 three 2-ors into 3-nand with 1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa222 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.374 0.273 + 0.050*sl 0.263 + 0.053*sl 0.246 + 0.055*sl t f 0.398 0.260 + 0.069*sl 0.255 + 0.071*sl 0.252 + 0.071*sl t plh 0.152 0.102 + 0.025*sl 0.104 + 0.024*sl 0.108 + 0.024*sl t phl 0.243 0.176 + 0.033*sl 0.178 + 0.033*sl 0.179 + 0.033*sl b to y t r 0.367 0.263 + 0.052*sl 0.256 + 0.054*sl 0.246 + 0.055*sl t f 0.447 0.309 + 0.069*sl 0.304 + 0.070*sl 0.301 + 0.070*sl t plh 0.153 0.103 + 0.025*sl 0.105 + 0.024*sl 0.110 + 0.024*sl t phl 0.272 0.206 + 0.033*sl 0.207 + 0.033*sl 0.208 + 0.032*sl c to y t r 0.411 0.310 + 0.050*sl 0.299 + 0.053*sl 0.282 + 0.055*sl t f 0.401 0.262 + 0.070*sl 0.258 + 0.071*sl 0.255 + 0.071*sl t plh 0.176 0.126 + 0.025*sl 0.128 + 0.024*sl 0.132 + 0.024*sl t phl 0.264 0.197 + 0.034*sl 0.199 + 0.033*sl 0.202 + 0.033*sl d to y t r 0.403 0.299 + 0.052*sl 0.292 + 0.054*sl 0.282 + 0.055*sl t f 0.448 0.309 + 0.069*sl 0.306 + 0.070*sl 0.302 + 0.070*sl t plh 0.177 0.127 + 0.025*sl 0.129 + 0.024*sl 0.134 + 0.024*sl t phl 0.294 0.228 + 0.033*sl 0.229 + 0.033*sl 0.231 + 0.033*sl e to y t r 0.441 0.341 + 0.050*sl 0.330 + 0.053*sl 0.312 + 0.055*sl t f 0.396 0.258 + 0.069*sl 0.254 + 0.070*sl 0.252 + 0.070*sl t plh 0.191 0.142 + 0.025*sl 0.144 + 0.024*sl 0.148 + 0.024*sl t phl 0.269 0.201 + 0.034*sl 0.204 + 0.033*sl 0.207 + 0.033*sl f to y t r 0.434 0.330 + 0.052*sl 0.323 + 0.054*sl 0.312 + 0.055*sl t f 0.446 0.307 + 0.070*sl 0.305 + 0.070*sl 0.302 + 0.070*sl t plh 0.193 0.143 + 0.025*sl 0.145 + 0.024*sl 0.150 + 0.024*sl t phl 0.300 0.234 + 0.033*sl 0.236 + 0.033*sl 0.238 + 0.033*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-176 samsung asic oa222/oa222d2/oa222d2b/oa222d4 three 2-ors into 3-nand with 1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa222d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.318 0.269 + 0.024*sl 0.263 + 0.026*sl 0.242 + 0.027*sl t f 0.319 0.250 + 0.034*sl 0.247 + 0.035*sl 0.240 + 0.036*sl t plh 0.123 0.097 + 0.013*sl 0.099 + 0.012*sl 0.104 + 0.012*sl t phl 0.205 0.171 + 0.017*sl 0.172 + 0.016*sl 0.174 + 0.016*sl b to y t r 0.309 0.257 + 0.026*sl 0.253 + 0.027*sl 0.240 + 0.028*sl t f 0.367 0.298 + 0.034*sl 0.297 + 0.035*sl 0.290 + 0.035*sl t plh 0.125 0.098 + 0.013*sl 0.101 + 0.012*sl 0.107 + 0.012*sl t phl 0.235 0.202 + 0.017*sl 0.203 + 0.016*sl 0.204 + 0.016*sl c to y t r 0.351 0.302 + 0.025*sl 0.295 + 0.026*sl 0.275 + 0.028*sl t f 0.322 0.253 + 0.035*sl 0.250 + 0.035*sl 0.244 + 0.036*sl t plh 0.145 0.121 + 0.012*sl 0.122 + 0.012*sl 0.126 + 0.012*sl t phl 0.222 0.188 + 0.017*sl 0.190 + 0.017*sl 0.193 + 0.016*sl d to y t r 0.342 0.291 + 0.025*sl 0.286 + 0.027*sl 0.274 + 0.028*sl t f 0.368 0.298 + 0.035*sl 0.297 + 0.035*sl 0.291 + 0.035*sl t plh 0.147 0.122 + 0.013*sl 0.123 + 0.012*sl 0.127 + 0.012*sl t phl 0.252 0.219 + 0.017*sl 0.220 + 0.016*sl 0.223 + 0.016*sl e to y t r 0.382 0.334 + 0.024*sl 0.327 + 0.026*sl 0.305 + 0.027*sl t f 0.316 0.247 + 0.034*sl 0.245 + 0.035*sl 0.241 + 0.035*sl t plh 0.161 0.136 + 0.013*sl 0.137 + 0.012*sl 0.142 + 0.012*sl t phl 0.227 0.193 + 0.017*sl 0.195 + 0.017*sl 0.199 + 0.016*sl f to y t r 0.373 0.322 + 0.025*sl 0.317 + 0.027*sl 0.304 + 0.028*sl t f 0.366 0.296 + 0.035*sl 0.295 + 0.035*sl 0.291 + 0.035*sl t plh 0.163 0.138 + 0.013*sl 0.139 + 0.012*sl 0.144 + 0.012*sl t phl 0.260 0.226 + 0.017*sl 0.227 + 0.016*sl 0.230 + 0.016*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-177 STD111 oa222/oa222d2/oa222d2b/oa222d4 three 2-ors into 3-nand with 1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa222d2b path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.087 0.061 + 0.013*sl 0.060 + 0.013*sl 0.047 + 0.014*sl t f 0.078 0.053 + 0.012*sl 0.057 + 0.011*sl 0.048 + 0.012*sl t plh 0.283 0.266 + 0.008*sl 0.273 + 0.007*sl 0.279 + 0.006*sl t phl 0.359 0.341 + 0.009*sl 0.349 + 0.007*sl 0.360 + 0.006*sl b to y t r 0.087 0.061 + 0.013*sl 0.060 + 0.013*sl 0.047 + 0.014*sl t f 0.079 0.055 + 0.012*sl 0.058 + 0.011*sl 0.050 + 0.012*sl t plh 0.285 0.268 + 0.008*sl 0.274 + 0.007*sl 0.281 + 0.006*sl t phl 0.398 0.380 + 0.009*sl 0.388 + 0.007*sl 0.399 + 0.006*sl c to y t r 0.088 0.063 + 0.012*sl 0.060 + 0.013*sl 0.048 + 0.014*sl t f 0.078 0.056 + 0.011*sl 0.057 + 0.011*sl 0.048 + 0.012*sl t plh 0.311 0.294 + 0.008*sl 0.300 + 0.007*sl 0.307 + 0.006*sl t phl 0.380 0.362 + 0.009*sl 0.370 + 0.007*sl 0.381 + 0.006*sl d to y t r 0.088 0.062 + 0.013*sl 0.062 + 0.013*sl 0.047 + 0.014*sl t f 0.079 0.055 + 0.012*sl 0.059 + 0.011*sl 0.050 + 0.012*sl t plh 0.312 0.296 + 0.008*sl 0.302 + 0.007*sl 0.309 + 0.006*sl t phl 0.419 0.401 + 0.009*sl 0.408 + 0.007*sl 0.419 + 0.006*sl e to y t r 0.090 0.064 + 0.013*sl 0.063 + 0.013*sl 0.049 + 0.014*sl t f 0.078 0.056 + 0.011*sl 0.056 + 0.011*sl 0.048 + 0.012*sl t plh 0.329 0.313 + 0.008*sl 0.319 + 0.007*sl 0.326 + 0.006*sl t phl 0.384 0.366 + 0.009*sl 0.373 + 0.007*sl 0.384 + 0.006*sl f to y t r 0.090 0.064 + 0.013*sl 0.063 + 0.013*sl 0.049 + 0.014*sl t f 0.080 0.057 + 0.012*sl 0.059 + 0.011*sl 0.050 + 0.012*sl t plh 0.330 0.314 + 0.008*sl 0.320 + 0.007*sl 0.327 + 0.006*sl t phl 0.424 0.406 + 0.009*sl 0.413 + 0.007*sl 0.424 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-178 samsung asic oa222/oa222d2/oa222d2b/oa222d4 three 2-ors into 3-nand with 1x/2x/2x(buffered)/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa222d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.082 0.069 + 0.006*sl 0.068 + 0.006*sl 0.056 + 0.007*sl t f 0.076 0.064 + 0.006*sl 0.065 + 0.006*sl 0.060 + 0.006*sl t plh 0.304 0.294 + 0.005*sl 0.299 + 0.004*sl 0.311 + 0.003*sl t phl 0.386 0.375 + 0.005*sl 0.381 + 0.004*sl 0.397 + 0.003*sl b to y t r 0.082 0.069 + 0.006*sl 0.069 + 0.006*sl 0.055 + 0.007*sl t f 0.077 0.065 + 0.006*sl 0.067 + 0.006*sl 0.061 + 0.006*sl t plh 0.305 0.296 + 0.005*sl 0.301 + 0.004*sl 0.313 + 0.003*sl t phl 0.425 0.414 + 0.005*sl 0.420 + 0.004*sl 0.436 + 0.003*sl c to y t r 0.083 0.069 + 0.007*sl 0.070 + 0.006*sl 0.057 + 0.007*sl t f 0.076 0.064 + 0.006*sl 0.065 + 0.006*sl 0.060 + 0.006*sl t plh 0.332 0.322 + 0.005*sl 0.327 + 0.004*sl 0.339 + 0.003*sl t phl 0.407 0.396 + 0.005*sl 0.402 + 0.004*sl 0.418 + 0.003*sl d to y t r 0.084 0.070 + 0.007*sl 0.071 + 0.006*sl 0.057 + 0.007*sl t f 0.077 0.065 + 0.006*sl 0.067 + 0.006*sl 0.061 + 0.006*sl t plh 0.333 0.323 + 0.005*sl 0.328 + 0.004*sl 0.340 + 0.003*sl t phl 0.446 0.435 + 0.005*sl 0.440 + 0.004*sl 0.457 + 0.003*sl e to y t r 0.085 0.072 + 0.006*sl 0.072 + 0.006*sl 0.058 + 0.007*sl t f 0.075 0.063 + 0.006*sl 0.064 + 0.006*sl 0.060 + 0.006*sl t plh 0.350 0.340 + 0.005*sl 0.346 + 0.004*sl 0.358 + 0.003*sl t phl 0.410 0.400 + 0.005*sl 0.406 + 0.004*sl 0.422 + 0.003*sl f to y t r 0.084 0.071 + 0.007*sl 0.072 + 0.006*sl 0.058 + 0.007*sl t f 0.077 0.065 + 0.006*sl 0.066 + 0.006*sl 0.061 + 0.006*sl t plh 0.352 0.342 + 0.005*sl 0.347 + 0.004*sl 0.359 + 0.003*sl t phl 0.451 0.440 + 0.005*sl 0.446 + 0.004*sl 0.462 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-179 STD111 oa2222/oa2222d2/oa2222d4 four 2-ors into 4-nand with 1x/2x/4x drive logic symbol cell data input load (sl) gate count oa2222 oa2222 abcdefgh 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 3.33 oa2222d2 oa2222d2 abcdefgh 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 4.00 oa2222d4 oa2222d4 abcdefgh 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 4.67 e f y c d g h a b truth table abcdefghy 00xxxxxx1 xx00xxxx1 xxxx00xx1 xxxxxx001 other states 0
STD111 3-180 samsung asic oa2222/oa2222d2/oa2222d4 four 2-ors into 4-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa2222 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.446 0.344 + 0.051*sl 0.334 + 0.053*sl 0.318 + 0.055*sl t f 0.420 0.283 + 0.069*sl 0.278 + 0.070*sl 0.275 + 0.070*sl t plh 0.172 0.122 + 0.025*sl 0.125 + 0.024*sl 0.129 + 0.024*sl t phl 0.240 0.176 + 0.032*sl 0.177 + 0.032*sl 0.178 + 0.032*sl b to y t r 0.439 0.335 + 0.052*sl 0.328 + 0.054*sl 0.318 + 0.055*sl t f 0.469 0.332 + 0.069*sl 0.327 + 0.070*sl 0.324 + 0.070*sl t plh 0.174 0.123 + 0.025*sl 0.126 + 0.024*sl 0.131 + 0.024*sl t phl 0.270 0.206 + 0.032*sl 0.207 + 0.032*sl 0.208 + 0.032*sl c to y t r 0.483 0.381 + 0.051*sl 0.371 + 0.054*sl 0.356 + 0.055*sl t f 0.422 0.285 + 0.069*sl 0.281 + 0.070*sl 0.277 + 0.070*sl t plh 0.200 0.150 + 0.025*sl 0.152 + 0.024*sl 0.156 + 0.024*sl t phl 0.266 0.200 + 0.033*sl 0.203 + 0.032*sl 0.205 + 0.032*sl d to y t r 0.477 0.372 + 0.052*sl 0.366 + 0.054*sl 0.357 + 0.055*sl t f 0.472 0.335 + 0.069*sl 0.332 + 0.070*sl 0.328 + 0.070*sl t plh 0.202 0.152 + 0.025*sl 0.154 + 0.024*sl 0.158 + 0.024*sl t phl 0.297 0.232 + 0.033*sl 0.234 + 0.032*sl 0.236 + 0.032*sl e to y t r 0.521 0.420 + 0.050*sl 0.409 + 0.053*sl 0.393 + 0.055*sl t f 0.423 0.285 + 0.069*sl 0.281 + 0.070*sl 0.279 + 0.070*sl t plh 0.220 0.171 + 0.025*sl 0.172 + 0.024*sl 0.176 + 0.024*sl t phl 0.280 0.214 + 0.033*sl 0.216 + 0.032*sl 0.219 + 0.032*sl f to y t r 0.516 0.411 + 0.052*sl 0.404 + 0.054*sl 0.394 + 0.055*sl t f 0.471 0.333 + 0.069*sl 0.330 + 0.070*sl 0.328 + 0.070*sl t plh 0.222 0.172 + 0.025*sl 0.174 + 0.024*sl 0.178 + 0.024*sl t phl 0.311 0.246 + 0.033*sl 0.247 + 0.032*sl 0.250 + 0.032*sl g to y t r 0.562 0.460 + 0.051*sl 0.449 + 0.054*sl 0.433 + 0.056*sl t f 0.538 0.381 + 0.079*sl 0.380 + 0.079*sl 0.378 + 0.079*sl t plh 0.239 0.188 + 0.025*sl 0.190 + 0.025*sl 0.195 + 0.024*sl t phl 0.367 0.293 + 0.037*sl 0.295 + 0.036*sl 0.299 + 0.036*sl h to y t r 0.556 0.451 + 0.053*sl 0.444 + 0.054*sl 0.434 + 0.056*sl t f 0.600 0.440 + 0.080*sl 0.440 + 0.080*sl 0.439 + 0.080*sl t plh 0.241 0.190 + 0.025*sl 0.193 + 0.025*sl 0.197 + 0.024*sl t phl 0.405 0.331 + 0.037*sl 0.333 + 0.036*sl 0.335 + 0.036*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-181 STD111 oa2222/oa2222d2/oa2222d4 four 2-ors into 4-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa2222d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.089 0.063 + 0.013*sl 0.063 + 0.013*sl 0.048 + 0.014*sl t f 0.079 0.056 + 0.011*sl 0.057 + 0.011*sl 0.049 + 0.012*sl t plh 0.311 0.294 + 0.008*sl 0.301 + 0.007*sl 0.307 + 0.006*sl t phl 0.364 0.346 + 0.009*sl 0.353 + 0.007*sl 0.364 + 0.006*sl b to y t r 0.090 0.066 + 0.012*sl 0.061 + 0.013*sl 0.048 + 0.014*sl t f 0.081 0.056 + 0.012*sl 0.060 + 0.011*sl 0.049 + 0.012*sl t plh 0.311 0.294 + 0.008*sl 0.301 + 0.007*sl 0.308 + 0.006*sl t phl 0.401 0.383 + 0.009*sl 0.391 + 0.007*sl 0.402 + 0.006*sl c to y t r 0.091 0.066 + 0.013*sl 0.063 + 0.013*sl 0.049 + 0.014*sl t f 0.079 0.055 + 0.012*sl 0.058 + 0.011*sl 0.049 + 0.012*sl t plh 0.342 0.325 + 0.008*sl 0.332 + 0.007*sl 0.339 + 0.006*sl t phl 0.389 0.371 + 0.009*sl 0.378 + 0.007*sl 0.389 + 0.006*sl d to y t r 0.090 0.066 + 0.012*sl 0.062 + 0.013*sl 0.049 + 0.014*sl t f 0.081 0.058 + 0.011*sl 0.059 + 0.011*sl 0.050 + 0.012*sl t plh 0.343 0.326 + 0.008*sl 0.333 + 0.007*sl 0.340 + 0.006*sl t phl 0.428 0.410 + 0.009*sl 0.417 + 0.007*sl 0.428 + 0.006*sl e to y t r 0.093 0.067 + 0.013*sl 0.066 + 0.013*sl 0.051 + 0.014*sl t f 0.079 0.056 + 0.012*sl 0.057 + 0.011*sl 0.049 + 0.012*sl t plh 0.365 0.348 + 0.008*sl 0.355 + 0.007*sl 0.362 + 0.006*sl t phl 0.403 0.384 + 0.009*sl 0.392 + 0.007*sl 0.403 + 0.006*sl f to y t r 0.092 0.068 + 0.012*sl 0.065 + 0.013*sl 0.051 + 0.014*sl t f 0.081 0.056 + 0.012*sl 0.060 + 0.011*sl 0.049 + 0.012*sl t plh 0.366 0.349 + 0.009*sl 0.356 + 0.007*sl 0.363 + 0.006*sl t phl 0.441 0.423 + 0.009*sl 0.431 + 0.007*sl 0.442 + 0.006*sl g to y t r 0.094 0.068 + 0.013*sl 0.069 + 0.013*sl 0.052 + 0.014*sl t f 0.083 0.059 + 0.012*sl 0.063 + 0.011*sl 0.051 + 0.012*sl t plh 0.386 0.369 + 0.009*sl 0.376 + 0.007*sl 0.383 + 0.006*sl t phl 0.500 0.482 + 0.009*sl 0.490 + 0.007*sl 0.501 + 0.006*sl h to y t r 0.094 0.069 + 0.013*sl 0.068 + 0.013*sl 0.052 + 0.014*sl t f 0.087 0.063 + 0.012*sl 0.066 + 0.011*sl 0.054 + 0.012*sl t plh 0.388 0.371 + 0.009*sl 0.378 + 0.007*sl 0.385 + 0.006*sl t phl 0.547 0.529 + 0.009*sl 0.536 + 0.007*sl 0.548 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-182 samsung asic oa2222/oa2222d2/oa2222d4 four 2-ors into 4-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa2222d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.085 0.074 + 0.006*sl 0.072 + 0.006*sl 0.059 + 0.007*sl t f 0.076 0.064 + 0.006*sl 0.066 + 0.006*sl 0.061 + 0.006*sl t plh 0.334 0.323 + 0.005*sl 0.329 + 0.004*sl 0.341 + 0.003*sl t phl 0.391 0.380 + 0.005*sl 0.386 + 0.004*sl 0.402 + 0.003*sl b to y t r 0.085 0.073 + 0.006*sl 0.072 + 0.006*sl 0.059 + 0.007*sl t f 0.079 0.067 + 0.006*sl 0.068 + 0.006*sl 0.063 + 0.006*sl t plh 0.334 0.324 + 0.005*sl 0.330 + 0.004*sl 0.342 + 0.003*sl t phl 0.428 0.418 + 0.005*sl 0.423 + 0.004*sl 0.440 + 0.003*sl c to y t r 0.088 0.077 + 0.006*sl 0.074 + 0.006*sl 0.060 + 0.007*sl t f 0.077 0.064 + 0.006*sl 0.066 + 0.006*sl 0.060 + 0.006*sl t plh 0.365 0.355 + 0.005*sl 0.360 + 0.004*sl 0.373 + 0.003*sl t phl 0.416 0.405 + 0.005*sl 0.411 + 0.004*sl 0.427 + 0.003*sl d to y t r 0.088 0.076 + 0.006*sl 0.074 + 0.006*sl 0.060 + 0.007*sl t f 0.078 0.067 + 0.006*sl 0.067 + 0.006*sl 0.062 + 0.006*sl t plh 0.366 0.356 + 0.005*sl 0.362 + 0.004*sl 0.374 + 0.003*sl t phl 0.455 0.444 + 0.005*sl 0.450 + 0.004*sl 0.467 + 0.003*sl e to y t r 0.089 0.078 + 0.006*sl 0.075 + 0.006*sl 0.061 + 0.007*sl t f 0.077 0.065 + 0.006*sl 0.066 + 0.006*sl 0.061 + 0.006*sl t plh 0.388 0.378 + 0.005*sl 0.384 + 0.004*sl 0.396 + 0.003*sl t phl 0.429 0.419 + 0.005*sl 0.425 + 0.004*sl 0.441 + 0.003*sl f to y t r 0.089 0.078 + 0.006*sl 0.075 + 0.006*sl 0.061 + 0.007*sl t f 0.079 0.067 + 0.006*sl 0.068 + 0.006*sl 0.063 + 0.006*sl t plh 0.389 0.379 + 0.005*sl 0.385 + 0.004*sl 0.398 + 0.003*sl t phl 0.469 0.458 + 0.005*sl 0.464 + 0.004*sl 0.480 + 0.003*sl g to y t r 0.091 0.080 + 0.006*sl 0.077 + 0.006*sl 0.063 + 0.007*sl t f 0.082 0.070 + 0.006*sl 0.071 + 0.006*sl 0.065 + 0.006*sl t plh 0.409 0.399 + 0.005*sl 0.405 + 0.004*sl 0.418 + 0.003*sl t phl 0.530 0.519 + 0.006*sl 0.525 + 0.004*sl 0.542 + 0.003*sl h to y t r 0.091 0.080 + 0.006*sl 0.077 + 0.006*sl 0.063 + 0.007*sl t f 0.085 0.074 + 0.005*sl 0.073 + 0.006*sl 0.066 + 0.006*sl t plh 0.412 0.401 + 0.005*sl 0.407 + 0.004*sl 0.420 + 0.003*sl t phl 0.577 0.566 + 0.006*sl 0.573 + 0.004*sl 0.590 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-183 STD111 oa31dh/oa31/oa31d2/oa31d4 3-or into 2-nand with 0.5x/1x/2x/4x drive logic symbol cell data input load (sl) oa31dh oa31 oa31d2 oa31d4 abcdabcdabcdabcd 0.4 0.5 0.5 0.5 0.8 0.9 0.9 1.1 1.7 1.8 1.8 2.1 0.8 0.9 0.9 1.1 gate count oa31dh oa31 oa31d2 oa31d4 1.67 1.67 3.00 3.33 c d y a b truth table abcdy 000x1 xxx01 other states 0
STD111 3-184 samsung asic oa31dh/oa31/oa31d2/oa31d4 3-or into 2-nand with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa31dh oa31 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.538 0.197 + 0.171*sl 0.181 + 0.175*sl 0.183 + 0.175*sl t f 0.302 0.105 + 0.098*sl 0.088 + 0.103*sl 0.082 + 0.104*sl t plh 0.241 0.093 + 0.074*sl 0.091 + 0.075*sl 0.090 + 0.075*sl t phl 0.189 0.089 + 0.050*sl 0.088 + 0.050*sl 0.088 + 0.050*sl b to y t r 0.541 0.198 + 0.171*sl 0.187 + 0.174*sl 0.183 + 0.175*sl t f 0.341 0.144 + 0.099*sl 0.126 + 0.104*sl 0.120 + 0.104*sl t plh 0.265 0.114 + 0.075*sl 0.116 + 0.075*sl 0.117 + 0.075*sl t phl 0.214 0.112 + 0.051*sl 0.113 + 0.051*sl 0.113 + 0.051*sl c to y t r 0.538 0.194 + 0.172*sl 0.185 + 0.174*sl 0.183 + 0.175*sl t f 0.383 0.186 + 0.099*sl 0.167 + 0.103*sl 0.160 + 0.104*sl t plh 0.275 0.123 + 0.076*sl 0.125 + 0.075*sl 0.127 + 0.075*sl t phl 0.230 0.125 + 0.052*sl 0.131 + 0.051*sl 0.134 + 0.051*sl d to y t r 0.260 0.150 + 0.055*sl 0.135 + 0.059*sl 0.115 + 0.061*sl t f 0.374 0.170 + 0.102*sl 0.164 + 0.104*sl 0.159 + 0.104*sl t plh 0.141 0.087 + 0.027*sl 0.088 + 0.027*sl 0.090 + 0.026*sl t phl 0.228 0.123 + 0.053*sl 0.129 + 0.051*sl 0.133 + 0.051*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.334 0.178 + 0.078*sl 0.166 + 0.081*sl 0.151 + 0.082*sl t f 0.197 0.100 + 0.049*sl 0.087 + 0.052*sl 0.072 + 0.054*sl t plh 0.150 0.080 + 0.035*sl 0.079 + 0.035*sl 0.078 + 0.035*sl t phl 0.137 0.084 + 0.026*sl 0.085 + 0.026*sl 0.085 + 0.026*sl b to y t r 0.334 0.177 + 0.079*sl 0.167 + 0.081*sl 0.157 + 0.082*sl t f 0.238 0.138 + 0.050*sl 0.127 + 0.053*sl 0.113 + 0.054*sl t plh 0.170 0.099 + 0.036*sl 0.100 + 0.035*sl 0.101 + 0.035*sl t phl 0.163 0.110 + 0.027*sl 0.111 + 0.027*sl 0.111 + 0.026*sl c to y t r 0.330 0.170 + 0.080*sl 0.163 + 0.081*sl 0.156 + 0.082*sl t f 0.282 0.183 + 0.049*sl 0.172 + 0.052*sl 0.156 + 0.054*sl t plh 0.179 0.107 + 0.036*sl 0.109 + 0.035*sl 0.110 + 0.035*sl t phl 0.179 0.123 + 0.028*sl 0.127 + 0.027*sl 0.131 + 0.027*sl d to y t r 0.186 0.139 + 0.024*sl 0.130 + 0.026*sl 0.114 + 0.028*sl t f 0.270 0.164 + 0.053*sl 0.162 + 0.053*sl 0.156 + 0.054*sl t plh 0.100 0.071 + 0.014*sl 0.077 + 0.012*sl 0.078 + 0.012*sl t phl 0.167 0.111 + 0.028*sl 0.115 + 0.027*sl 0.119 + 0.027*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-185 STD111 oa31dh/oa31/oa31d2/oa31d4 3-or into 2-nand with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa31d2 oa31d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.268 0.192 + 0.038*sl 0.185 + 0.040*sl 0.166 + 0.041*sl t f 0.155 0.108 + 0.023*sl 0.099 + 0.026*sl 0.082 + 0.027*sl t plh 0.119 0.084 + 0.018*sl 0.085 + 0.018*sl 0.083 + 0.018*sl t phl 0.116 0.088 + 0.014*sl 0.091 + 0.013*sl 0.090 + 0.013*sl b to y t r 0.267 0.190 + 0.039*sl 0.183 + 0.040*sl 0.171 + 0.041*sl t f 0.195 0.147 + 0.024*sl 0.139 + 0.026*sl 0.122 + 0.027*sl t plh 0.138 0.101 + 0.018*sl 0.104 + 0.018*sl 0.105 + 0.018*sl t phl 0.141 0.114 + 0.013*sl 0.115 + 0.013*sl 0.116 + 0.013*sl c to y t r 0.262 0.184 + 0.039*sl 0.178 + 0.040*sl 0.169 + 0.041*sl t f 0.239 0.191 + 0.024*sl 0.185 + 0.026*sl 0.167 + 0.027*sl t plh 0.146 0.109 + 0.018*sl 0.112 + 0.018*sl 0.113 + 0.018*sl t phl 0.156 0.127 + 0.014*sl 0.130 + 0.014*sl 0.135 + 0.013*sl d to y t r 0.168 0.144 + 0.012*sl 0.140 + 0.013*sl 0.123 + 0.014*sl t f 0.224 0.171 + 0.026*sl 0.170 + 0.027*sl 0.165 + 0.027*sl t plh 0.088 0.073 + 0.008*sl 0.078 + 0.006*sl 0.080 + 0.006*sl t phl 0.146 0.117 + 0.014*sl 0.119 + 0.014*sl 0.125 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.078 0.064 + 0.007*sl 0.065 + 0.007*sl 0.053 + 0.007*sl t f 0.066 0.054 + 0.006*sl 0.055 + 0.006*sl 0.052 + 0.006*sl t plh 0.280 0.271 + 0.005*sl 0.276 + 0.004*sl 0.287 + 0.003*sl t phl 0.252 0.241 + 0.005*sl 0.247 + 0.004*sl 0.262 + 0.003*sl b to y t r 0.078 0.065 + 0.007*sl 0.065 + 0.007*sl 0.053 + 0.007*sl t f 0.068 0.055 + 0.006*sl 0.056 + 0.006*sl 0.053 + 0.006*sl t plh 0.301 0.291 + 0.005*sl 0.297 + 0.004*sl 0.308 + 0.003*sl t phl 0.286 0.276 + 0.005*sl 0.281 + 0.004*sl 0.297 + 0.003*sl c to y t r 0.078 0.065 + 0.007*sl 0.064 + 0.007*sl 0.053 + 0.007*sl t f 0.070 0.058 + 0.006*sl 0.059 + 0.006*sl 0.054 + 0.006*sl t plh 0.311 0.301 + 0.005*sl 0.306 + 0.004*sl 0.318 + 0.003*sl t phl 0.310 0.300 + 0.005*sl 0.305 + 0.004*sl 0.321 + 0.003*sl d to y t r 0.073 0.060 + 0.007*sl 0.060 + 0.007*sl 0.049 + 0.007*sl t f 0.069 0.056 + 0.006*sl 0.058 + 0.006*sl 0.055 + 0.006*sl t plh 0.228 0.219 + 0.005*sl 0.223 + 0.003*sl 0.234 + 0.003*sl t phl 0.299 0.288 + 0.005*sl 0.294 + 0.004*sl 0.310 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-186 samsung asic oa311/oa311d2/oa311d4 3-or into 3-nand with 1x/2x/4x drive logic symbol cell data input load (sl) oa311 oa311d2 oa311d4 abcdeabcdeabcde 0.9 0.9 1.0 1.0 1.0 0.9 0.9 1.0 1.0 1.0 0.9 0.9 1.0 1.0 1.0 gate count oa311 oa311d2 oa311d4 2.00 2.67 3.33 d e y a b c truth table abcdey 000xx1 xxx0x1 xxxx01 other states 0
samsung asic 3-187 STD111 oa311/oa311d2/oa311d4 3-or into 3-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa311 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.379 0.222 + 0.079*sl 0.211 + 0.081*sl 0.201 + 0.082*sl t f 0.245 0.139 + 0.053*sl 0.130 + 0.055*sl 0.118 + 0.057*sl t plh 0.172 0.102 + 0.035*sl 0.100 + 0.035*sl 0.100 + 0.035*sl t phl 0.150 0.097 + 0.026*sl 0.097 + 0.026*sl 0.096 + 0.026*sl b to y t r 0.380 0.221 + 0.080*sl 0.215 + 0.081*sl 0.206 + 0.082*sl t f 0.288 0.182 + 0.053*sl 0.173 + 0.055*sl 0.161 + 0.057*sl t plh 0.193 0.122 + 0.036*sl 0.123 + 0.036*sl 0.124 + 0.035*sl t phl 0.176 0.122 + 0.027*sl 0.123 + 0.026*sl 0.123 + 0.026*sl c to y t r 0.377 0.216 + 0.080*sl 0.211 + 0.082*sl 0.205 + 0.082*sl t f 0.333 0.230 + 0.052*sl 0.220 + 0.054*sl 0.206 + 0.056*sl t plh 0.202 0.131 + 0.036*sl 0.132 + 0.036*sl 0.133 + 0.035*sl t phl 0.191 0.135 + 0.028*sl 0.139 + 0.027*sl 0.142 + 0.026*sl d to y t r 0.233 0.172 + 0.031*sl 0.163 + 0.033*sl 0.150 + 0.034*sl t f 0.325 0.216 + 0.054*sl 0.213 + 0.055*sl 0.206 + 0.056*sl t plh 0.128 0.097 + 0.016*sl 0.098 + 0.015*sl 0.099 + 0.015*sl t phl 0.196 0.140 + 0.028*sl 0.144 + 0.027*sl 0.148 + 0.026*sl e to y t r 0.253 0.193 + 0.030*sl 0.182 + 0.033*sl 0.167 + 0.034*sl t f 0.323 0.214 + 0.054*sl 0.211 + 0.055*sl 0.205 + 0.056*sl t plh 0.137 0.106 + 0.015*sl 0.106 + 0.015*sl 0.107 + 0.015*sl t phl 0.197 0.141 + 0.028*sl 0.145 + 0.027*sl 0.149 + 0.026*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-188 samsung asic oa311/oa311d2/oa311d4 3-or into 3-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa311d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.084 0.058 + 0.013*sl 0.057 + 0.013*sl 0.045 + 0.014*sl t f 0.072 0.047 + 0.013*sl 0.052 + 0.011*sl 0.044 + 0.012*sl t plh 0.284 0.267 + 0.008*sl 0.273 + 0.007*sl 0.280 + 0.006*sl t phl 0.252 0.234 + 0.009*sl 0.241 + 0.007*sl 0.251 + 0.006*sl b to y t r 0.084 0.058 + 0.013*sl 0.057 + 0.013*sl 0.045 + 0.014*sl t f 0.074 0.052 + 0.011*sl 0.052 + 0.011*sl 0.045 + 0.012*sl t plh 0.303 0.287 + 0.008*sl 0.293 + 0.007*sl 0.300 + 0.006*sl t phl 0.284 0.266 + 0.009*sl 0.274 + 0.007*sl 0.284 + 0.006*sl c to y t r 0.085 0.058 + 0.013*sl 0.058 + 0.013*sl 0.045 + 0.014*sl t f 0.074 0.050 + 0.012*sl 0.054 + 0.011*sl 0.046 + 0.012*sl t plh 0.311 0.295 + 0.008*sl 0.301 + 0.007*sl 0.308 + 0.006*sl t phl 0.304 0.286 + 0.009*sl 0.293 + 0.007*sl 0.304 + 0.006*sl d to y t r 0.079 0.053 + 0.013*sl 0.051 + 0.014*sl 0.041 + 0.014*sl t f 0.076 0.053 + 0.012*sl 0.054 + 0.011*sl 0.046 + 0.012*sl t plh 0.247 0.231 + 0.008*sl 0.237 + 0.007*sl 0.243 + 0.006*sl t phl 0.308 0.290 + 0.009*sl 0.298 + 0.007*sl 0.308 + 0.006*sl e to y t r 0.079 0.053 + 0.013*sl 0.051 + 0.014*sl 0.042 + 0.014*sl t f 0.076 0.053 + 0.012*sl 0.054 + 0.011*sl 0.047 + 0.012*sl t plh 0.258 0.242 + 0.008*sl 0.248 + 0.007*sl 0.253 + 0.006*sl t phl 0.308 0.291 + 0.009*sl 0.298 + 0.007*sl 0.309 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-189 STD111 oa311/oa311d2/oa311d4 3-or into 3-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa311d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.080 0.067 + 0.006*sl 0.067 + 0.007*sl 0.054 + 0.007*sl t f 0.068 0.055 + 0.007*sl 0.058 + 0.006*sl 0.055 + 0.006*sl t plh 0.311 0.301 + 0.005*sl 0.307 + 0.004*sl 0.318 + 0.003*sl t phl 0.275 0.264 + 0.005*sl 0.270 + 0.004*sl 0.286 + 0.003*sl b to y t r 0.080 0.067 + 0.006*sl 0.067 + 0.007*sl 0.054 + 0.007*sl t f 0.070 0.057 + 0.007*sl 0.060 + 0.006*sl 0.054 + 0.006*sl t plh 0.331 0.322 + 0.005*sl 0.327 + 0.004*sl 0.338 + 0.003*sl t phl 0.308 0.297 + 0.005*sl 0.303 + 0.004*sl 0.319 + 0.003*sl c to y t r 0.081 0.068 + 0.006*sl 0.068 + 0.006*sl 0.055 + 0.007*sl t f 0.072 0.059 + 0.006*sl 0.062 + 0.006*sl 0.056 + 0.006*sl t plh 0.340 0.330 + 0.005*sl 0.335 + 0.004*sl 0.347 + 0.003*sl t phl 0.329 0.318 + 0.005*sl 0.324 + 0.004*sl 0.340 + 0.003*sl d to y t r 0.076 0.063 + 0.006*sl 0.063 + 0.007*sl 0.051 + 0.007*sl t f 0.072 0.059 + 0.006*sl 0.062 + 0.006*sl 0.056 + 0.006*sl t plh 0.265 0.255 + 0.005*sl 0.260 + 0.004*sl 0.271 + 0.003*sl t phl 0.333 0.322 + 0.005*sl 0.328 + 0.004*sl 0.344 + 0.003*sl e to y t r 0.077 0.064 + 0.007*sl 0.064 + 0.007*sl 0.052 + 0.007*sl t f 0.072 0.059 + 0.006*sl 0.062 + 0.006*sl 0.056 + 0.006*sl t plh 0.273 0.263 + 0.005*sl 0.269 + 0.004*sl 0.279 + 0.003*sl t phl 0.334 0.323 + 0.005*sl 0.329 + 0.004*sl 0.345 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-190 samsung asic oa3111/oa3111d2 3-or into 4-nand with 1x/2x drive logic symbol cell data input load (sl) gate count oa3111 oa3111d2 oa3111 oa3111d2 abcdefabcdef 1.0 1.0 1.0 0.8 0.8 0.9 1.0 1.0 1.0 0.8 0.9 0.9 2.33 3.33 d e y a c b f truth table abcdefy 000xxx1 xxx0xx1 xxxx0x1 xxxxx01 other states 0
samsung asic 3-191 STD111 oa3111/oa3111d2 3-or into 4-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa3111 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.400 0.241 + 0.079*sl 0.233 + 0.082*sl 0.225 + 0.082*sl t f 0.313 0.186 + 0.063*sl 0.179 + 0.065*sl 0.170 + 0.066*sl t plh 0.184 0.114 + 0.035*sl 0.113 + 0.035*sl 0.113 + 0.035*sl t phl 0.165 0.106 + 0.030*sl 0.105 + 0.030*sl 0.105 + 0.030*sl b to y t r 0.403 0.243 + 0.080*sl 0.238 + 0.081*sl 0.229 + 0.082*sl t f 0.363 0.237 + 0.063*sl 0.229 + 0.065*sl 0.219 + 0.066*sl t plh 0.206 0.134 + 0.036*sl 0.135 + 0.036*sl 0.137 + 0.035*sl t phl 0.195 0.135 + 0.030*sl 0.135 + 0.030*sl 0.135 + 0.030*sl c to y t r 0.400 0.239 + 0.080*sl 0.234 + 0.082*sl 0.229 + 0.082*sl t f 0.415 0.293 + 0.061*sl 0.283 + 0.064*sl 0.270 + 0.065*sl t plh 0.214 0.142 + 0.036*sl 0.144 + 0.036*sl 0.146 + 0.035*sl t phl 0.214 0.152 + 0.031*sl 0.155 + 0.030*sl 0.158 + 0.030*sl d to y t r 0.314 0.226 + 0.044*sl 0.218 + 0.046*sl 0.206 + 0.048*sl t f 0.412 0.285 + 0.063*sl 0.281 + 0.064*sl 0.274 + 0.065*sl t plh 0.171 0.129 + 0.021*sl 0.130 + 0.021*sl 0.132 + 0.021*sl t phl 0.234 0.171 + 0.031*sl 0.175 + 0.030*sl 0.179 + 0.030*sl e to y t r 0.337 0.249 + 0.044*sl 0.241 + 0.046*sl 0.228 + 0.048*sl t f 0.411 0.284 + 0.063*sl 0.280 + 0.064*sl 0.273 + 0.065*sl t plh 0.184 0.142 + 0.021*sl 0.142 + 0.021*sl 0.145 + 0.021*sl t phl 0.241 0.178 + 0.031*sl 0.182 + 0.030*sl 0.186 + 0.030*sl f to y t r 0.361 0.273 + 0.044*sl 0.265 + 0.046*sl 0.252 + 0.048*sl t f 0.409 0.282 + 0.064*sl 0.278 + 0.065*sl 0.273 + 0.065*sl t plh 0.195 0.152 + 0.021*sl 0.153 + 0.021*sl 0.156 + 0.021*sl t phl 0.243 0.181 + 0.031*sl 0.184 + 0.030*sl 0.189 + 0.030*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-192 samsung asic oa3111/oa3111d2 3-or into 4-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa3111d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.085 0.059 + 0.013*sl 0.059 + 0.013*sl 0.045 + 0.014*sl t f 0.075 0.049 + 0.013*sl 0.055 + 0.011*sl 0.046 + 0.012*sl t plh 0.298 0.281 + 0.008*sl 0.288 + 0.007*sl 0.294 + 0.006*sl t phl 0.275 0.257 + 0.009*sl 0.265 + 0.007*sl 0.275 + 0.006*sl b to y t r 0.086 0.060 + 0.013*sl 0.059 + 0.013*sl 0.046 + 0.014*sl t f 0.077 0.053 + 0.012*sl 0.056 + 0.011*sl 0.047 + 0.012*sl t plh 0.319 0.303 + 0.008*sl 0.309 + 0.007*sl 0.315 + 0.006*sl t phl 0.312 0.294 + 0.009*sl 0.302 + 0.007*sl 0.312 + 0.006*sl c to y t r 0.084 0.059 + 0.013*sl 0.056 + 0.013*sl 0.046 + 0.014*sl t f 0.079 0.055 + 0.012*sl 0.058 + 0.011*sl 0.049 + 0.012*sl t plh 0.328 0.311 + 0.008*sl 0.317 + 0.007*sl 0.324 + 0.006*sl t phl 0.338 0.320 + 0.009*sl 0.328 + 0.007*sl 0.339 + 0.006*sl d to y t r 0.083 0.056 + 0.013*sl 0.056 + 0.013*sl 0.043 + 0.014*sl t f 0.079 0.055 + 0.012*sl 0.058 + 0.011*sl 0.049 + 0.012*sl t plh 0.297 0.280 + 0.008*sl 0.286 + 0.007*sl 0.293 + 0.006*sl t phl 0.358 0.340 + 0.009*sl 0.347 + 0.007*sl 0.358 + 0.006*sl e to y t r 0.083 0.057 + 0.013*sl 0.056 + 0.013*sl 0.044 + 0.014*sl t f 0.080 0.056 + 0.012*sl 0.058 + 0.011*sl 0.049 + 0.012*sl t plh 0.312 0.296 + 0.008*sl 0.302 + 0.007*sl 0.308 + 0.006*sl t phl 0.365 0.347 + 0.009*sl 0.354 + 0.007*sl 0.365 + 0.006*sl f to y t r 0.084 0.057 + 0.013*sl 0.058 + 0.013*sl 0.045 + 0.014*sl t f 0.079 0.055 + 0.012*sl 0.058 + 0.011*sl 0.049 + 0.012*sl t plh 0.326 0.310 + 0.008*sl 0.316 + 0.007*sl 0.322 + 0.006*sl t phl 0.367 0.349 + 0.009*sl 0.357 + 0.007*sl 0.368 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-193 STD111 oa32/oa32d2/oa32d4 3-or and 2-or into 2-nand with 1x/2x/4x drive logic symbol cell data input load (sl) oa32 oa32d2 oa32d4 abcdeabcdeabcde 0.8 0.8 0.9 0.9 0.9 0.8 0.8 0.9 0.9 0.9 0.8 0.8 0.9 0.9 0.9 gate count oa32 oa32d2 oa32d4 2.00 3.33 4.00 d e y a b c truth table abcdey 000xx1 xxx001 other states 0
STD111 3-194 samsung asic oa32/oa32d2/oa32d4 3-or and 2-or into 2-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa32 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.429 0.274 + 0.078*sl 0.261 + 0.081*sl 0.246 + 0.083*sl t f 0.311 0.170 + 0.071*sl 0.162 + 0.073*sl 0.157 + 0.073*sl t plh 0.167 0.094 + 0.036*sl 0.097 + 0.036*sl 0.100 + 0.035*sl t phl 0.209 0.138 + 0.036*sl 0.140 + 0.035*sl 0.141 + 0.035*sl b to y t r 0.429 0.272 + 0.079*sl 0.262 + 0.081*sl 0.251 + 0.083*sl t f 0.367 0.223 + 0.072*sl 0.216 + 0.074*sl 0.212 + 0.074*sl t plh 0.189 0.115 + 0.037*sl 0.118 + 0.036*sl 0.123 + 0.036*sl t phl 0.247 0.175 + 0.036*sl 0.177 + 0.036*sl 0.178 + 0.036*sl c to y t r 0.425 0.266 + 0.080*sl 0.258 + 0.082*sl 0.250 + 0.083*sl t f 0.424 0.280 + 0.072*sl 0.274 + 0.073*sl 0.269 + 0.074*sl t plh 0.198 0.123 + 0.037*sl 0.128 + 0.036*sl 0.133 + 0.036*sl t phl 0.274 0.200 + 0.037*sl 0.204 + 0.036*sl 0.208 + 0.036*sl d to y t r 0.322 0.221 + 0.050*sl 0.210 + 0.053*sl 0.193 + 0.055*sl t f 0.369 0.224 + 0.073*sl 0.220 + 0.074*sl 0.215 + 0.074*sl t plh 0.151 0.102 + 0.024*sl 0.103 + 0.024*sl 0.105 + 0.024*sl t phl 0.245 0.169 + 0.038*sl 0.175 + 0.036*sl 0.181 + 0.036*sl e to y t r 0.314 0.210 + 0.052*sl 0.202 + 0.054*sl 0.192 + 0.055*sl t f 0.420 0.274 + 0.073*sl 0.271 + 0.074*sl 0.268 + 0.074*sl t plh 0.152 0.102 + 0.025*sl 0.104 + 0.024*sl 0.107 + 0.024*sl t phl 0.280 0.206 + 0.037*sl 0.210 + 0.036*sl 0.215 + 0.036*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-195 STD111 oa32/oa32d2/oa32d4 3-or and 2-or into 2-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa32d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.087 0.061 + 0.013*sl 0.062 + 0.013*sl 0.047 + 0.014*sl t f 0.074 0.049 + 0.013*sl 0.054 + 0.011*sl 0.046 + 0.012*sl t plh 0.286 0.270 + 0.008*sl 0.276 + 0.007*sl 0.283 + 0.006*sl t phl 0.313 0.295 + 0.009*sl 0.302 + 0.007*sl 0.312 + 0.006*sl b to y t r 0.088 0.062 + 0.013*sl 0.060 + 0.013*sl 0.047 + 0.014*sl t f 0.077 0.054 + 0.012*sl 0.055 + 0.011*sl 0.047 + 0.012*sl t plh 0.307 0.291 + 0.008*sl 0.297 + 0.007*sl 0.304 + 0.006*sl t phl 0.359 0.341 + 0.009*sl 0.348 + 0.007*sl 0.358 + 0.006*sl c to y t r 0.087 0.062 + 0.013*sl 0.059 + 0.013*sl 0.047 + 0.014*sl t f 0.078 0.053 + 0.012*sl 0.057 + 0.011*sl 0.048 + 0.012*sl t plh 0.318 0.302 + 0.008*sl 0.308 + 0.007*sl 0.314 + 0.006*sl t phl 0.395 0.377 + 0.009*sl 0.385 + 0.007*sl 0.395 + 0.006*sl d to y t r 0.087 0.062 + 0.013*sl 0.061 + 0.013*sl 0.047 + 0.014*sl t f 0.077 0.054 + 0.011*sl 0.055 + 0.011*sl 0.047 + 0.012*sl t plh 0.275 0.259 + 0.008*sl 0.265 + 0.007*sl 0.272 + 0.006*sl t phl 0.357 0.340 + 0.009*sl 0.347 + 0.007*sl 0.357 + 0.006*sl e to y t r 0.087 0.061 + 0.013*sl 0.060 + 0.013*sl 0.047 + 0.014*sl t f 0.079 0.056 + 0.011*sl 0.057 + 0.011*sl 0.048 + 0.012*sl t plh 0.277 0.260 + 0.008*sl 0.267 + 0.007*sl 0.273 + 0.006*sl t phl 0.402 0.384 + 0.009*sl 0.391 + 0.007*sl 0.402 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-196 samsung asic oa32/oa32d2/oa32d4 3-or and 2-or into 2-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa32d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.082 0.070 + 0.006*sl 0.069 + 0.006*sl 0.057 + 0.007*sl t f 0.071 0.060 + 0.006*sl 0.060 + 0.006*sl 0.056 + 0.006*sl t plh 0.315 0.305 + 0.005*sl 0.310 + 0.004*sl 0.322 + 0.003*sl t phl 0.339 0.329 + 0.005*sl 0.334 + 0.004*sl 0.350 + 0.003*sl b to y t r 0.083 0.070 + 0.006*sl 0.070 + 0.006*sl 0.057 + 0.007*sl t f 0.073 0.061 + 0.006*sl 0.062 + 0.006*sl 0.057 + 0.006*sl t plh 0.336 0.326 + 0.005*sl 0.331 + 0.004*sl 0.343 + 0.003*sl t phl 0.386 0.375 + 0.005*sl 0.381 + 0.004*sl 0.397 + 0.003*sl c to y t r 0.083 0.071 + 0.006*sl 0.070 + 0.006*sl 0.056 + 0.007*sl t f 0.075 0.063 + 0.006*sl 0.064 + 0.006*sl 0.059 + 0.006*sl t plh 0.347 0.337 + 0.005*sl 0.343 + 0.004*sl 0.354 + 0.003*sl t phl 0.424 0.413 + 0.005*sl 0.419 + 0.004*sl 0.435 + 0.003*sl d to y t r 0.083 0.070 + 0.006*sl 0.069 + 0.006*sl 0.056 + 0.007*sl t f 0.074 0.062 + 0.006*sl 0.063 + 0.006*sl 0.058 + 0.006*sl t plh 0.299 0.289 + 0.005*sl 0.295 + 0.004*sl 0.307 + 0.003*sl t phl 0.386 0.375 + 0.005*sl 0.380 + 0.004*sl 0.397 + 0.003*sl e to y t r 0.083 0.070 + 0.006*sl 0.069 + 0.006*sl 0.056 + 0.007*sl t f 0.075 0.063 + 0.006*sl 0.064 + 0.006*sl 0.059 + 0.006*sl t plh 0.301 0.291 + 0.005*sl 0.296 + 0.004*sl 0.308 + 0.003*sl t phl 0.430 0.419 + 0.005*sl 0.425 + 0.004*sl 0.441 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-197 STD111 oa321/oa321d2/oa321d4 3-or and 2-or into 3-nand with 1x/2x/4x drive logic symbol cell data input load (sl) oa321 oa321d2 oa321d4 abcdefabcdefabcdef 0.9 0.9 0.9 0.9 1.0 1.0 0.9 0.9 0.9 0.9 1.0 1.0 0.9 0.9 0.9 0.9 1.0 1.0 gate count oa321 oa321d2 oa321d4 2.67 3.33 4.00 d e y a b c f truth table abcdefy 000xxx1 xxx00x1 xxxxx01 other states 0
STD111 3-198 samsung asic oa321/oa321d2/oa321d4 3-or and 2-or into 3-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa321 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.474 0.318 + 0.078*sl 0.306 + 0.081*sl 0.294 + 0.082*sl t f 0.337 0.205 + 0.066*sl 0.199 + 0.068*sl 0.193 + 0.068*sl t plh 0.188 0.116 + 0.036*sl 0.118 + 0.036*sl 0.121 + 0.035*sl t phl 0.210 0.146 + 0.032*sl 0.147 + 0.032*sl 0.148 + 0.032*sl b to y t r 0.474 0.316 + 0.079*sl 0.309 + 0.081*sl 0.299 + 0.082*sl t f 0.385 0.253 + 0.066*sl 0.246 + 0.068*sl 0.242 + 0.068*sl t plh 0.209 0.136 + 0.037*sl 0.139 + 0.036*sl 0.143 + 0.035*sl t phl 0.241 0.177 + 0.032*sl 0.178 + 0.032*sl 0.179 + 0.032*sl c to y t r 0.471 0.311 + 0.080*sl 0.305 + 0.082*sl 0.298 + 0.082*sl t f 0.438 0.307 + 0.066*sl 0.300 + 0.067*sl 0.294 + 0.068*sl t plh 0.218 0.144 + 0.037*sl 0.147 + 0.036*sl 0.152 + 0.035*sl t phl 0.265 0.199 + 0.033*sl 0.202 + 0.032*sl 0.205 + 0.032*sl d to y t r 0.357 0.255 + 0.051*sl 0.245 + 0.054*sl 0.231 + 0.055*sl t f 0.385 0.253 + 0.066*sl 0.249 + 0.067*sl 0.244 + 0.067*sl t plh 0.172 0.124 + 0.024*sl 0.125 + 0.024*sl 0.126 + 0.024*sl t phl 0.244 0.177 + 0.033*sl 0.182 + 0.032*sl 0.187 + 0.032*sl e to y t r 0.351 0.246 + 0.053*sl 0.240 + 0.054*sl 0.232 + 0.055*sl t f 0.436 0.302 + 0.067*sl 0.299 + 0.068*sl 0.294 + 0.068*sl t plh 0.173 0.124 + 0.024*sl 0.126 + 0.024*sl 0.128 + 0.024*sl t phl 0.278 0.211 + 0.033*sl 0.215 + 0.032*sl 0.219 + 0.032*sl f to y t r 0.290 0.238 + 0.026*sl 0.227 + 0.029*sl 0.207 + 0.031*sl t f 0.434 0.300 + 0.067*sl 0.298 + 0.068*sl 0.294 + 0.068*sl t plh 0.136 0.107 + 0.015*sl 0.108 + 0.014*sl 0.110 + 0.014*sl t phl 0.278 0.211 + 0.033*sl 0.214 + 0.033*sl 0.219 + 0.032*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-199 STD111 oa321/oa321d2/oa321d4 3-or and 2-or into 3-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa321d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.090 0.065 + 0.013*sl 0.064 + 0.013*sl 0.049 + 0.014*sl t f 0.076 0.051 + 0.013*sl 0.055 + 0.011*sl 0.047 + 0.012*sl t plh 0.312 0.296 + 0.008*sl 0.302 + 0.007*sl 0.309 + 0.006*sl t phl 0.321 0.303 + 0.009*sl 0.310 + 0.007*sl 0.321 + 0.006*sl b to y t r 0.090 0.064 + 0.013*sl 0.064 + 0.013*sl 0.049 + 0.014*sl t f 0.079 0.055 + 0.012*sl 0.056 + 0.011*sl 0.048 + 0.012*sl t plh 0.333 0.317 + 0.008*sl 0.323 + 0.007*sl 0.330 + 0.006*sl t phl 0.362 0.344 + 0.009*sl 0.351 + 0.007*sl 0.362 + 0.006*sl c to y t r 0.089 0.065 + 0.012*sl 0.061 + 0.013*sl 0.049 + 0.014*sl t f 0.080 0.056 + 0.012*sl 0.059 + 0.011*sl 0.050 + 0.012*sl t plh 0.342 0.325 + 0.008*sl 0.332 + 0.007*sl 0.339 + 0.006*sl t phl 0.391 0.373 + 0.009*sl 0.380 + 0.007*sl 0.391 + 0.006*sl d to y t r 0.089 0.064 + 0.012*sl 0.060 + 0.013*sl 0.048 + 0.014*sl t f 0.079 0.056 + 0.012*sl 0.056 + 0.011*sl 0.049 + 0.012*sl t plh 0.300 0.283 + 0.008*sl 0.289 + 0.007*sl 0.296 + 0.006*sl t phl 0.360 0.343 + 0.009*sl 0.350 + 0.007*sl 0.360 + 0.006*sl e to y t r 0.089 0.064 + 0.012*sl 0.061 + 0.013*sl 0.049 + 0.014*sl t f 0.081 0.057 + 0.012*sl 0.058 + 0.011*sl 0.050 + 0.012*sl t plh 0.301 0.284 + 0.008*sl 0.291 + 0.007*sl 0.297 + 0.006*sl t phl 0.403 0.385 + 0.009*sl 0.392 + 0.007*sl 0.403 + 0.006*sl f to y t r 0.081 0.055 + 0.013*sl 0.053 + 0.013*sl 0.043 + 0.014*sl t f 0.081 0.057 + 0.012*sl 0.059 + 0.011*sl 0.050 + 0.012*sl t plh 0.263 0.247 + 0.008*sl 0.252 + 0.007*sl 0.258 + 0.006*sl t phl 0.402 0.384 + 0.009*sl 0.392 + 0.007*sl 0.402 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-200 samsung asic oa321/oa321d2/oa321d4 3-or and 2-or into 3-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa321d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.086 0.075 + 0.006*sl 0.072 + 0.006*sl 0.059 + 0.007*sl t f 0.073 0.061 + 0.006*sl 0.061 + 0.006*sl 0.058 + 0.006*sl t plh 0.342 0.332 + 0.005*sl 0.338 + 0.004*sl 0.350 + 0.003*sl t phl 0.346 0.335 + 0.005*sl 0.341 + 0.004*sl 0.357 + 0.003*sl b to y t r 0.086 0.073 + 0.007*sl 0.074 + 0.006*sl 0.059 + 0.007*sl t f 0.075 0.063 + 0.006*sl 0.064 + 0.006*sl 0.059 + 0.006*sl t plh 0.363 0.353 + 0.005*sl 0.359 + 0.004*sl 0.371 + 0.003*sl t phl 0.387 0.376 + 0.005*sl 0.382 + 0.004*sl 0.398 + 0.003*sl c to y t r 0.086 0.073 + 0.007*sl 0.074 + 0.006*sl 0.059 + 0.007*sl t f 0.077 0.064 + 0.006*sl 0.066 + 0.006*sl 0.059 + 0.006*sl t plh 0.372 0.362 + 0.005*sl 0.368 + 0.004*sl 0.380 + 0.003*sl t phl 0.416 0.405 + 0.005*sl 0.412 + 0.004*sl 0.428 + 0.003*sl d to y t r 0.085 0.072 + 0.006*sl 0.071 + 0.006*sl 0.058 + 0.007*sl t f 0.075 0.063 + 0.006*sl 0.064 + 0.006*sl 0.060 + 0.006*sl t plh 0.324 0.314 + 0.005*sl 0.320 + 0.004*sl 0.332 + 0.003*sl t phl 0.386 0.375 + 0.005*sl 0.381 + 0.004*sl 0.397 + 0.003*sl e to y t r 0.085 0.072 + 0.006*sl 0.072 + 0.006*sl 0.058 + 0.007*sl t f 0.077 0.065 + 0.006*sl 0.066 + 0.006*sl 0.061 + 0.006*sl t plh 0.325 0.315 + 0.005*sl 0.321 + 0.004*sl 0.333 + 0.003*sl t phl 0.428 0.418 + 0.005*sl 0.423 + 0.004*sl 0.440 + 0.003*sl f to y t r 0.079 0.067 + 0.006*sl 0.066 + 0.006*sl 0.053 + 0.007*sl t f 0.077 0.065 + 0.006*sl 0.066 + 0.006*sl 0.061 + 0.006*sl t plh 0.279 0.270 + 0.005*sl 0.275 + 0.004*sl 0.286 + 0.003*sl t phl 0.427 0.417 + 0.005*sl 0.422 + 0.004*sl 0.439 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-201 STD111 oa322/oa322d2/oa322d4 3-or and two 2-ors into 3-nand with 1x/2x/4x drive logic symbol cell data input load (sl) gate count oa322 oa322 abcdefg 0.8 0.9 0.9 0.9 0.9 0.9 1.0 3.00 oa322d2 oa322d2 abcdefg 0.8 0.9 0.9 0.9 0.9 0.9 1.0 4.00 oa322d4 oa322d4 abcdefg 0.8 0.9 0.9 0.9 0.9 0.9 1.0 4.67 d e y a b f g c truth table abcdefgy 000xxxx1 xxx00xx1 xxxxx001 other states 0
STD111 3-202 samsung asic oa322/oa322d2/oa322d4 3-or and two 2-ors into 3-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa322 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.560 0.404 + 0.078*sl 0.391 + 0.081*sl 0.379 + 0.082*sl t f 0.474 0.305 + 0.085*sl 0.301 + 0.086*sl 0.301 + 0.086*sl t plh 0.205 0.131 + 0.037*sl 0.135 + 0.036*sl 0.139 + 0.035*sl t phl 0.296 0.215 + 0.040*sl 0.217 + 0.040*sl 0.219 + 0.040*sl b to y t r 0.560 0.402 + 0.079*sl 0.394 + 0.081*sl 0.383 + 0.082*sl t f 0.533 0.363 + 0.085*sl 0.361 + 0.086*sl 0.361 + 0.086*sl t plh 0.226 0.152 + 0.037*sl 0.156 + 0.036*sl 0.161 + 0.035*sl t phl 0.336 0.255 + 0.040*sl 0.257 + 0.040*sl 0.258 + 0.040*sl c to y t r 0.556 0.397 + 0.080*sl 0.390 + 0.081*sl 0.383 + 0.082*sl t f 0.597 0.427 + 0.085*sl 0.425 + 0.086*sl 0.426 + 0.085*sl t plh 0.235 0.160 + 0.037*sl 0.165 + 0.036*sl 0.170 + 0.035*sl t phl 0.368 0.287 + 0.041*sl 0.289 + 0.040*sl 0.292 + 0.040*sl d to y t r 0.413 0.310 + 0.052*sl 0.301 + 0.054*sl 0.285 + 0.056*sl t f 0.537 0.368 + 0.084*sl 0.365 + 0.085*sl 0.363 + 0.085*sl t plh 0.179 0.129 + 0.025*sl 0.131 + 0.024*sl 0.135 + 0.024*sl t phl 0.346 0.263 + 0.042*sl 0.267 + 0.040*sl 0.272 + 0.040*sl e to y t r 0.407 0.301 + 0.053*sl 0.294 + 0.055*sl 0.285 + 0.056*sl t f 0.598 0.428 + 0.085*sl 0.426 + 0.085*sl 0.425 + 0.085*sl t plh 0.183 0.133 + 0.025*sl 0.134 + 0.025*sl 0.138 + 0.024*sl t phl 0.387 0.305 + 0.041*sl 0.308 + 0.040*sl 0.312 + 0.040*sl f to y t r 0.446 0.345 + 0.051*sl 0.335 + 0.053*sl 0.318 + 0.055*sl t f 0.535 0.366 + 0.084*sl 0.365 + 0.085*sl 0.363 + 0.085*sl t plh 0.197 0.148 + 0.025*sl 0.150 + 0.024*sl 0.153 + 0.024*sl t phl 0.360 0.277 + 0.041*sl 0.282 + 0.040*sl 0.287 + 0.040*sl g to y t r 0.440 0.335 + 0.052*sl 0.329 + 0.054*sl 0.319 + 0.055*sl t f 0.597 0.426 + 0.085*sl 0.426 + 0.085*sl 0.425 + 0.086*sl t plh 0.199 0.149 + 0.025*sl 0.151 + 0.024*sl 0.155 + 0.024*sl t phl 0.402 0.320 + 0.041*sl 0.323 + 0.040*sl 0.327 + 0.040*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-203 STD111 oa322/oa322d2/oa322d4 3-or and two 2-ors into 3-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa322d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.095 0.069 + 0.013*sl 0.069 + 0.013*sl 0.052 + 0.014*sl t f 0.081 0.057 + 0.012*sl 0.060 + 0.011*sl 0.051 + 0.012*sl t plh 0.341 0.324 + 0.008*sl 0.331 + 0.007*sl 0.338 + 0.006*sl t phl 0.416 0.398 + 0.009*sl 0.406 + 0.007*sl 0.417 + 0.006*sl b to y t r 0.095 0.070 + 0.013*sl 0.069 + 0.013*sl 0.053 + 0.014*sl t f 0.084 0.060 + 0.012*sl 0.063 + 0.011*sl 0.052 + 0.012*sl t plh 0.362 0.345 + 0.008*sl 0.352 + 0.007*sl 0.360 + 0.006*sl t phl 0.466 0.448 + 0.009*sl 0.455 + 0.007*sl 0.466 + 0.006*sl c to y t r 0.095 0.070 + 0.012*sl 0.067 + 0.013*sl 0.053 + 0.014*sl t f 0.086 0.062 + 0.012*sl 0.066 + 0.011*sl 0.054 + 0.012*sl t plh 0.371 0.354 + 0.008*sl 0.361 + 0.007*sl 0.368 + 0.006*sl t phl 0.506 0.488 + 0.009*sl 0.496 + 0.007*sl 0.507 + 0.006*sl d to y t r 0.093 0.066 + 0.013*sl 0.067 + 0.013*sl 0.051 + 0.014*sl t f 0.084 0.061 + 0.011*sl 0.062 + 0.011*sl 0.053 + 0.012*sl t plh 0.318 0.302 + 0.008*sl 0.308 + 0.007*sl 0.315 + 0.006*sl t phl 0.473 0.455 + 0.009*sl 0.463 + 0.007*sl 0.474 + 0.006*sl e to y t r 0.092 0.069 + 0.012*sl 0.063 + 0.013*sl 0.051 + 0.014*sl t f 0.086 0.062 + 0.012*sl 0.066 + 0.011*sl 0.054 + 0.012*sl t plh 0.321 0.304 + 0.008*sl 0.311 + 0.007*sl 0.318 + 0.006*sl t phl 0.525 0.507 + 0.009*sl 0.514 + 0.007*sl 0.526 + 0.006*sl f to y t r 0.094 0.070 + 0.012*sl 0.067 + 0.013*sl 0.053 + 0.014*sl t f 0.083 0.060 + 0.012*sl 0.062 + 0.011*sl 0.053 + 0.012*sl t plh 0.340 0.323 + 0.008*sl 0.330 + 0.007*sl 0.337 + 0.006*sl t phl 0.488 0.469 + 0.009*sl 0.477 + 0.007*sl 0.488 + 0.006*sl g to y t r 0.094 0.070 + 0.012*sl 0.067 + 0.013*sl 0.053 + 0.014*sl t f 0.087 0.063 + 0.012*sl 0.066 + 0.011*sl 0.055 + 0.012*sl t plh 0.341 0.324 + 0.008*sl 0.331 + 0.007*sl 0.338 + 0.006*sl t phl 0.539 0.521 + 0.009*sl 0.529 + 0.007*sl 0.540 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-204 samsung asic oa322/oa322d2/oa322d4 3-or and two 2-ors into 3-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa322d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.091 0.080 + 0.006*sl 0.077 + 0.006*sl 0.063 + 0.007*sl t f 0.079 0.066 + 0.006*sl 0.068 + 0.006*sl 0.062 + 0.006*sl t plh 0.367 0.357 + 0.005*sl 0.363 + 0.004*sl 0.376 + 0.003*sl t phl 0.446 0.435 + 0.005*sl 0.440 + 0.004*sl 0.457 + 0.003*sl b to y t r 0.091 0.078 + 0.006*sl 0.078 + 0.006*sl 0.063 + 0.007*sl t f 0.081 0.069 + 0.006*sl 0.069 + 0.006*sl 0.063 + 0.006*sl t plh 0.389 0.379 + 0.005*sl 0.384 + 0.004*sl 0.398 + 0.003*sl t phl 0.495 0.484 + 0.006*sl 0.491 + 0.004*sl 0.507 + 0.003*sl c to y t r 0.090 0.078 + 0.006*sl 0.077 + 0.006*sl 0.063 + 0.007*sl t f 0.084 0.073 + 0.006*sl 0.073 + 0.006*sl 0.065 + 0.006*sl t plh 0.398 0.387 + 0.005*sl 0.393 + 0.004*sl 0.406 + 0.003*sl t phl 0.537 0.526 + 0.006*sl 0.532 + 0.004*sl 0.549 + 0.003*sl d to y t r 0.088 0.077 + 0.006*sl 0.074 + 0.006*sl 0.061 + 0.007*sl t f 0.080 0.068 + 0.006*sl 0.070 + 0.006*sl 0.064 + 0.006*sl t plh 0.340 0.330 + 0.005*sl 0.336 + 0.004*sl 0.348 + 0.003*sl t phl 0.503 0.493 + 0.005*sl 0.498 + 0.004*sl 0.515 + 0.003*sl e to y t r 0.088 0.076 + 0.006*sl 0.074 + 0.006*sl 0.061 + 0.007*sl t f 0.084 0.072 + 0.006*sl 0.073 + 0.006*sl 0.066 + 0.006*sl t plh 0.343 0.333 + 0.005*sl 0.339 + 0.004*sl 0.351 + 0.003*sl t phl 0.556 0.544 + 0.006*sl 0.551 + 0.004*sl 0.568 + 0.003*sl f to y t r 0.090 0.078 + 0.006*sl 0.076 + 0.006*sl 0.062 + 0.007*sl t f 0.081 0.069 + 0.006*sl 0.071 + 0.006*sl 0.064 + 0.006*sl t plh 0.362 0.352 + 0.005*sl 0.358 + 0.004*sl 0.371 + 0.003*sl t phl 0.518 0.507 + 0.005*sl 0.513 + 0.004*sl 0.530 + 0.003*sl g to y t r 0.090 0.078 + 0.006*sl 0.076 + 0.006*sl 0.062 + 0.007*sl t f 0.084 0.072 + 0.006*sl 0.072 + 0.006*sl 0.065 + 0.006*sl t plh 0.363 0.353 + 0.005*sl 0.359 + 0.004*sl 0.372 + 0.003*sl t phl 0.570 0.559 + 0.005*sl 0.565 + 0.004*sl 0.582 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-205 STD111 oa33/oa33d2/oa33d4 two 3-ors into 2-nand with 1x/2x/4x drive logic symbol cell data input load (sl) oa33 oa33d2 oa33d4 abcdefabcdefabcdef 0.8 0.8 0.9 0.8 0.8 0.9 0.8 0.8 0.9 0.8 0.8 0.9 0.8 0.8 0.9 0.8 0.8 0.9 gate count oa33 oa33d2 oa33d4 2.33 3.33 4.00 d f y a c e b truth table abcdefy 000xxx1 xxx0001 other states 0
STD111 3-206 samsung asic oa33/oa33d2/oa33d4 two 3-ors into 2-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa33 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.537 0.385 + 0.076*sl 0.369 + 0.080*sl 0.350 + 0.082*sl t f 0.401 0.247 + 0.077*sl 0.242 + 0.078*sl 0.239 + 0.078*sl t plh 0.170 0.096 + 0.037*sl 0.098 + 0.037*sl 0.102 + 0.036*sl t phl 0.259 0.180 + 0.040*sl 0.185 + 0.038*sl 0.191 + 0.038*sl b to y t r 0.537 0.382 + 0.077*sl 0.370 + 0.080*sl 0.356 + 0.082*sl t f 0.461 0.303 + 0.079*sl 0.300 + 0.080*sl 0.299 + 0.080*sl t plh 0.192 0.117 + 0.037*sl 0.120 + 0.037*sl 0.125 + 0.036*sl t phl 0.302 0.223 + 0.040*sl 0.227 + 0.039*sl 0.232 + 0.038*sl c to y t r 0.533 0.376 + 0.078*sl 0.366 + 0.081*sl 0.355 + 0.082*sl t f 0.520 0.363 + 0.079*sl 0.360 + 0.079*sl 0.358 + 0.080*sl t plh 0.200 0.125 + 0.037*sl 0.128 + 0.037*sl 0.134 + 0.036*sl t phl 0.334 0.254 + 0.040*sl 0.258 + 0.039*sl 0.264 + 0.038*sl d to y t r 0.478 0.323 + 0.078*sl 0.310 + 0.081*sl 0.297 + 0.082*sl t f 0.401 0.244 + 0.078*sl 0.240 + 0.079*sl 0.237 + 0.080*sl t plh 0.200 0.128 + 0.036*sl 0.130 + 0.036*sl 0.132 + 0.035*sl t phl 0.271 0.190 + 0.040*sl 0.196 + 0.039*sl 0.202 + 0.038*sl e to y t r 0.478 0.319 + 0.079*sl 0.312 + 0.081*sl 0.302 + 0.082*sl t f 0.459 0.301 + 0.079*sl 0.299 + 0.080*sl 0.297 + 0.080*sl t plh 0.224 0.151 + 0.037*sl 0.154 + 0.036*sl 0.157 + 0.035*sl t phl 0.314 0.234 + 0.040*sl 0.238 + 0.039*sl 0.243 + 0.038*sl f to y t r 0.474 0.314 + 0.080*sl 0.309 + 0.081*sl 0.301 + 0.082*sl t f 0.520 0.363 + 0.079*sl 0.361 + 0.079*sl 0.358 + 0.080*sl t plh 0.234 0.161 + 0.037*sl 0.164 + 0.036*sl 0.168 + 0.035*sl t phl 0.346 0.266 + 0.040*sl 0.271 + 0.039*sl 0.277 + 0.038*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-207 STD111 oa33/oa33d2/oa33d4 two 3-ors into 2-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa33d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.094 0.069 + 0.013*sl 0.068 + 0.013*sl 0.052 + 0.014*sl t f 0.078 0.053 + 0.012*sl 0.057 + 0.011*sl 0.048 + 0.012*sl t plh 0.305 0.288 + 0.008*sl 0.295 + 0.007*sl 0.303 + 0.006*sl t phl 0.368 0.350 + 0.009*sl 0.358 + 0.007*sl 0.368 + 0.006*sl b to y t r 0.095 0.071 + 0.012*sl 0.066 + 0.013*sl 0.053 + 0.014*sl t f 0.080 0.056 + 0.012*sl 0.059 + 0.011*sl 0.049 + 0.012*sl t plh 0.326 0.309 + 0.008*sl 0.316 + 0.007*sl 0.324 + 0.006*sl t phl 0.420 0.402 + 0.009*sl 0.410 + 0.007*sl 0.420 + 0.006*sl c to y t r 0.095 0.071 + 0.012*sl 0.067 + 0.013*sl 0.053 + 0.014*sl t f 0.082 0.058 + 0.012*sl 0.060 + 0.011*sl 0.051 + 0.012*sl t plh 0.334 0.317 + 0.008*sl 0.324 + 0.007*sl 0.332 + 0.006*sl t phl 0.459 0.441 + 0.009*sl 0.449 + 0.007*sl 0.459 + 0.006*sl d to y t r 0.095 0.071 + 0.012*sl 0.068 + 0.013*sl 0.054 + 0.014*sl t f 0.078 0.055 + 0.011*sl 0.056 + 0.011*sl 0.048 + 0.012*sl t plh 0.332 0.315 + 0.008*sl 0.322 + 0.007*sl 0.330 + 0.006*sl t phl 0.378 0.361 + 0.009*sl 0.368 + 0.007*sl 0.378 + 0.006*sl e to y t r 0.096 0.071 + 0.013*sl 0.070 + 0.013*sl 0.053 + 0.014*sl t f 0.080 0.056 + 0.012*sl 0.058 + 0.011*sl 0.050 + 0.012*sl t plh 0.355 0.338 + 0.008*sl 0.345 + 0.007*sl 0.353 + 0.006*sl t phl 0.431 0.413 + 0.009*sl 0.420 + 0.007*sl 0.431 + 0.006*sl f to y t r 0.096 0.073 + 0.011*sl 0.067 + 0.013*sl 0.054 + 0.014*sl t f 0.082 0.060 + 0.011*sl 0.060 + 0.011*sl 0.052 + 0.012*sl t plh 0.366 0.349 + 0.008*sl 0.356 + 0.007*sl 0.364 + 0.006*sl t phl 0.471 0.453 + 0.009*sl 0.461 + 0.007*sl 0.471 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-208 samsung asic oa33/oa33d2/oa33d4 two 3-ors into 2-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa33d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.092 0.079 + 0.006*sl 0.079 + 0.006*sl 0.064 + 0.007*sl t f 0.075 0.062 + 0.007*sl 0.065 + 0.006*sl 0.058 + 0.006*sl t plh 0.337 0.327 + 0.005*sl 0.333 + 0.004*sl 0.346 + 0.003*sl t phl 0.397 0.386 + 0.005*sl 0.392 + 0.004*sl 0.408 + 0.003*sl b to y t r 0.091 0.079 + 0.006*sl 0.078 + 0.006*sl 0.065 + 0.007*sl t f 0.077 0.065 + 0.006*sl 0.066 + 0.006*sl 0.061 + 0.006*sl t plh 0.358 0.348 + 0.005*sl 0.354 + 0.004*sl 0.367 + 0.003*sl t phl 0.450 0.439 + 0.005*sl 0.445 + 0.004*sl 0.461 + 0.003*sl c to y t r 0.091 0.079 + 0.006*sl 0.078 + 0.006*sl 0.065 + 0.007*sl t f 0.080 0.067 + 0.006*sl 0.069 + 0.006*sl 0.063 + 0.006*sl t plh 0.367 0.356 + 0.005*sl 0.362 + 0.004*sl 0.376 + 0.003*sl t phl 0.489 0.478 + 0.005*sl 0.484 + 0.004*sl 0.501 + 0.003*sl d to y t r 0.093 0.082 + 0.006*sl 0.079 + 0.006*sl 0.065 + 0.007*sl t f 0.075 0.063 + 0.006*sl 0.065 + 0.006*sl 0.060 + 0.006*sl t plh 0.364 0.354 + 0.005*sl 0.360 + 0.004*sl 0.374 + 0.003*sl t phl 0.407 0.397 + 0.005*sl 0.402 + 0.004*sl 0.419 + 0.003*sl e to y t r 0.093 0.082 + 0.006*sl 0.079 + 0.006*sl 0.065 + 0.007*sl t f 0.077 0.064 + 0.006*sl 0.067 + 0.006*sl 0.060 + 0.006*sl t plh 0.387 0.377 + 0.005*sl 0.383 + 0.004*sl 0.397 + 0.003*sl t phl 0.460 0.449 + 0.005*sl 0.455 + 0.004*sl 0.471 + 0.003*sl f to y t r 0.093 0.081 + 0.006*sl 0.079 + 0.006*sl 0.065 + 0.007*sl t f 0.079 0.066 + 0.006*sl 0.069 + 0.006*sl 0.062 + 0.006*sl t plh 0.398 0.388 + 0.005*sl 0.394 + 0.004*sl 0.408 + 0.003*sl t phl 0.501 0.491 + 0.005*sl 0.496 + 0.004*sl 0.513 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-209 STD111 oa331/oa331d2/oa331d4 two 3-ors into 3-nand with 1x/2x/4x drive logic symbol cell data input load (sl) gate count oa331 oa331 abcdefg 0.8 0.9 0.9 0.8 0.9 0.9 1.1 2.67 oa331d2 oa331d2 abcdefg 0.8 0.9 0.9 0.8 0.9 0.9 1.1 3.33 oa331d4 oa331d4 abcdefg 0.8 0.9 0.9 0.8 0.9 0.9 1.1 4.00 d f y a b g c e truth table abcdefgy 000xxxx1 xxx000x1 xxxxxx01 other states 0
STD111 3-210 samsung asic oa331/oa331d2/oa331d4 two 3-ors into 3-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa331 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.583 0.428 + 0.077*sl 0.413 + 0.081*sl 0.399 + 0.083*sl t f 0.445 0.294 + 0.076*sl 0.289 + 0.077*sl 0.287 + 0.077*sl t plh 0.191 0.117 + 0.037*sl 0.118 + 0.037*sl 0.122 + 0.036*sl t phl 0.268 0.193 + 0.038*sl 0.197 + 0.037*sl 0.202 + 0.036*sl b to y t r 0.583 0.425 + 0.079*sl 0.417 + 0.081*sl 0.403 + 0.083*sl t f 0.504 0.349 + 0.077*sl 0.345 + 0.078*sl 0.344 + 0.079*sl t plh 0.213 0.138 + 0.038*sl 0.140 + 0.037*sl 0.145 + 0.036*sl t phl 0.310 0.235 + 0.038*sl 0.238 + 0.037*sl 0.242 + 0.037*sl c to y t r 0.580 0.421 + 0.080*sl 0.413 + 0.082*sl 0.403 + 0.083*sl t f 0.561 0.407 + 0.077*sl 0.403 + 0.078*sl 0.402 + 0.078*sl t plh 0.223 0.147 + 0.038*sl 0.150 + 0.037*sl 0.156 + 0.036*sl t phl 0.341 0.264 + 0.038*sl 0.268 + 0.037*sl 0.273 + 0.037*sl d to y t r 0.531 0.373 + 0.079*sl 0.364 + 0.081*sl 0.355 + 0.082*sl t f 0.444 0.291 + 0.076*sl 0.287 + 0.077*sl 0.284 + 0.078*sl t plh 0.227 0.155 + 0.036*sl 0.157 + 0.036*sl 0.159 + 0.035*sl t phl 0.287 0.210 + 0.038*sl 0.215 + 0.037*sl 0.221 + 0.037*sl e to y t r 0.533 0.373 + 0.080*sl 0.368 + 0.081*sl 0.360 + 0.082*sl t f 0.504 0.349 + 0.078*sl 0.346 + 0.078*sl 0.344 + 0.079*sl t plh 0.252 0.179 + 0.036*sl 0.181 + 0.036*sl 0.185 + 0.035*sl t phl 0.330 0.254 + 0.038*sl 0.257 + 0.037*sl 0.262 + 0.037*sl f to y t r 0.530 0.370 + 0.080*sl 0.365 + 0.082*sl 0.359 + 0.082*sl t f 0.561 0.407 + 0.077*sl 0.405 + 0.078*sl 0.402 + 0.078*sl t plh 0.262 0.189 + 0.037*sl 0.192 + 0.036*sl 0.195 + 0.035*sl t phl 0.361 0.284 + 0.038*sl 0.288 + 0.037*sl 0.294 + 0.037*sl g to y t r 0.266 0.220 + 0.023*sl 0.211 + 0.025*sl 0.193 + 0.027*sl t f 0.560 0.406 + 0.077*sl 0.404 + 0.078*sl 0.402 + 0.078*sl t plh 0.125 0.098 + 0.013*sl 0.100 + 0.013*sl 0.102 + 0.012*sl t phl 0.356 0.278 + 0.039*sl 0.283 + 0.037*sl 0.289 + 0.037*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-211 STD111 oa331/oa331d2/oa331d4 two 3-ors into 3-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa331d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.097 0.072 + 0.013*sl 0.071 + 0.013*sl 0.055 + 0.014*sl t f 0.080 0.057 + 0.012*sl 0.059 + 0.011*sl 0.051 + 0.012*sl t plh 0.336 0.318 + 0.009*sl 0.326 + 0.007*sl 0.334 + 0.006*sl t phl 0.391 0.373 + 0.009*sl 0.380 + 0.007*sl 0.391 + 0.006*sl b to y t r 0.097 0.072 + 0.013*sl 0.071 + 0.013*sl 0.055 + 0.014*sl t f 0.082 0.059 + 0.012*sl 0.060 + 0.011*sl 0.052 + 0.012*sl t plh 0.356 0.339 + 0.009*sl 0.346 + 0.007*sl 0.355 + 0.006*sl t phl 0.436 0.418 + 0.009*sl 0.426 + 0.007*sl 0.437 + 0.006*sl c to y t r 0.097 0.073 + 0.012*sl 0.069 + 0.013*sl 0.055 + 0.014*sl t f 0.084 0.062 + 0.011*sl 0.062 + 0.011*sl 0.054 + 0.012*sl t plh 0.366 0.348 + 0.009*sl 0.356 + 0.007*sl 0.364 + 0.006*sl t phl 0.473 0.455 + 0.009*sl 0.463 + 0.007*sl 0.474 + 0.006*sl d to y t r 0.099 0.074 + 0.013*sl 0.073 + 0.013*sl 0.056 + 0.014*sl t f 0.080 0.057 + 0.011*sl 0.058 + 0.011*sl 0.049 + 0.012*sl t plh 0.368 0.351 + 0.009*sl 0.358 + 0.007*sl 0.366 + 0.006*sl t phl 0.403 0.386 + 0.009*sl 0.393 + 0.007*sl 0.404 + 0.006*sl e to y t r 0.099 0.075 + 0.012*sl 0.071 + 0.013*sl 0.057 + 0.014*sl t f 0.082 0.059 + 0.012*sl 0.060 + 0.011*sl 0.052 + 0.012*sl t plh 0.391 0.374 + 0.009*sl 0.381 + 0.007*sl 0.390 + 0.006*sl t phl 0.455 0.437 + 0.009*sl 0.445 + 0.007*sl 0.456 + 0.006*sl f to y t r 0.099 0.074 + 0.013*sl 0.073 + 0.013*sl 0.056 + 0.014*sl t f 0.084 0.062 + 0.011*sl 0.062 + 0.011*sl 0.054 + 0.012*sl t plh 0.401 0.384 + 0.009*sl 0.392 + 0.007*sl 0.400 + 0.006*sl t phl 0.492 0.474 + 0.009*sl 0.482 + 0.007*sl 0.493 + 0.006*sl g to y t r 0.085 0.059 + 0.013*sl 0.057 + 0.013*sl 0.046 + 0.014*sl t f 0.085 0.061 + 0.012*sl 0.064 + 0.011*sl 0.053 + 0.012*sl t plh 0.255 0.239 + 0.008*sl 0.245 + 0.007*sl 0.252 + 0.006*sl t phl 0.488 0.470 + 0.009*sl 0.477 + 0.007*sl 0.489 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-212 samsung asic oa331/oa331d2/oa331d4 two 3-ors into 3-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa331d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.094 0.083 + 0.006*sl 0.080 + 0.006*sl 0.066 + 0.007*sl t f 0.078 0.066 + 0.006*sl 0.068 + 0.006*sl 0.062 + 0.006*sl t plh 0.366 0.355 + 0.005*sl 0.361 + 0.004*sl 0.375 + 0.003*sl t phl 0.424 0.414 + 0.005*sl 0.419 + 0.004*sl 0.436 + 0.003*sl b to y t r 0.093 0.082 + 0.006*sl 0.079 + 0.006*sl 0.067 + 0.007*sl t f 0.080 0.068 + 0.006*sl 0.070 + 0.006*sl 0.064 + 0.006*sl t plh 0.387 0.377 + 0.005*sl 0.383 + 0.004*sl 0.396 + 0.003*sl t phl 0.471 0.460 + 0.005*sl 0.466 + 0.004*sl 0.483 + 0.003*sl c to y t r 0.093 0.081 + 0.006*sl 0.081 + 0.006*sl 0.066 + 0.007*sl t f 0.083 0.070 + 0.006*sl 0.073 + 0.006*sl 0.066 + 0.006*sl t plh 0.396 0.386 + 0.005*sl 0.392 + 0.004*sl 0.406 + 0.003*sl t phl 0.508 0.497 + 0.005*sl 0.503 + 0.004*sl 0.520 + 0.003*sl d to y t r 0.095 0.083 + 0.006*sl 0.081 + 0.006*sl 0.068 + 0.007*sl t f 0.078 0.066 + 0.006*sl 0.068 + 0.006*sl 0.060 + 0.006*sl t plh 0.398 0.387 + 0.005*sl 0.394 + 0.004*sl 0.408 + 0.003*sl t phl 0.437 0.426 + 0.005*sl 0.433 + 0.004*sl 0.449 + 0.003*sl e to y t r 0.095 0.083 + 0.006*sl 0.082 + 0.006*sl 0.067 + 0.007*sl t f 0.080 0.068 + 0.006*sl 0.070 + 0.006*sl 0.064 + 0.006*sl t plh 0.422 0.411 + 0.005*sl 0.417 + 0.004*sl 0.431 + 0.003*sl t phl 0.489 0.478 + 0.005*sl 0.484 + 0.004*sl 0.501 + 0.003*sl f to y t r 0.095 0.083 + 0.006*sl 0.082 + 0.006*sl 0.068 + 0.007*sl t f 0.083 0.070 + 0.006*sl 0.073 + 0.006*sl 0.066 + 0.006*sl t plh 0.432 0.421 + 0.005*sl 0.427 + 0.004*sl 0.441 + 0.003*sl t phl 0.527 0.516 + 0.005*sl 0.522 + 0.004*sl 0.539 + 0.003*sl g to y t r 0.080 0.068 + 0.006*sl 0.067 + 0.006*sl 0.055 + 0.007*sl t f 0.082 0.070 + 0.006*sl 0.071 + 0.006*sl 0.065 + 0.006*sl t plh 0.271 0.261 + 0.005*sl 0.266 + 0.004*sl 0.277 + 0.003*sl t phl 0.523 0.512 + 0.005*sl 0.518 + 0.004*sl 0.535 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-213 STD111 oa332/oa332d2/oa332d4 two 3-ors and 2-or into 3-nand with 1x/2x/4x drive logic symbol cell data input load (sl) gate count oa332 oa332 abcdefgh 0.8 0.8 0.9 0.8 0.9 0.9 0.9 0.9 3.00 oa332d2 oa332d2 abcdefgh 0.8 0.9 0.9 0.8 0.9 0.9 0.9 0.9 4.00 oa332d4 oa332d4 abcdefgh 0.8 0.9 0.9 0.8 0.9 0.9 0.9 0.9 4.67 d f y a c g h e b truth table abcdefghy 000xxxxx1 xxx000xx1 xxxxxx001 other states 0
STD111 3-214 samsung asic oa332/oa332d2/oa332d4 two 3-ors and 2-or into 3-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa332 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.667 0.511 + 0.078*sl 0.497 + 0.081*sl 0.482 + 0.083*sl t f 0.480 0.312 + 0.084*sl 0.308 + 0.085*sl 0.307 + 0.085*sl t plh 0.209 0.134 + 0.038*sl 0.137 + 0.037*sl 0.142 + 0.036*sl t phl 0.293 0.210 + 0.042*sl 0.214 + 0.040*sl 0.219 + 0.040*sl b to y t r 0.667 0.509 + 0.079*sl 0.500 + 0.081*sl 0.487 + 0.083*sl t f 0.543 0.373 + 0.085*sl 0.370 + 0.086*sl 0.370 + 0.086*sl t plh 0.232 0.156 + 0.038*sl 0.159 + 0.037*sl 0.166 + 0.036*sl t phl 0.339 0.255 + 0.042*sl 0.259 + 0.041*sl 0.263 + 0.040*sl c to y t r 0.663 0.504 + 0.080*sl 0.496 + 0.082*sl 0.486 + 0.083*sl t f 0.605 0.436 + 0.085*sl 0.433 + 0.085*sl 0.433 + 0.085*sl t plh 0.242 0.165 + 0.038*sl 0.169 + 0.037*sl 0.177 + 0.036*sl t phl 0.373 0.289 + 0.042*sl 0.293 + 0.041*sl 0.298 + 0.040*sl d to y t r 0.615 0.457 + 0.079*sl 0.447 + 0.081*sl 0.437 + 0.082*sl t f 0.634 0.435 + 0.100*sl 0.435 + 0.100*sl 0.433 + 0.100*sl t plh 0.244 0.171 + 0.036*sl 0.173 + 0.036*sl 0.176 + 0.035*sl t phl 0.416 0.319 + 0.048*sl 0.324 + 0.047*sl 0.330 + 0.046*sl e to y t r 0.616 0.456 + 0.080*sl 0.451 + 0.081*sl 0.442 + 0.082*sl t f 0.706 0.506 + 0.100*sl 0.506 + 0.100*sl 0.506 + 0.100*sl t plh 0.269 0.196 + 0.037*sl 0.199 + 0.036*sl 0.202 + 0.035*sl t phl 0.468 0.372 + 0.048*sl 0.375 + 0.047*sl 0.380 + 0.046*sl f to y t r 0.613 0.452 + 0.080*sl 0.447 + 0.082*sl 0.441 + 0.082*sl t f 0.777 0.578 + 0.099*sl 0.579 + 0.099*sl 0.578 + 0.099*sl t plh 0.279 0.206 + 0.037*sl 0.209 + 0.036*sl 0.213 + 0.035*sl t phl 0.509 0.414 + 0.048*sl 0.417 + 0.047*sl 0.423 + 0.046*sl g to y t r 0.456 0.354 + 0.051*sl 0.344 + 0.054*sl 0.327 + 0.055*sl t f 0.702 0.505 + 0.098*sl 0.505 + 0.098*sl 0.503 + 0.098*sl t plh 0.202 0.152 + 0.025*sl 0.154 + 0.024*sl 0.158 + 0.024*sl t phl 0.468 0.372 + 0.048*sl 0.377 + 0.047*sl 0.385 + 0.046*sl h to y t r 0.450 0.345 + 0.053*sl 0.338 + 0.054*sl 0.328 + 0.055*sl t f 0.777 0.578 + 0.100*sl 0.579 + 0.099*sl 0.578 + 0.099*sl t plh 0.204 0.154 + 0.025*sl 0.156 + 0.024*sl 0.160 + 0.024*sl t phl 0.521 0.425 + 0.048*sl 0.428 + 0.047*sl 0.434 + 0.046*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-215 STD111 oa332/oa332d2/oa332d4 two 3-ors and 2-or into 3-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa332d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.099 0.075 + 0.012*sl 0.071 + 0.013*sl 0.057 + 0.014*sl t f 0.081 0.057 + 0.012*sl 0.058 + 0.011*sl 0.050 + 0.012*sl t plh 0.356 0.338 + 0.009*sl 0.346 + 0.007*sl 0.355 + 0.006*sl t phl 0.409 0.391 + 0.009*sl 0.399 + 0.007*sl 0.409 + 0.006*sl b to y t r 0.099 0.077 + 0.011*sl 0.070 + 0.013*sl 0.057 + 0.014*sl t f 0.082 0.058 + 0.012*sl 0.062 + 0.011*sl 0.050 + 0.012*sl t plh 0.377 0.360 + 0.009*sl 0.367 + 0.007*sl 0.376 + 0.006*sl t phl 0.463 0.445 + 0.009*sl 0.453 + 0.007*sl 0.464 + 0.006*sl c to y t r 0.100 0.075 + 0.012*sl 0.073 + 0.013*sl 0.057 + 0.014*sl t f 0.085 0.060 + 0.012*sl 0.065 + 0.011*sl 0.052 + 0.012*sl t plh 0.387 0.370 + 0.009*sl 0.377 + 0.007*sl 0.386 + 0.006*sl t phl 0.505 0.487 + 0.009*sl 0.494 + 0.007*sl 0.506 + 0.006*sl d to y t r 0.101 0.076 + 0.013*sl 0.075 + 0.013*sl 0.058 + 0.014*sl t f 0.086 0.063 + 0.011*sl 0.064 + 0.011*sl 0.054 + 0.012*sl t plh 0.389 0.371 + 0.009*sl 0.379 + 0.007*sl 0.388 + 0.006*sl t phl 0.540 0.522 + 0.009*sl 0.530 + 0.007*sl 0.541 + 0.006*sl e to y t r 0.101 0.076 + 0.012*sl 0.074 + 0.013*sl 0.058 + 0.014*sl t f 0.090 0.067 + 0.012*sl 0.069 + 0.011*sl 0.056 + 0.012*sl t plh 0.412 0.394 + 0.009*sl 0.402 + 0.007*sl 0.411 + 0.006*sl t phl 0.605 0.586 + 0.009*sl 0.594 + 0.007*sl 0.606 + 0.006*sl f to y t r 0.101 0.076 + 0.013*sl 0.076 + 0.013*sl 0.058 + 0.014*sl t f 0.093 0.071 + 0.011*sl 0.071 + 0.011*sl 0.060 + 0.012*sl t plh 0.423 0.406 + 0.009*sl 0.414 + 0.007*sl 0.423 + 0.006*sl t phl 0.656 0.637 + 0.009*sl 0.646 + 0.007*sl 0.658 + 0.006*sl g to y t r 0.097 0.072 + 0.013*sl 0.071 + 0.013*sl 0.054 + 0.014*sl t f 0.090 0.067 + 0.011*sl 0.068 + 0.011*sl 0.055 + 0.012*sl t plh 0.346 0.329 + 0.009*sl 0.336 + 0.007*sl 0.344 + 0.006*sl t phl 0.604 0.585 + 0.009*sl 0.593 + 0.007*sl 0.605 + 0.006*sl h to y t r 0.097 0.072 + 0.012*sl 0.070 + 0.013*sl 0.054 + 0.014*sl t f 0.093 0.070 + 0.012*sl 0.072 + 0.011*sl 0.060 + 0.012*sl t plh 0.348 0.331 + 0.009*sl 0.339 + 0.007*sl 0.346 + 0.006*sl t phl 0.668 0.649 + 0.009*sl 0.657 + 0.007*sl 0.669 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-216 samsung asic oa332/oa332d2/oa332d4 two 3-ors and 2-or into 3-nand with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa332d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.099 0.087 + 0.006*sl 0.085 + 0.006*sl 0.070 + 0.007*sl t f 0.078 0.066 + 0.006*sl 0.068 + 0.006*sl 0.062 + 0.006*sl t plh 0.391 0.381 + 0.005*sl 0.387 + 0.004*sl 0.402 + 0.003*sl t phl 0.441 0.430 + 0.005*sl 0.436 + 0.004*sl 0.453 + 0.003*sl b to y t r 0.098 0.087 + 0.006*sl 0.084 + 0.006*sl 0.070 + 0.007*sl t f 0.081 0.070 + 0.006*sl 0.070 + 0.006*sl 0.064 + 0.006*sl t plh 0.413 0.403 + 0.005*sl 0.409 + 0.004*sl 0.424 + 0.003*sl t phl 0.496 0.485 + 0.006*sl 0.491 + 0.004*sl 0.508 + 0.003*sl c to y t r 0.098 0.085 + 0.006*sl 0.085 + 0.006*sl 0.069 + 0.007*sl t f 0.084 0.073 + 0.005*sl 0.072 + 0.006*sl 0.066 + 0.006*sl t plh 0.423 0.412 + 0.005*sl 0.419 + 0.004*sl 0.434 + 0.003*sl t phl 0.538 0.527 + 0.006*sl 0.533 + 0.004*sl 0.550 + 0.003*sl d to y t r 0.100 0.088 + 0.006*sl 0.086 + 0.006*sl 0.071 + 0.007*sl t f 0.085 0.073 + 0.006*sl 0.075 + 0.006*sl 0.067 + 0.006*sl t plh 0.425 0.414 + 0.005*sl 0.420 + 0.004*sl 0.435 + 0.003*sl t phl 0.574 0.563 + 0.006*sl 0.570 + 0.004*sl 0.587 + 0.003*sl e to y t r 0.100 0.088 + 0.006*sl 0.087 + 0.006*sl 0.072 + 0.007*sl t f 0.089 0.078 + 0.005*sl 0.078 + 0.006*sl 0.071 + 0.006*sl t plh 0.448 0.437 + 0.005*sl 0.444 + 0.004*sl 0.458 + 0.003*sl t phl 0.639 0.628 + 0.006*sl 0.634 + 0.004*sl 0.652 + 0.003*sl f to y t r 0.100 0.088 + 0.006*sl 0.086 + 0.006*sl 0.071 + 0.007*sl t f 0.092 0.080 + 0.006*sl 0.083 + 0.005*sl 0.074 + 0.006*sl t plh 0.459 0.448 + 0.005*sl 0.455 + 0.004*sl 0.470 + 0.003*sl t phl 0.691 0.680 + 0.006*sl 0.686 + 0.004*sl 0.704 + 0.003*sl g to y t r 0.094 0.083 + 0.006*sl 0.080 + 0.006*sl 0.067 + 0.007*sl t f 0.089 0.078 + 0.005*sl 0.077 + 0.006*sl 0.070 + 0.006*sl t plh 0.376 0.366 + 0.005*sl 0.372 + 0.004*sl 0.386 + 0.003*sl t phl 0.641 0.630 + 0.006*sl 0.637 + 0.004*sl 0.654 + 0.003*sl h to y t r 0.094 0.083 + 0.006*sl 0.081 + 0.006*sl 0.067 + 0.007*sl t f 0.093 0.083 + 0.005*sl 0.081 + 0.006*sl 0.074 + 0.006*sl t plh 0.378 0.368 + 0.005*sl 0.374 + 0.004*sl 0.388 + 0.003*sl t phl 0.702 0.690 + 0.006*sl 0.697 + 0.004*sl 0.715 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-217 STD111 oa4111/oa4111d2 4-or into 4-nand with 1x/2x drive logic symbol cell data input load (sl) gate count oa4111 oa4111 abcdefg 0.9 0.9 0.9 1.0 0.8 0.8 0.9 2.67 oa4111d2 oa4111d2 abcdefg 0.9 0.9 0.9 1.0 0.8 0.8 0.9 3.67 c d y a b f g e truth table abcdefgy 0000xxx1 xxxx0xx1 xxxxx0x1 xxxxxx01 other states 0
STD111 3-218 samsung asic oa4111/oa4111d2 4-or into 4-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa4111 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.544 0.329 + 0.107*sl 0.321 + 0.110*sl 0.320 + 0.110*sl t f 0.328 0.192 + 0.068*sl 0.184 + 0.070*sl 0.176 + 0.071*sl t plh 0.215 0.121 + 0.047*sl 0.120 + 0.047*sl 0.120 + 0.047*sl t phl 0.177 0.113 + 0.032*sl 0.111 + 0.032*sl 0.112 + 0.032*sl b to y t r 0.557 0.343 + 0.107*sl 0.337 + 0.109*sl 0.332 + 0.109*sl t f 0.380 0.245 + 0.068*sl 0.236 + 0.070*sl 0.230 + 0.071*sl t plh 0.257 0.161 + 0.048*sl 0.163 + 0.047*sl 0.165 + 0.047*sl t phl 0.210 0.145 + 0.033*sl 0.145 + 0.032*sl 0.146 + 0.032*sl c to y t r 0.558 0.344 + 0.107*sl 0.337 + 0.109*sl 0.332 + 0.109*sl t f 0.439 0.305 + 0.067*sl 0.296 + 0.070*sl 0.287 + 0.071*sl t plh 0.287 0.190 + 0.048*sl 0.193 + 0.048*sl 0.197 + 0.047*sl t phl 0.235 0.167 + 0.034*sl 0.171 + 0.033*sl 0.175 + 0.032*sl d to y t r 0.556 0.341 + 0.107*sl 0.336 + 0.109*sl 0.332 + 0.109*sl t f 0.491 0.359 + 0.066*sl 0.351 + 0.068*sl 0.341 + 0.069*sl t plh 0.299 0.202 + 0.048*sl 0.205 + 0.048*sl 0.209 + 0.047*sl t phl 0.246 0.176 + 0.035*sl 0.183 + 0.033*sl 0.192 + 0.032*sl e to y t r 0.322 0.233 + 0.045*sl 0.226 + 0.046*sl 0.214 + 0.048*sl t f 0.488 0.353 + 0.068*sl 0.350 + 0.068*sl 0.343 + 0.069*sl t plh 0.178 0.136 + 0.021*sl 0.137 + 0.021*sl 0.139 + 0.021*sl t phl 0.272 0.202 + 0.035*sl 0.208 + 0.033*sl 0.217 + 0.032*sl f to y t r 0.344 0.255 + 0.044*sl 0.248 + 0.046*sl 0.236 + 0.048*sl t f 0.487 0.352 + 0.068*sl 0.349 + 0.068*sl 0.343 + 0.069*sl t plh 0.190 0.148 + 0.021*sl 0.149 + 0.021*sl 0.151 + 0.021*sl t phl 0.279 0.209 + 0.035*sl 0.216 + 0.033*sl 0.225 + 0.032*sl g to y t r 0.368 0.280 + 0.044*sl 0.272 + 0.046*sl 0.259 + 0.048*sl t f 0.486 0.350 + 0.068*sl 0.347 + 0.069*sl 0.343 + 0.069*sl t plh 0.202 0.159 + 0.021*sl 0.160 + 0.021*sl 0.163 + 0.021*sl t phl 0.283 0.212 + 0.035*sl 0.219 + 0.033*sl 0.229 + 0.032*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-219 STD111 oa4111/oa4111d2 4-or into 4-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oa4111d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.091 0.065 + 0.013*sl 0.066 + 0.013*sl 0.050 + 0.014*sl t f 0.076 0.052 + 0.012*sl 0.055 + 0.011*sl 0.047 + 0.012*sl t plh 0.332 0.315 + 0.008*sl 0.322 + 0.007*sl 0.329 + 0.006*sl t phl 0.286 0.267 + 0.009*sl 0.275 + 0.007*sl 0.286 + 0.006*sl b to y t r 0.091 0.067 + 0.012*sl 0.062 + 0.013*sl 0.050 + 0.014*sl t f 0.078 0.055 + 0.011*sl 0.056 + 0.011*sl 0.048 + 0.012*sl t plh 0.373 0.356 + 0.008*sl 0.363 + 0.007*sl 0.370 + 0.006*sl t phl 0.327 0.309 + 0.009*sl 0.316 + 0.007*sl 0.327 + 0.006*sl c to y t r 0.092 0.066 + 0.013*sl 0.065 + 0.013*sl 0.050 + 0.014*sl t f 0.080 0.056 + 0.012*sl 0.059 + 0.011*sl 0.050 + 0.012*sl t plh 0.403 0.386 + 0.008*sl 0.393 + 0.007*sl 0.400 + 0.006*sl t phl 0.359 0.341 + 0.009*sl 0.349 + 0.007*sl 0.360 + 0.006*sl d to y t r 0.091 0.067 + 0.012*sl 0.064 + 0.013*sl 0.050 + 0.014*sl t f 0.082 0.059 + 0.012*sl 0.061 + 0.011*sl 0.052 + 0.012*sl t plh 0.415 0.398 + 0.008*sl 0.405 + 0.007*sl 0.412 + 0.006*sl t phl 0.376 0.358 + 0.009*sl 0.366 + 0.007*sl 0.377 + 0.006*sl e to y t r 0.086 0.061 + 0.013*sl 0.058 + 0.013*sl 0.046 + 0.014*sl t f 0.082 0.057 + 0.012*sl 0.062 + 0.011*sl 0.051 + 0.012*sl t plh 0.308 0.291 + 0.008*sl 0.298 + 0.007*sl 0.304 + 0.006*sl t phl 0.401 0.383 + 0.009*sl 0.391 + 0.007*sl 0.402 + 0.006*sl f to y t r 0.088 0.062 + 0.013*sl 0.062 + 0.013*sl 0.047 + 0.014*sl t f 0.082 0.060 + 0.011*sl 0.060 + 0.011*sl 0.052 + 0.012*sl t plh 0.323 0.307 + 0.008*sl 0.313 + 0.007*sl 0.320 + 0.006*sl t phl 0.409 0.390 + 0.009*sl 0.398 + 0.007*sl 0.409 + 0.006*sl g to y t r 0.088 0.064 + 0.012*sl 0.060 + 0.013*sl 0.048 + 0.014*sl t f 0.082 0.060 + 0.011*sl 0.060 + 0.011*sl 0.052 + 0.012*sl t plh 0.337 0.321 + 0.008*sl 0.327 + 0.007*sl 0.334 + 0.006*sl t phl 0.412 0.394 + 0.009*sl 0.402 + 0.007*sl 0.413 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-220 samsung asic scg1/scg1d2 2-nand and two (2-and into 2-nor)s into 3-nand with 1x/2x drive logic symbol cell data input load (sl) gate count scg1 scg1 abcdefgh 3.67 0.8 0.9 0.8 0.8 0.8 0.8 0.8 0.8 scg1d2 scg1d2 abcdefgh 4.67 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 c d e a b f g h y truth table abcdefghy 11xxxxxx1 xx11xxxx1 xxxx1xxx1 xxxxx11x1 xxxxxxx11 other states 0
samsung asic 3-221 STD111 scg1/scg1d2 2-nand and two (2-and into 2-nor)s into 3-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg1 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.170 0.080 + 0.045*sl 0.076 + 0.046*sl 0.071 + 0.046*sl t f 0.186 0.093 + 0.046*sl 0.089 + 0.048*sl 0.084 + 0.048*sl t plh 0.168 0.126 + 0.021*sl 0.129 + 0.020*sl 0.131 + 0.020*sl t phl 0.175 0.129 + 0.023*sl 0.132 + 0.022*sl 0.132 + 0.022*sl b to y t r 0.170 0.081 + 0.045*sl 0.076 + 0.046*sl 0.071 + 0.046*sl t f 0.188 0.096 + 0.046*sl 0.090 + 0.048*sl 0.085 + 0.048*sl t plh 0.164 0.122 + 0.021*sl 0.126 + 0.020*sl 0.127 + 0.020*sl t phl 0.188 0.142 + 0.023*sl 0.145 + 0.022*sl 0.145 + 0.022*sl c to y t r 0.193 0.106 + 0.044*sl 0.102 + 0.045*sl 0.094 + 0.045*sl t f 0.195 0.102 + 0.047*sl 0.100 + 0.047*sl 0.094 + 0.048*sl t plh 0.205 0.163 + 0.021*sl 0.167 + 0.020*sl 0.168 + 0.020*sl t phl 0.209 0.161 + 0.024*sl 0.167 + 0.023*sl 0.170 + 0.022*sl d to y t r 0.193 0.107 + 0.043*sl 0.102 + 0.045*sl 0.094 + 0.045*sl t f 0.198 0.106 + 0.046*sl 0.103 + 0.047*sl 0.095 + 0.048*sl t plh 0.199 0.158 + 0.021*sl 0.161 + 0.020*sl 0.163 + 0.020*sl t phl 0.225 0.177 + 0.024*sl 0.183 + 0.023*sl 0.187 + 0.022*sl e to y t r 0.190 0.102 + 0.044*sl 0.098 + 0.045*sl 0.092 + 0.046*sl t f 0.199 0.107 + 0.046*sl 0.103 + 0.047*sl 0.096 + 0.048*sl t plh 0.205 0.164 + 0.021*sl 0.167 + 0.020*sl 0.168 + 0.020*sl t phl 0.240 0.192 + 0.024*sl 0.198 + 0.023*sl 0.201 + 0.022*sl f to y t r 0.214 0.129 + 0.043*sl 0.125 + 0.044*sl 0.116 + 0.045*sl t f 0.192 0.098 + 0.047*sl 0.097 + 0.047*sl 0.092 + 0.048*sl t plh 0.218 0.177 + 0.021*sl 0.180 + 0.020*sl 0.182 + 0.020*sl t phl 0.216 0.168 + 0.024*sl 0.173 + 0.023*sl 0.177 + 0.022*sl g to y t r 0.215 0.130 + 0.043*sl 0.125 + 0.044*sl 0.116 + 0.045*sl t f 0.196 0.103 + 0.046*sl 0.100 + 0.047*sl 0.094 + 0.048*sl t plh 0.212 0.170 + 0.021*sl 0.174 + 0.020*sl 0.176 + 0.020*sl t phl 0.230 0.182 + 0.024*sl 0.187 + 0.023*sl 0.191 + 0.022*sl h to y t r 0.211 0.126 + 0.043*sl 0.120 + 0.044*sl 0.113 + 0.045*sl t f 0.196 0.104 + 0.046*sl 0.100 + 0.047*sl 0.094 + 0.048*sl t plh 0.217 0.176 + 0.020*sl 0.179 + 0.020*sl 0.180 + 0.020*sl t phl 0.246 0.198 + 0.024*sl 0.203 + 0.023*sl 0.206 + 0.022*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-222 samsung asic scg1/scg1d2 2-nand and two (2-and into 2-nor)s into 3-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg1d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.119 0.077 + 0.021*sl 0.073 + 0.022*sl 0.065 + 0.023*sl t f 0.131 0.085 + 0.023*sl 0.084 + 0.023*sl 0.078 + 0.024*sl t plh 0.164 0.142 + 0.011*sl 0.147 + 0.010*sl 0.151 + 0.010*sl t phl 0.166 0.141 + 0.012*sl 0.146 + 0.011*sl 0.148 + 0.011*sl b to y t r 0.118 0.075 + 0.022*sl 0.074 + 0.022*sl 0.065 + 0.023*sl t f 0.134 0.089 + 0.023*sl 0.087 + 0.023*sl 0.079 + 0.024*sl t plh 0.159 0.135 + 0.012*sl 0.141 + 0.010*sl 0.146 + 0.010*sl t phl 0.177 0.152 + 0.012*sl 0.157 + 0.011*sl 0.159 + 0.011*sl c to y t r 0.153 0.112 + 0.021*sl 0.107 + 0.022*sl 0.095 + 0.023*sl t f 0.148 0.102 + 0.023*sl 0.102 + 0.023*sl 0.094 + 0.024*sl t plh 0.215 0.192 + 0.012*sl 0.197 + 0.010*sl 0.203 + 0.010*sl t phl 0.210 0.183 + 0.013*sl 0.190 + 0.012*sl 0.199 + 0.011*sl d to y t r 0.153 0.111 + 0.021*sl 0.107 + 0.022*sl 0.096 + 0.023*sl t f 0.152 0.107 + 0.023*sl 0.107 + 0.023*sl 0.096 + 0.024*sl t plh 0.208 0.185 + 0.012*sl 0.190 + 0.010*sl 0.196 + 0.010*sl t phl 0.224 0.197 + 0.014*sl 0.204 + 0.012*sl 0.214 + 0.011*sl e to y t r 0.143 0.102 + 0.021*sl 0.097 + 0.022*sl 0.086 + 0.023*sl t f 0.153 0.109 + 0.022*sl 0.106 + 0.023*sl 0.096 + 0.024*sl t plh 0.201 0.179 + 0.011*sl 0.182 + 0.010*sl 0.185 + 0.010*sl t phl 0.241 0.214 + 0.013*sl 0.220 + 0.012*sl 0.230 + 0.011*sl f to y t r 0.180 0.138 + 0.021*sl 0.134 + 0.022*sl 0.120 + 0.023*sl t f 0.147 0.102 + 0.023*sl 0.099 + 0.023*sl 0.093 + 0.024*sl t plh 0.232 0.208 + 0.012*sl 0.213 + 0.010*sl 0.219 + 0.010*sl t phl 0.219 0.193 + 0.013*sl 0.198 + 0.012*sl 0.207 + 0.011*sl g to y t r 0.180 0.138 + 0.021*sl 0.134 + 0.022*sl 0.120 + 0.023*sl t f 0.151 0.107 + 0.022*sl 0.103 + 0.023*sl 0.096 + 0.024*sl t plh 0.226 0.203 + 0.012*sl 0.207 + 0.010*sl 0.213 + 0.010*sl t phl 0.233 0.207 + 0.013*sl 0.212 + 0.012*sl 0.222 + 0.011*sl h to y t r 0.167 0.126 + 0.021*sl 0.120 + 0.022*sl 0.110 + 0.023*sl t f 0.151 0.107 + 0.022*sl 0.104 + 0.023*sl 0.095 + 0.024*sl t plh 0.214 0.192 + 0.011*sl 0.195 + 0.010*sl 0.199 + 0.010*sl t phl 0.250 0.223 + 0.013*sl 0.229 + 0.012*sl 0.239 + 0.011*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-223 STD111 scg2/scg2d2 two 2-ands into 2-or with 1x/2x drive logic symbol cell data input load (sl) gate count scg2 scg2d2 scg2 scg2d2 abcdabcd 0.8 0.9 0.9 0.9 0.8 0.9 0.9 0.9 2.00 2.00 c d a b y truth table abcdy 11xx1 xx111 other states 0
STD111 3-224 samsung asic scg2/scg2d2 two 2-ands into 2-or with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg2 scg2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.118 0.066 + 0.026*sl 0.062 + 0.027*sl 0.056 + 0.028*sl t f 0.116 0.068 + 0.024*sl 0.072 + 0.023*sl 0.069 + 0.023*sl t plh 0.161 0.131 + 0.015*sl 0.139 + 0.013*sl 0.146 + 0.012*sl t phl 0.200 0.165 + 0.017*sl 0.177 + 0.014*sl 0.190 + 0.013*sl b to y t r 0.119 0.068 + 0.026*sl 0.062 + 0.027*sl 0.056 + 0.028*sl t f 0.123 0.076 + 0.023*sl 0.080 + 0.022*sl 0.075 + 0.023*sl t plh 0.155 0.125 + 0.015*sl 0.133 + 0.013*sl 0.140 + 0.012*sl t phl 0.218 0.183 + 0.017*sl 0.195 + 0.014*sl 0.209 + 0.013*sl c to y t r 0.122 0.070 + 0.026*sl 0.067 + 0.027*sl 0.058 + 0.028*sl t f 0.117 0.070 + 0.024*sl 0.074 + 0.023*sl 0.069 + 0.023*sl t plh 0.201 0.170 + 0.015*sl 0.179 + 0.013*sl 0.185 + 0.012*sl t phl 0.219 0.185 + 0.017*sl 0.196 + 0.014*sl 0.209 + 0.013*sl d to y t r 0.123 0.071 + 0.026*sl 0.067 + 0.027*sl 0.059 + 0.028*sl t f 0.122 0.076 + 0.023*sl 0.079 + 0.022*sl 0.074 + 0.023*sl t plh 0.193 0.163 + 0.015*sl 0.171 + 0.013*sl 0.177 + 0.012*sl t phl 0.236 0.201 + 0.018*sl 0.213 + 0.014*sl 0.227 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.094 0.067 + 0.013*sl 0.066 + 0.014*sl 0.063 + 0.014*sl t f 0.104 0.078 + 0.013*sl 0.082 + 0.012*sl 0.083 + 0.012*sl t plh 0.172 0.154 + 0.009*sl 0.162 + 0.007*sl 0.176 + 0.006*sl t phl 0.209 0.187 + 0.011*sl 0.198 + 0.008*sl 0.220 + 0.007*sl b to y t r 0.097 0.071 + 0.013*sl 0.068 + 0.013*sl 0.063 + 0.014*sl t f 0.109 0.083 + 0.013*sl 0.089 + 0.012*sl 0.089 + 0.012*sl t plh 0.166 0.146 + 0.010*sl 0.156 + 0.007*sl 0.170 + 0.006*sl t phl 0.226 0.203 + 0.012*sl 0.216 + 0.008*sl 0.239 + 0.007*sl c to y t r 0.102 0.075 + 0.014*sl 0.077 + 0.013*sl 0.067 + 0.014*sl t f 0.104 0.078 + 0.013*sl 0.083 + 0.012*sl 0.082 + 0.012*sl t plh 0.208 0.189 + 0.010*sl 0.198 + 0.007*sl 0.213 + 0.006*sl t phl 0.227 0.205 + 0.011*sl 0.216 + 0.008*sl 0.238 + 0.007*sl d to y t r 0.102 0.075 + 0.013*sl 0.076 + 0.013*sl 0.067 + 0.014*sl t f 0.110 0.084 + 0.013*sl 0.089 + 0.012*sl 0.090 + 0.012*sl t plh 0.201 0.182 + 0.010*sl 0.191 + 0.007*sl 0.206 + 0.006*sl t phl 0.242 0.219 + 0.011*sl 0.232 + 0.008*sl 0.255 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-225 STD111 scg3/scg3d2 two 2-nands into 3-nand with 1x/2x drive logic symbol cell data input load (sl) gate count scg3 scg3d2 scg3 scg3d2 abcdeabcde 0.8 0.8 0.8 0.8 0.9 0.8 0.9 0.8 0.8 1.9 2.67 3.33 a b y c d e truth table abcdey 11xxx1 xx11x1 xxxx01 other states 0
STD111 3-226 samsung asic scg3/scg3d2 two 2-nands into 3-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.167 0.080 + 0.043*sl 0.076 + 0.045*sl 0.071 + 0.045*sl t f 0.185 0.093 + 0.046*sl 0.089 + 0.047*sl 0.084 + 0.048*sl t plh 0.165 0.124 + 0.021*sl 0.127 + 0.020*sl 0.128 + 0.020*sl t phl 0.173 0.128 + 0.023*sl 0.130 + 0.022*sl 0.131 + 0.022*sl b to y t r 0.167 0.080 + 0.043*sl 0.076 + 0.045*sl 0.070 + 0.045*sl t f 0.187 0.096 + 0.045*sl 0.090 + 0.047*sl 0.085 + 0.047*sl t plh 0.161 0.119 + 0.021*sl 0.123 + 0.020*sl 0.124 + 0.020*sl t phl 0.188 0.142 + 0.023*sl 0.145 + 0.022*sl 0.146 + 0.022*sl c to y t r 0.191 0.102 + 0.044*sl 0.098 + 0.045*sl 0.092 + 0.046*sl t f 0.185 0.093 + 0.046*sl 0.089 + 0.047*sl 0.085 + 0.047*sl t plh 0.180 0.139 + 0.021*sl 0.141 + 0.020*sl 0.142 + 0.020*sl t phl 0.183 0.137 + 0.023*sl 0.140 + 0.022*sl 0.142 + 0.022*sl d to y t r 0.191 0.103 + 0.044*sl 0.098 + 0.045*sl 0.092 + 0.046*sl t f 0.186 0.093 + 0.046*sl 0.091 + 0.047*sl 0.086 + 0.047*sl t plh 0.176 0.134 + 0.021*sl 0.137 + 0.020*sl 0.138 + 0.020*sl t phl 0.197 0.150 + 0.023*sl 0.154 + 0.022*sl 0.155 + 0.022*sl e to y t r 0.225 0.146 + 0.040*sl 0.134 + 0.043*sl 0.116 + 0.045*sl t f 0.193 0.104 + 0.045*sl 0.096 + 0.047*sl 0.089 + 0.047*sl t plh 0.137 0.098 + 0.020*sl 0.099 + 0.019*sl 0.099 + 0.019*sl t phl 0.110 0.064 + 0.023*sl 0.068 + 0.022*sl 0.068 + 0.022*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-227 STD111 scg3/scg3d2 two 2-nands into 3-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.120 0.077 + 0.021*sl 0.074 + 0.022*sl 0.066 + 0.023*sl t f 0.132 0.087 + 0.023*sl 0.085 + 0.023*sl 0.078 + 0.024*sl t plh 0.166 0.142 + 0.012*sl 0.148 + 0.010*sl 0.152 + 0.010*sl t phl 0.165 0.140 + 0.012*sl 0.144 + 0.011*sl 0.147 + 0.011*sl b to y t r 0.120 0.077 + 0.022*sl 0.074 + 0.022*sl 0.066 + 0.023*sl t f 0.135 0.090 + 0.023*sl 0.088 + 0.023*sl 0.079 + 0.024*sl t plh 0.160 0.136 + 0.012*sl 0.142 + 0.010*sl 0.147 + 0.010*sl t phl 0.176 0.152 + 0.012*sl 0.156 + 0.011*sl 0.159 + 0.011*sl c to y t r 0.145 0.102 + 0.021*sl 0.098 + 0.022*sl 0.089 + 0.023*sl t f 0.132 0.087 + 0.023*sl 0.085 + 0.023*sl 0.080 + 0.024*sl t plh 0.183 0.160 + 0.011*sl 0.164 + 0.010*sl 0.168 + 0.010*sl t phl 0.176 0.150 + 0.013*sl 0.156 + 0.011*sl 0.160 + 0.011*sl d to y t r 0.145 0.104 + 0.021*sl 0.098 + 0.022*sl 0.089 + 0.023*sl t f 0.135 0.089 + 0.023*sl 0.087 + 0.023*sl 0.081 + 0.024*sl t plh 0.177 0.154 + 0.011*sl 0.158 + 0.010*sl 0.162 + 0.010*sl t phl 0.188 0.163 + 0.013*sl 0.168 + 0.011*sl 0.173 + 0.011*sl e to y t r 0.179 0.141 + 0.019*sl 0.133 + 0.021*sl 0.110 + 0.022*sl t f 0.139 0.096 + 0.022*sl 0.090 + 0.023*sl 0.081 + 0.024*sl t plh 0.113 0.092 + 0.011*sl 0.095 + 0.010*sl 0.095 + 0.010*sl t phl 0.082 0.057 + 0.013*sl 0.063 + 0.011*sl 0.066 + 0.011*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-228 samsung asic scg4/scg4d2 two (two 2-ands into 2-nor)s into 2-nand with 1x/2x drive logic symbol cell data input load (sl) gate count scg4 scg4 abcdefgh 3.67 0.8 0.9 0.9 0.9 0.8 0.8 0.9 0.9 scg4d2 scg4d2 abcdefgh 4.67 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 c d a b g h e f y truth table abcdefgh y 11xxxxxx 1 xx11xxxx 1 xxxx11xx 1 xxxxxx111 other states 0
samsung asic 3-229 STD111 scg4/scg4d2 two (two 2-ands into 2-nor)s into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.138 0.072 + 0.033*sl 0.070 + 0.033*sl 0.063 + 0.034*sl t f 0.148 0.083 + 0.033*sl 0.084 + 0.032*sl 0.079 + 0.033*sl t plh 0.179 0.144 + 0.018*sl 0.152 + 0.016*sl 0.157 + 0.015*sl t phl 0.211 0.171 + 0.020*sl 0.182 + 0.017*sl 0.192 + 0.016*sl b to y t r 0.138 0.074 + 0.032*sl 0.070 + 0.033*sl 0.063 + 0.034*sl t f 0.153 0.089 + 0.032*sl 0.090 + 0.032*sl 0.084 + 0.033*sl t plh 0.173 0.137 + 0.018*sl 0.146 + 0.016*sl 0.151 + 0.015*sl t phl 0.228 0.188 + 0.020*sl 0.199 + 0.017*sl 0.209 + 0.016*sl c to y t r 0.142 0.078 + 0.032*sl 0.073 + 0.033*sl 0.065 + 0.034*sl t f 0.149 0.084 + 0.032*sl 0.085 + 0.032*sl 0.080 + 0.033*sl t plh 0.220 0.184 + 0.018*sl 0.192 + 0.016*sl 0.197 + 0.015*sl t phl 0.231 0.192 + 0.020*sl 0.202 + 0.017*sl 0.212 + 0.016*sl d to y t r 0.144 0.081 + 0.032*sl 0.075 + 0.033*sl 0.065 + 0.034*sl t f 0.154 0.090 + 0.032*sl 0.090 + 0.032*sl 0.084 + 0.033*sl t plh 0.211 0.176 + 0.018*sl 0.184 + 0.016*sl 0.189 + 0.015*sl t phl 0.247 0.207 + 0.020*sl 0.218 + 0.017*sl 0.228 + 0.016*sl e to y t r 0.156 0.091 + 0.032*sl 0.087 + 0.033*sl 0.079 + 0.034*sl t f 0.140 0.076 + 0.032*sl 0.074 + 0.032*sl 0.068 + 0.033*sl t plh 0.189 0.155 + 0.017*sl 0.161 + 0.015*sl 0.164 + 0.015*sl t phl 0.204 0.167 + 0.019*sl 0.174 + 0.017*sl 0.180 + 0.016*sl f to y t r 0.156 0.091 + 0.032*sl 0.086 + 0.034*sl 0.079 + 0.034*sl t f 0.145 0.083 + 0.031*sl 0.079 + 0.032*sl 0.071 + 0.033*sl t plh 0.183 0.148 + 0.017*sl 0.154 + 0.015*sl 0.158 + 0.015*sl t phl 0.220 0.183 + 0.019*sl 0.190 + 0.017*sl 0.197 + 0.016*sl g to y t r 0.165 0.101 + 0.032*sl 0.097 + 0.033*sl 0.086 + 0.034*sl t f 0.141 0.078 + 0.031*sl 0.074 + 0.032*sl 0.069 + 0.033*sl t plh 0.223 0.188 + 0.017*sl 0.195 + 0.016*sl 0.200 + 0.015*sl t phl 0.224 0.186 + 0.019*sl 0.194 + 0.017*sl 0.200 + 0.016*sl h to y t r 0.166 0.102 + 0.032*sl 0.097 + 0.033*sl 0.088 + 0.034*sl t f 0.146 0.084 + 0.031*sl 0.080 + 0.032*sl 0.072 + 0.033*sl t plh 0.217 0.182 + 0.018*sl 0.189 + 0.016*sl 0.194 + 0.015*sl t phl 0.240 0.202 + 0.019*sl 0.210 + 0.017*sl 0.217 + 0.016*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-230 samsung asic scg4/scg4d2 two (two 2-ands into 2-nor)s into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.109 0.076 + 0.017*sl 0.076 + 0.016*sl 0.068 + 0.017*sl t f 0.126 0.094 + 0.016*sl 0.094 + 0.016*sl 0.093 + 0.016*sl t plh 0.185 0.165 + 0.010*sl 0.172 + 0.008*sl 0.184 + 0.008*sl t phl 0.216 0.192 + 0.012*sl 0.202 + 0.009*sl 0.221 + 0.008*sl b to y t r 0.109 0.076 + 0.017*sl 0.077 + 0.016*sl 0.068 + 0.017*sl t f 0.133 0.102 + 0.016*sl 0.100 + 0.016*sl 0.098 + 0.016*sl t plh 0.179 0.158 + 0.010*sl 0.165 + 0.008*sl 0.178 + 0.008*sl t phl 0.234 0.209 + 0.012*sl 0.220 + 0.010*sl 0.239 + 0.008*sl c to y t r 0.120 0.088 + 0.016*sl 0.087 + 0.016*sl 0.075 + 0.017*sl t f 0.127 0.095 + 0.016*sl 0.095 + 0.016*sl 0.093 + 0.016*sl t plh 0.232 0.211 + 0.011*sl 0.219 + 0.008*sl 0.231 + 0.008*sl t phl 0.246 0.222 + 0.012*sl 0.232 + 0.009*sl 0.251 + 0.008*sl d to y t r 0.120 0.089 + 0.015*sl 0.086 + 0.016*sl 0.074 + 0.017*sl t f 0.135 0.103 + 0.016*sl 0.103 + 0.016*sl 0.099 + 0.016*sl t plh 0.225 0.205 + 0.010*sl 0.212 + 0.008*sl 0.225 + 0.008*sl t phl 0.263 0.238 + 0.012*sl 0.248 + 0.010*sl 0.268 + 0.008*sl e to y t r 0.130 0.098 + 0.016*sl 0.098 + 0.016*sl 0.086 + 0.017*sl t f 0.122 0.092 + 0.015*sl 0.088 + 0.016*sl 0.083 + 0.016*sl t plh 0.199 0.180 + 0.010*sl 0.185 + 0.008*sl 0.195 + 0.008*sl t phl 0.217 0.194 + 0.011*sl 0.203 + 0.009*sl 0.216 + 0.008*sl f to y t r 0.130 0.098 + 0.016*sl 0.098 + 0.016*sl 0.087 + 0.017*sl t f 0.129 0.099 + 0.015*sl 0.095 + 0.016*sl 0.088 + 0.016*sl t plh 0.193 0.174 + 0.010*sl 0.179 + 0.008*sl 0.189 + 0.008*sl t phl 0.233 0.210 + 0.012*sl 0.219 + 0.009*sl 0.233 + 0.008*sl g to y t r 0.144 0.112 + 0.016*sl 0.112 + 0.016*sl 0.101 + 0.017*sl t f 0.123 0.093 + 0.015*sl 0.090 + 0.016*sl 0.083 + 0.016*sl t plh 0.241 0.221 + 0.010*sl 0.227 + 0.008*sl 0.239 + 0.008*sl t phl 0.247 0.224 + 0.011*sl 0.232 + 0.009*sl 0.246 + 0.008*sl h to y t r 0.145 0.114 + 0.016*sl 0.113 + 0.016*sl 0.100 + 0.017*sl t f 0.130 0.100 + 0.015*sl 0.097 + 0.016*sl 0.088 + 0.016*sl t plh 0.235 0.215 + 0.010*sl 0.221 + 0.008*sl 0.233 + 0.008*sl t phl 0.262 0.238 + 0.012*sl 0.248 + 0.009*sl 0.262 + 0.008*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-231 STD111 scg5/scg5d2 three 2-ands into 3-or with 1x/2x drive logic symbol cell data input load (sl) gate count scg5 scg5 abcdef 2.67 0.8 0.8 0.8 0.8 0.8 0.8 scg5d2 scg5d2 abcdef 3.00 0.8 0.8 0.8 0.8 0.8 0.8 a b y c d e f truth table abcdef y 11xxxx 1 xx11xx 1 xxxx11 1 other states 0
STD111 3-232 samsung asic scg5/scg5d2 three 2-ands into 3-or with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg5 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.125 0.071 + 0.027*sl 0.071 + 0.027*sl 0.066 + 0.027*sl t f 0.158 0.106 + 0.026*sl 0.114 + 0.024*sl 0.121 + 0.023*sl t plh 0.182 0.150 + 0.016*sl 0.159 + 0.013*sl 0.170 + 0.012*sl t phl 0.268 0.225 + 0.021*sl 0.243 + 0.017*sl 0.266 + 0.014*sl b to y t r 0.128 0.076 + 0.026*sl 0.072 + 0.027*sl 0.066 + 0.027*sl t f 0.170 0.119 + 0.025*sl 0.125 + 0.024*sl 0.131 + 0.023*sl t plh 0.175 0.142 + 0.017*sl 0.153 + 0.014*sl 0.164 + 0.012*sl t phl 0.291 0.246 + 0.022*sl 0.267 + 0.017*sl 0.291 + 0.014*sl c to y t r 0.135 0.083 + 0.026*sl 0.082 + 0.026*sl 0.073 + 0.027*sl t f 0.164 0.113 + 0.026*sl 0.120 + 0.024*sl 0.125 + 0.023*sl t plh 0.232 0.199 + 0.017*sl 0.211 + 0.014*sl 0.221 + 0.012*sl t phl 0.341 0.298 + 0.021*sl 0.316 + 0.017*sl 0.339 + 0.014*sl d to y t r 0.135 0.083 + 0.026*sl 0.081 + 0.026*sl 0.073 + 0.027*sl t f 0.172 0.121 + 0.026*sl 0.130 + 0.023*sl 0.133 + 0.023*sl t plh 0.227 0.194 + 0.016*sl 0.205 + 0.014*sl 0.215 + 0.012*sl t phl 0.363 0.319 + 0.022*sl 0.339 + 0.017*sl 0.363 + 0.014*sl e to y t r 0.147 0.093 + 0.027*sl 0.095 + 0.026*sl 0.086 + 0.027*sl t f 0.163 0.112 + 0.026*sl 0.119 + 0.024*sl 0.124 + 0.023*sl t plh 0.258 0.223 + 0.017*sl 0.236 + 0.014*sl 0.249 + 0.013*sl t phl 0.367 0.324 + 0.021*sl 0.342 + 0.017*sl 0.365 + 0.014*sl f to y t r 0.147 0.094 + 0.026*sl 0.094 + 0.026*sl 0.087 + 0.027*sl t f 0.173 0.121 + 0.026*sl 0.130 + 0.023*sl 0.133 + 0.023*sl t plh 0.253 0.218 + 0.017*sl 0.231 + 0.014*sl 0.244 + 0.013*sl t phl 0.391 0.347 + 0.022*sl 0.367 + 0.017*sl 0.391 + 0.014*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-233 STD111 scg5/scg5d2 three 2-ands into 3-or with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.104 0.076 + 0.014*sl 0.076 + 0.014*sl 0.074 + 0.014*sl t f 0.156 0.126 + 0.015*sl 0.135 + 0.012*sl 0.146 + 0.012*sl t plh 0.189 0.169 + 0.010*sl 0.179 + 0.008*sl 0.196 + 0.006*sl t phl 0.290 0.262 + 0.014*sl 0.279 + 0.010*sl 0.313 + 0.008*sl b to y t r 0.103 0.075 + 0.014*sl 0.078 + 0.013*sl 0.073 + 0.014*sl t f 0.166 0.137 + 0.015*sl 0.147 + 0.012*sl 0.156 + 0.012*sl t plh 0.184 0.164 + 0.010*sl 0.173 + 0.008*sl 0.191 + 0.006*sl t phl 0.312 0.283 + 0.014*sl 0.300 + 0.010*sl 0.336 + 0.008*sl c to y t r 0.116 0.089 + 0.013*sl 0.089 + 0.013*sl 0.084 + 0.014*sl t f 0.160 0.131 + 0.015*sl 0.140 + 0.012*sl 0.149 + 0.012*sl t plh 0.240 0.219 + 0.011*sl 0.230 + 0.008*sl 0.249 + 0.006*sl t phl 0.365 0.338 + 0.014*sl 0.353 + 0.010*sl 0.388 + 0.008*sl d to y t r 0.116 0.089 + 0.013*sl 0.090 + 0.013*sl 0.083 + 0.014*sl t f 0.169 0.139 + 0.015*sl 0.149 + 0.012*sl 0.159 + 0.011*sl t plh 0.234 0.213 + 0.011*sl 0.224 + 0.008*sl 0.243 + 0.006*sl t phl 0.386 0.357 + 0.014*sl 0.374 + 0.010*sl 0.411 + 0.008*sl e to y t r 0.125 0.098 + 0.013*sl 0.099 + 0.013*sl 0.093 + 0.014*sl t f 0.159 0.130 + 0.015*sl 0.140 + 0.012*sl 0.148 + 0.012*sl t plh 0.267 0.245 + 0.011*sl 0.257 + 0.008*sl 0.277 + 0.006*sl t phl 0.391 0.363 + 0.014*sl 0.379 + 0.010*sl 0.413 + 0.008*sl f to y t r 0.125 0.099 + 0.013*sl 0.098 + 0.013*sl 0.094 + 0.014*sl t f 0.169 0.139 + 0.015*sl 0.149 + 0.012*sl 0.159 + 0.011*sl t plh 0.261 0.239 + 0.011*sl 0.252 + 0.008*sl 0.272 + 0.007*sl t phl 0.414 0.385 + 0.014*sl 0.402 + 0.010*sl 0.438 + 0.008*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-234 samsung asic scg6/scg6d2 2-and into 2-or with 1x/2x drive logic symbol cell data input load (sl) gate count scg6 scg6d2 scg6 scg6d2 abcabc 1.67 2.00 0.8 0.8 0.8 0.8 0.8 0.8 a b y c truth table abc y 11x 1 xx1 1 other states 0
samsung asic 3-235 STD111 scg6/scg6d2 2-and into 2-or with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg6 scg6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.112 0.058 + 0.027*sl 0.056 + 0.028*sl 0.051 + 0.028*sl t f 0.110 0.061 + 0.024*sl 0.065 + 0.023*sl 0.062 + 0.024*sl t plh 0.157 0.128 + 0.015*sl 0.135 + 0.013*sl 0.139 + 0.012*sl t phl 0.177 0.143 + 0.017*sl 0.154 + 0.014*sl 0.165 + 0.013*sl b to y t r 0.113 0.060 + 0.026*sl 0.056 + 0.028*sl 0.050 + 0.028*sl t f 0.115 0.066 + 0.025*sl 0.072 + 0.023*sl 0.066 + 0.024*sl t plh 0.151 0.121 + 0.015*sl 0.128 + 0.013*sl 0.133 + 0.012*sl t phl 0.193 0.159 + 0.017*sl 0.170 + 0.014*sl 0.182 + 0.013*sl c to y t r 0.106 0.052 + 0.027*sl 0.049 + 0.028*sl 0.042 + 0.028*sl t f 0.116 0.068 + 0.024*sl 0.072 + 0.023*sl 0.067 + 0.024*sl t plh 0.160 0.133 + 0.014*sl 0.137 + 0.013*sl 0.138 + 0.012*sl t phl 0.211 0.176 + 0.017*sl 0.187 + 0.014*sl 0.199 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.089 0.060 + 0.014*sl 0.063 + 0.014*sl 0.057 + 0.014*sl t f 0.096 0.069 + 0.013*sl 0.074 + 0.012*sl 0.076 + 0.012*sl t plh 0.169 0.150 + 0.009*sl 0.158 + 0.007*sl 0.171 + 0.006*sl t phl 0.190 0.169 + 0.011*sl 0.179 + 0.008*sl 0.200 + 0.007*sl b to y t r 0.092 0.067 + 0.013*sl 0.063 + 0.014*sl 0.056 + 0.014*sl t f 0.102 0.077 + 0.013*sl 0.081 + 0.012*sl 0.081 + 0.012*sl t plh 0.161 0.142 + 0.009*sl 0.151 + 0.007*sl 0.164 + 0.006*sl t phl 0.205 0.183 + 0.011*sl 0.195 + 0.008*sl 0.216 + 0.007*sl c to y t r 0.083 0.060 + 0.012*sl 0.053 + 0.013*sl 0.042 + 0.014*sl t f 0.102 0.077 + 0.012*sl 0.079 + 0.012*sl 0.082 + 0.012*sl t plh 0.162 0.145 + 0.009*sl 0.152 + 0.007*sl 0.158 + 0.006*sl t phl 0.223 0.201 + 0.011*sl 0.212 + 0.008*sl 0.234 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-236 samsung asic scg7/scg7d2 2-nand and (2-and into 2-nor) into 2-nand with 1x/2x drive logic symbol cell data input load (sl) gate count scg7 scg7d2 scg7 scg7d2 abcdeabcde 2.67 3.00 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 c d e a b y truth table abcdey 11xxx1 xx11x1 xxxx11 other states 0
samsung asic 3-237 STD111 scg7/scg7d2 2-nand and (2-and into 2-nor) into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg7 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.127 0.062 + 0.032*sl 0.058 + 0.033*sl 0.051 + 0.034*sl t f 0.128 0.063 + 0.032*sl 0.059 + 0.033*sl 0.053 + 0.034*sl t plh 0.148 0.115 + 0.017*sl 0.121 + 0.015*sl 0.123 + 0.015*sl t phl 0.154 0.119 + 0.018*sl 0.124 + 0.016*sl 0.125 + 0.016*sl b to y t r 0.126 0.061 + 0.033*sl 0.058 + 0.033*sl 0.051 + 0.034*sl t f 0.130 0.067 + 0.032*sl 0.061 + 0.033*sl 0.055 + 0.034*sl t plh 0.143 0.110 + 0.017*sl 0.115 + 0.015*sl 0.118 + 0.015*sl t phl 0.169 0.134 + 0.018*sl 0.139 + 0.016*sl 0.141 + 0.016*sl c to y t r 0.148 0.083 + 0.033*sl 0.080 + 0.034*sl 0.072 + 0.035*sl t f 0.135 0.071 + 0.032*sl 0.068 + 0.033*sl 0.062 + 0.034*sl t plh 0.180 0.147 + 0.017*sl 0.152 + 0.015*sl 0.154 + 0.015*sl t phl 0.183 0.146 + 0.019*sl 0.152 + 0.017*sl 0.158 + 0.016*sl d to y t r 0.152 0.091 + 0.031*sl 0.079 + 0.034*sl 0.073 + 0.034*sl t f 0.139 0.075 + 0.032*sl 0.072 + 0.033*sl 0.065 + 0.034*sl t plh 0.174 0.141 + 0.017*sl 0.146 + 0.015*sl 0.148 + 0.015*sl t phl 0.199 0.161 + 0.019*sl 0.168 + 0.017*sl 0.173 + 0.016*sl e to y t r 0.143 0.078 + 0.033*sl 0.072 + 0.034*sl 0.066 + 0.035*sl t f 0.140 0.076 + 0.032*sl 0.074 + 0.033*sl 0.065 + 0.034*sl t plh 0.185 0.153 + 0.016*sl 0.156 + 0.015*sl 0.156 + 0.015*sl t phl 0.216 0.178 + 0.019*sl 0.185 + 0.017*sl 0.190 + 0.016*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-238 samsung asic scg7/scg7d2 2-nand and (2-and into 2-nor) into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg7d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.098 0.065 + 0.017*sl 0.065 + 0.017*sl 0.056 + 0.017*sl t f 0.098 0.066 + 0.016*sl 0.064 + 0.016*sl 0.057 + 0.017*sl t plh 0.156 0.137 + 0.010*sl 0.143 + 0.008*sl 0.150 + 0.008*sl t phl 0.158 0.138 + 0.010*sl 0.144 + 0.009*sl 0.150 + 0.008*sl b to y t r 0.099 0.066 + 0.016*sl 0.066 + 0.017*sl 0.056 + 0.017*sl t f 0.100 0.067 + 0.017*sl 0.067 + 0.016*sl 0.060 + 0.017*sl t plh 0.150 0.131 + 0.010*sl 0.136 + 0.008*sl 0.144 + 0.008*sl t phl 0.171 0.150 + 0.010*sl 0.157 + 0.009*sl 0.163 + 0.008*sl c to y t r 0.127 0.095 + 0.016*sl 0.094 + 0.016*sl 0.083 + 0.017*sl t f 0.115 0.084 + 0.015*sl 0.080 + 0.016*sl 0.074 + 0.017*sl t plh 0.198 0.179 + 0.009*sl 0.184 + 0.008*sl 0.192 + 0.008*sl t phl 0.199 0.177 + 0.011*sl 0.184 + 0.009*sl 0.195 + 0.008*sl d to y t r 0.128 0.095 + 0.016*sl 0.095 + 0.016*sl 0.083 + 0.017*sl t f 0.120 0.089 + 0.015*sl 0.086 + 0.016*sl 0.078 + 0.017*sl t plh 0.191 0.172 + 0.009*sl 0.177 + 0.008*sl 0.185 + 0.008*sl t phl 0.213 0.191 + 0.011*sl 0.199 + 0.009*sl 0.210 + 0.008*sl e to y t r 0.116 0.086 + 0.015*sl 0.081 + 0.016*sl 0.069 + 0.017*sl t f 0.121 0.091 + 0.015*sl 0.087 + 0.016*sl 0.078 + 0.017*sl t plh 0.191 0.174 + 0.009*sl 0.177 + 0.008*sl 0.180 + 0.008*sl t phl 0.231 0.208 + 0.011*sl 0.217 + 0.009*sl 0.228 + 0.008*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-239 STD111 scg8/scg8d2 2-and into 3-or with 1x/2x drive logic symbol cell data input load (sl) gate count scg8 scg8d2 scg8 scg8d2 abcdabcd 0.7 0.8 0.7 0.8 0.7 0.8 0.7 0.8 2.00 2.33 a b y c d truth table abcdy 11xx1 xx1x1 xxx11 other states 0
STD111 3-240 samsung asic scg8/scg8d2 2-and into 3-or with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg8 scg8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.118 0.064 + 0.027*sl 0.062 + 0.027*sl 0.055 + 0.028*sl t f 0.135 0.082 + 0.026*sl 0.090 + 0.024*sl 0.096 + 0.024*sl t plh 0.178 0.147 + 0.015*sl 0.156 + 0.013*sl 0.162 + 0.012*sl t phl 0.218 0.178 + 0.020*sl 0.192 + 0.016*sl 0.212 + 0.014*sl b to y t r 0.119 0.065 + 0.027*sl 0.063 + 0.027*sl 0.056 + 0.028*sl t f 0.143 0.092 + 0.026*sl 0.097 + 0.024*sl 0.103 + 0.024*sl t plh 0.171 0.141 + 0.015*sl 0.149 + 0.013*sl 0.156 + 0.012*sl t phl 0.236 0.195 + 0.020*sl 0.211 + 0.016*sl 0.231 + 0.014*sl c to y t r 0.115 0.064 + 0.026*sl 0.058 + 0.027*sl 0.049 + 0.028*sl t f 0.146 0.094 + 0.026*sl 0.102 + 0.024*sl 0.105 + 0.023*sl t plh 0.195 0.166 + 0.015*sl 0.173 + 0.013*sl 0.175 + 0.012*sl t phl 0.284 0.244 + 0.020*sl 0.259 + 0.016*sl 0.280 + 0.014*sl d to y t r 0.121 0.069 + 0.026*sl 0.064 + 0.027*sl 0.055 + 0.028*sl t f 0.147 0.096 + 0.025*sl 0.102 + 0.024*sl 0.105 + 0.023*sl t plh 0.207 0.177 + 0.015*sl 0.185 + 0.013*sl 0.189 + 0.012*sl t phl 0.292 0.252 + 0.020*sl 0.267 + 0.016*sl 0.288 + 0.014*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.096 0.070 + 0.013*sl 0.068 + 0.014*sl 0.066 + 0.014*sl t f 0.131 0.103 + 0.014*sl 0.109 + 0.012*sl 0.118 + 0.012*sl t plh 0.191 0.172 + 0.010*sl 0.181 + 0.007*sl 0.196 + 0.006*sl t phl 0.241 0.215 + 0.013*sl 0.229 + 0.009*sl 0.259 + 0.007*sl b to y t r 0.097 0.069 + 0.014*sl 0.071 + 0.014*sl 0.065 + 0.014*sl t f 0.138 0.109 + 0.015*sl 0.118 + 0.012*sl 0.126 + 0.012*sl t plh 0.185 0.165 + 0.010*sl 0.174 + 0.007*sl 0.190 + 0.006*sl t phl 0.258 0.231 + 0.013*sl 0.246 + 0.009*sl 0.277 + 0.007*sl c to y t r 0.093 0.066 + 0.013*sl 0.067 + 0.013*sl 0.053 + 0.014*sl t f 0.140 0.112 + 0.014*sl 0.120 + 0.012*sl 0.127 + 0.012*sl t plh 0.201 0.182 + 0.009*sl 0.191 + 0.007*sl 0.201 + 0.006*sl t phl 0.309 0.282 + 0.013*sl 0.297 + 0.009*sl 0.328 + 0.007*sl d to y t r 0.098 0.073 + 0.012*sl 0.070 + 0.013*sl 0.060 + 0.014*sl t f 0.140 0.111 + 0.014*sl 0.118 + 0.012*sl 0.127 + 0.012*sl t plh 0.213 0.194 + 0.009*sl 0.203 + 0.007*sl 0.215 + 0.006*sl t phl 0.317 0.290 + 0.013*sl 0.305 + 0.009*sl 0.336 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-241 STD111 scg9/scg9d2 2-or into 2-and with 1x/2x drive logic symbol cell data input load (sl) gate count scg9 scg9d2 scg9 scg9d2 abcabc 2.00 2.33 0.7 0.8 0.9 0.7 0.8 0.9 y c a b truth table abc y 00x 0 xx0 0 other states 1
STD111 3-242 samsung asic scg9/scg9d2 2-or into 2-and with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg9 scg9d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.116 0.063 + 0.027*sl 0.059 + 0.027*sl 0.052 + 0.028*sl t f 0.112 0.062 + 0.025*sl 0.070 + 0.023*sl 0.066 + 0.023*sl t plh 0.171 0.141 + 0.015*sl 0.149 + 0.013*sl 0.154 + 0.012*sl t phl 0.188 0.155 + 0.017*sl 0.166 + 0.014*sl 0.178 + 0.013*sl b to y t r 0.121 0.068 + 0.026*sl 0.065 + 0.027*sl 0.058 + 0.028*sl t f 0.113 0.064 + 0.024*sl 0.070 + 0.023*sl 0.066 + 0.023*sl t plh 0.192 0.162 + 0.015*sl 0.170 + 0.013*sl 0.176 + 0.012*sl t phl 0.189 0.155 + 0.017*sl 0.166 + 0.014*sl 0.179 + 0.013*sl c to y t r 0.121 0.067 + 0.027*sl 0.066 + 0.027*sl 0.057 + 0.028*sl t f 0.103 0.058 + 0.023*sl 0.057 + 0.023*sl 0.053 + 0.023*sl t plh 0.185 0.154 + 0.015*sl 0.163 + 0.013*sl 0.169 + 0.012*sl t phl 0.166 0.134 + 0.016*sl 0.144 + 0.013*sl 0.152 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.095 0.067 + 0.014*sl 0.070 + 0.013*sl 0.062 + 0.014*sl t f 0.101 0.075 + 0.013*sl 0.080 + 0.012*sl 0.082 + 0.012*sl t plh 0.184 0.166 + 0.009*sl 0.174 + 0.007*sl 0.187 + 0.006*sl t phl 0.205 0.183 + 0.011*sl 0.193 + 0.008*sl 0.215 + 0.007*sl b to y t r 0.102 0.074 + 0.014*sl 0.076 + 0.013*sl 0.067 + 0.014*sl t f 0.102 0.077 + 0.013*sl 0.081 + 0.012*sl 0.082 + 0.012*sl t plh 0.205 0.186 + 0.010*sl 0.195 + 0.007*sl 0.209 + 0.006*sl t phl 0.206 0.184 + 0.011*sl 0.195 + 0.008*sl 0.217 + 0.007*sl c to y t r 0.102 0.076 + 0.013*sl 0.075 + 0.013*sl 0.068 + 0.014*sl t f 0.083 0.058 + 0.013*sl 0.062 + 0.012*sl 0.060 + 0.012*sl t plh 0.198 0.179 + 0.010*sl 0.187 + 0.007*sl 0.202 + 0.006*sl t phl 0.167 0.147 + 0.010*sl 0.156 + 0.007*sl 0.172 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-243 STD111 scg10/scg10d2 two 2-ors into 2-and with 1x/2x drive logic symbol cell data input load (sl) gate count scg10 scg10d2 scg10 scg10d2 abcdabcd 0.7 0.8 0.7 0.8 0.7 0.8 0.7 0.8 2.33 2.67 c d y a b truth table abcdy 00xx0 xx000 other states 1
STD111 3-244 samsung asic scg10/scg10d2 two 2-ors into 2-and with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg10 scg10d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.126 0.072 + 0.027*sl 0.072 + 0.027*sl 0.064 + 0.028*sl t f 0.126 0.076 + 0.025*sl 0.083 + 0.023*sl 0.080 + 0.024*sl t plh 0.207 0.175 + 0.016*sl 0.185 + 0.013*sl 0.193 + 0.013*sl t phl 0.194 0.157 + 0.019*sl 0.170 + 0.015*sl 0.187 + 0.013*sl b to y t r 0.136 0.083 + 0.026*sl 0.083 + 0.027*sl 0.071 + 0.028*sl t f 0.126 0.075 + 0.025*sl 0.082 + 0.023*sl 0.080 + 0.024*sl t plh 0.237 0.204 + 0.016*sl 0.215 + 0.014*sl 0.225 + 0.013*sl t phl 0.197 0.160 + 0.019*sl 0.173 + 0.015*sl 0.189 + 0.013*sl c to y t r 0.127 0.073 + 0.027*sl 0.072 + 0.027*sl 0.064 + 0.028*sl t f 0.135 0.085 + 0.025*sl 0.091 + 0.023*sl 0.089 + 0.023*sl t plh 0.215 0.183 + 0.016*sl 0.193 + 0.013*sl 0.202 + 0.013*sl t phl 0.221 0.183 + 0.019*sl 0.197 + 0.015*sl 0.215 + 0.013*sl d to y t r 0.135 0.082 + 0.026*sl 0.080 + 0.027*sl 0.071 + 0.028*sl t f 0.136 0.087 + 0.024*sl 0.092 + 0.023*sl 0.089 + 0.023*sl t plh 0.245 0.212 + 0.016*sl 0.223 + 0.014*sl 0.232 + 0.013*sl t phl 0.223 0.185 + 0.019*sl 0.199 + 0.015*sl 0.217 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.109 0.082 + 0.013*sl 0.082 + 0.014*sl 0.077 + 0.014*sl t f 0.111 0.083 + 0.014*sl 0.090 + 0.012*sl 0.093 + 0.012*sl t plh 0.223 0.202 + 0.010*sl 0.213 + 0.008*sl 0.230 + 0.006*sl t phl 0.205 0.181 + 0.012*sl 0.194 + 0.009*sl 0.219 + 0.007*sl b to y t r 0.119 0.093 + 0.013*sl 0.093 + 0.013*sl 0.085 + 0.014*sl t f 0.112 0.086 + 0.013*sl 0.089 + 0.012*sl 0.095 + 0.012*sl t plh 0.252 0.230 + 0.011*sl 0.242 + 0.008*sl 0.262 + 0.006*sl t phl 0.208 0.184 + 0.012*sl 0.197 + 0.009*sl 0.222 + 0.007*sl c to y t r 0.109 0.081 + 0.014*sl 0.083 + 0.013*sl 0.077 + 0.014*sl t f 0.122 0.095 + 0.013*sl 0.100 + 0.012*sl 0.105 + 0.012*sl t plh 0.232 0.211 + 0.010*sl 0.222 + 0.008*sl 0.239 + 0.006*sl t phl 0.230 0.205 + 0.013*sl 0.220 + 0.009*sl 0.246 + 0.007*sl d to y t r 0.119 0.092 + 0.013*sl 0.092 + 0.013*sl 0.087 + 0.014*sl t f 0.122 0.096 + 0.013*sl 0.101 + 0.012*sl 0.105 + 0.012*sl t plh 0.260 0.238 + 0.011*sl 0.250 + 0.008*sl 0.270 + 0.006*sl t phl 0.232 0.208 + 0.012*sl 0.222 + 0.009*sl 0.248 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-245 STD111 scg11/scg11d2 two 2-nors into 3-nor with 1x/2x drive logic symbol cell data input load (sl) gate count scg11 scg11d2 scg11 scg11d2 abcdeabcde 2.67 3.67 0.9 0.9 0.9 0.9 1.0 0.9 0.9 0.9 0.9 2.2 c d y a b e truth table abcdey 00xxx0 xx00x0 xxxx10 other states 1
STD111 3-246 samsung asic scg11/scg11d2 two 2-nors into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg11 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.320 0.155 + 0.082*sl 0.154 + 0.083*sl 0.156 + 0.082*sl t f 0.115 0.067 + 0.024*sl 0.072 + 0.023*sl 0.067 + 0.023*sl t plh 0.186 0.114 + 0.036*sl 0.115 + 0.036*sl 0.117 + 0.035*sl t phl 0.190 0.157 + 0.016*sl 0.167 + 0.014*sl 0.177 + 0.013*sl b to y t r 0.321 0.156 + 0.082*sl 0.154 + 0.083*sl 0.156 + 0.082*sl t f 0.115 0.068 + 0.024*sl 0.071 + 0.023*sl 0.067 + 0.023*sl t plh 0.200 0.128 + 0.036*sl 0.129 + 0.035*sl 0.130 + 0.035*sl t phl 0.188 0.155 + 0.016*sl 0.165 + 0.014*sl 0.175 + 0.013*sl c to y t r 0.326 0.163 + 0.081*sl 0.160 + 0.082*sl 0.157 + 0.082*sl t f 0.136 0.090 + 0.023*sl 0.092 + 0.022*sl 0.084 + 0.023*sl t plh 0.216 0.144 + 0.036*sl 0.146 + 0.036*sl 0.148 + 0.035*sl t phl 0.201 0.170 + 0.016*sl 0.178 + 0.013*sl 0.186 + 0.013*sl d to y t r 0.326 0.164 + 0.081*sl 0.161 + 0.082*sl 0.158 + 0.082*sl t f 0.136 0.090 + 0.023*sl 0.092 + 0.022*sl 0.085 + 0.023*sl t plh 0.229 0.156 + 0.036*sl 0.158 + 0.036*sl 0.160 + 0.035*sl t phl 0.199 0.168 + 0.016*sl 0.176 + 0.013*sl 0.184 + 0.013*sl e to y t r 0.332 0.173 + 0.080*sl 0.166 + 0.082*sl 0.159 + 0.082*sl t f 0.159 0.120 + 0.019*sl 0.112 + 0.021*sl 0.098 + 0.023*sl t plh 0.183 0.111 + 0.036*sl 0.112 + 0.036*sl 0.114 + 0.035*sl t phl 0.099 0.069 + 0.015*sl 0.077 + 0.013*sl 0.079 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-247 STD111 scg11/scg11d2 two 2-nors into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg11d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.222 0.141 + 0.041*sl 0.138 + 0.041*sl 0.137 + 0.041*sl t f 0.103 0.078 + 0.013*sl 0.083 + 0.012*sl 0.083 + 0.012*sl t plh 0.163 0.128 + 0.018*sl 0.127 + 0.018*sl 0.128 + 0.018*sl t phl 0.205 0.185 + 0.010*sl 0.194 + 0.008*sl 0.214 + 0.007*sl b to y t r 0.223 0.141 + 0.041*sl 0.139 + 0.041*sl 0.138 + 0.041*sl t f 0.104 0.079 + 0.012*sl 0.082 + 0.012*sl 0.083 + 0.012*sl t plh 0.175 0.141 + 0.017*sl 0.139 + 0.018*sl 0.140 + 0.018*sl t phl 0.203 0.183 + 0.010*sl 0.192 + 0.008*sl 0.212 + 0.007*sl c to y t r 0.230 0.151 + 0.040*sl 0.147 + 0.041*sl 0.141 + 0.041*sl t f 0.128 0.105 + 0.012*sl 0.106 + 0.011*sl 0.105 + 0.011*sl t plh 0.194 0.157 + 0.019*sl 0.159 + 0.018*sl 0.162 + 0.018*sl t phl 0.221 0.202 + 0.010*sl 0.210 + 0.008*sl 0.227 + 0.007*sl d to y t r 0.231 0.152 + 0.040*sl 0.148 + 0.041*sl 0.142 + 0.041*sl t f 0.129 0.106 + 0.012*sl 0.107 + 0.011*sl 0.105 + 0.011*sl t plh 0.204 0.167 + 0.019*sl 0.170 + 0.018*sl 0.173 + 0.018*sl t phl 0.220 0.200 + 0.010*sl 0.208 + 0.008*sl 0.225 + 0.007*sl e to y t r 0.237 0.159 + 0.039*sl 0.154 + 0.041*sl 0.143 + 0.041*sl t f 0.136 0.117 + 0.010*sl 0.114 + 0.010*sl 0.096 + 0.011*sl t plh 0.141 0.103 + 0.019*sl 0.106 + 0.018*sl 0.108 + 0.018*sl t phl 0.079 0.062 + 0.009*sl 0.070 + 0.007*sl 0.075 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-248 samsung asic scg12/scg12d2 2-nand into 2-nor with 1x/2x drive logic symbol cell data input load (sl) gate count scg12 scg12d2 scg12 scg12d2 abcabc 1.67 2.33 0.8 0.8 1.1 0.8 0.8 2.3 a b y c truth table abc y 110 1 other states 0
samsung asic 3-249 STD111 scg12/scg12d2 2-nand into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg12 scg12d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.203 0.095 + 0.054*sl 0.091 + 0.055*sl 0.087 + 0.055*sl t f 0.085 0.048 + 0.018*sl 0.047 + 0.019*sl 0.041 + 0.019*sl t plh 0.173 0.124 + 0.024*sl 0.127 + 0.024*sl 0.127 + 0.024*sl t phl 0.141 0.116 + 0.012*sl 0.123 + 0.011*sl 0.128 + 0.010*sl b to y t r 0.203 0.095 + 0.054*sl 0.091 + 0.055*sl 0.086 + 0.055*sl t f 0.087 0.051 + 0.018*sl 0.049 + 0.018*sl 0.043 + 0.019*sl t plh 0.169 0.120 + 0.024*sl 0.122 + 0.024*sl 0.123 + 0.024*sl t phl 0.155 0.129 + 0.013*sl 0.137 + 0.011*sl 0.143 + 0.010*sl c to y t r 0.212 0.108 + 0.052*sl 0.100 + 0.054*sl 0.090 + 0.055*sl t f 0.127 0.096 + 0.015*sl 0.092 + 0.016*sl 0.074 + 0.018*sl t plh 0.121 0.072 + 0.025*sl 0.076 + 0.024*sl 0.075 + 0.024*sl t phl 0.076 0.049 + 0.014*sl 0.061 + 0.010*sl 0.064 + 0.010*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.147 0.093 + 0.027*sl 0.092 + 0.027*sl 0.083 + 0.028*sl t f 0.074 0.055 + 0.010*sl 0.056 + 0.009*sl 0.054 + 0.009*sl t plh 0.179 0.153 + 0.013*sl 0.156 + 0.012*sl 0.159 + 0.012*sl t phl 0.154 0.138 + 0.008*sl 0.146 + 0.006*sl 0.158 + 0.005*sl b to y t r 0.147 0.095 + 0.026*sl 0.092 + 0.027*sl 0.083 + 0.028*sl t f 0.078 0.058 + 0.010*sl 0.061 + 0.009*sl 0.058 + 0.009*sl t plh 0.173 0.146 + 0.013*sl 0.151 + 0.012*sl 0.153 + 0.012*sl t phl 0.165 0.149 + 0.008*sl 0.157 + 0.006*sl 0.171 + 0.005*sl c to y t r 0.153 0.102 + 0.025*sl 0.096 + 0.027*sl 0.085 + 0.028*sl t f 0.107 0.090 + 0.008*sl 0.091 + 0.008*sl 0.074 + 0.009*sl t plh 0.092 0.065 + 0.014*sl 0.071 + 0.012*sl 0.072 + 0.012*sl t phl 0.057 0.041 + 0.008*sl 0.050 + 0.006*sl 0.061 + 0.005*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-250 samsung asic scg13/scg13d2 2-nor into 2-nand with 1x/2x drive logic symbol cell data input load (sl) gate count scg13 scg13d2 scg13 scg13d2 abcabc 1.67 2.33 0.9 0.9 1.0 0.9 0.9 2.1 y a b c truth table abc y 001 0 other states 1
samsung asic 3-251 STD111 scg13/scg13d2 2-nor into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg13 scg13d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.122 0.057 + 0.032*sl 0.050 + 0.034*sl 0.047 + 0.034*sl t f 0.141 0.075 + 0.033*sl 0.077 + 0.032*sl 0.071 + 0.033*sl t plh 0.124 0.092 + 0.016*sl 0.095 + 0.015*sl 0.095 + 0.015*sl t phl 0.193 0.155 + 0.019*sl 0.163 + 0.017*sl 0.170 + 0.016*sl b to y t r 0.122 0.058 + 0.032*sl 0.052 + 0.034*sl 0.048 + 0.034*sl t f 0.142 0.077 + 0.032*sl 0.078 + 0.032*sl 0.071 + 0.033*sl t plh 0.137 0.106 + 0.016*sl 0.108 + 0.015*sl 0.109 + 0.015*sl t phl 0.191 0.152 + 0.019*sl 0.161 + 0.017*sl 0.169 + 0.016*sl c to y t r 0.165 0.107 + 0.029*sl 0.096 + 0.032*sl 0.079 + 0.034*sl t f 0.141 0.082 + 0.030*sl 0.073 + 0.032*sl 0.063 + 0.033*sl t plh 0.102 0.069 + 0.016*sl 0.075 + 0.015*sl 0.074 + 0.015*sl t phl 0.082 0.045 + 0.018*sl 0.053 + 0.016*sl 0.055 + 0.016*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.089 0.058 + 0.015*sl 0.054 + 0.017*sl 0.045 + 0.017*sl t f 0.119 0.086 + 0.016*sl 0.087 + 0.016*sl 0.084 + 0.016*sl t plh 0.127 0.110 + 0.008*sl 0.113 + 0.008*sl 0.115 + 0.007*sl t phl 0.205 0.182 + 0.011*sl 0.190 + 0.009*sl 0.206 + 0.008*sl b to y t r 0.090 0.059 + 0.016*sl 0.055 + 0.017*sl 0.047 + 0.017*sl t f 0.119 0.087 + 0.016*sl 0.087 + 0.016*sl 0.085 + 0.016*sl t plh 0.139 0.122 + 0.009*sl 0.126 + 0.008*sl 0.127 + 0.007*sl t phl 0.203 0.180 + 0.011*sl 0.188 + 0.009*sl 0.204 + 0.008*sl c to y t r 0.133 0.107 + 0.013*sl 0.098 + 0.016*sl 0.080 + 0.017*sl t f 0.107 0.076 + 0.016*sl 0.075 + 0.016*sl 0.064 + 0.017*sl t plh 0.084 0.065 + 0.009*sl 0.072 + 0.008*sl 0.073 + 0.007*sl t phl 0.062 0.042 + 0.010*sl 0.049 + 0.009*sl 0.057 + 0.008*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-252 samsung asic scg14/scg14d2 2-nand into 2-nand with 1x/2x drive logic symbol cell data input load (sl) gate count scg14 scg14d2 scg14 scg14d2 abcabc 1.67 2.33 0.8 0.8 1.0 0.8 0.8 2.0 a b y c truth table abc y 0x1 0 x01 0 other states 1
samsung asic 3-253 STD111 scg14/scg14d2 2-nand into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg14 scg14d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.128 0.062 + 0.033*sl 0.058 + 0.034*sl 0.051 + 0.035*sl t f 0.126 0.064 + 0.031*sl 0.058 + 0.033*sl 0.052 + 0.033*sl t plh 0.146 0.113 + 0.017*sl 0.118 + 0.015*sl 0.120 + 0.015*sl t phl 0.154 0.119 + 0.017*sl 0.124 + 0.016*sl 0.126 + 0.016*sl b to y t r 0.127 0.061 + 0.033*sl 0.058 + 0.034*sl 0.051 + 0.035*sl t f 0.128 0.067 + 0.031*sl 0.060 + 0.033*sl 0.053 + 0.033*sl t plh 0.142 0.108 + 0.017*sl 0.114 + 0.015*sl 0.116 + 0.015*sl t phl 0.169 0.134 + 0.018*sl 0.139 + 0.016*sl 0.141 + 0.016*sl c to y t r 0.164 0.106 + 0.029*sl 0.094 + 0.032*sl 0.076 + 0.034*sl t f 0.138 0.080 + 0.029*sl 0.070 + 0.032*sl 0.058 + 0.033*sl t plh 0.102 0.069 + 0.016*sl 0.075 + 0.015*sl 0.074 + 0.015*sl t phl 0.080 0.043 + 0.018*sl 0.052 + 0.016*sl 0.053 + 0.016*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.099 0.066 + 0.017*sl 0.066 + 0.017*sl 0.057 + 0.017*sl t f 0.098 0.067 + 0.016*sl 0.065 + 0.016*sl 0.058 + 0.017*sl t plh 0.156 0.137 + 0.009*sl 0.142 + 0.008*sl 0.149 + 0.008*sl t phl 0.159 0.139 + 0.010*sl 0.145 + 0.008*sl 0.151 + 0.008*sl b to y t r 0.100 0.067 + 0.016*sl 0.067 + 0.017*sl 0.057 + 0.017*sl t f 0.101 0.069 + 0.016*sl 0.068 + 0.016*sl 0.062 + 0.016*sl t plh 0.150 0.131 + 0.010*sl 0.136 + 0.008*sl 0.143 + 0.008*sl t phl 0.172 0.152 + 0.010*sl 0.158 + 0.008*sl 0.165 + 0.008*sl c to y t r 0.133 0.106 + 0.013*sl 0.097 + 0.016*sl 0.078 + 0.017*sl t f 0.106 0.075 + 0.015*sl 0.074 + 0.016*sl 0.060 + 0.017*sl t plh 0.084 0.066 + 0.009*sl 0.072 + 0.008*sl 0.074 + 0.007*sl t phl 0.061 0.041 + 0.010*sl 0.048 + 0.008*sl 0.054 + 0.008*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-254 samsung asic scg15/scg15d2 2-nand into 3-nand with 1x/2x drive logic symbol cell data input load (sl) gate count scg15 scg15d2 scg15 scg15d2 abcdabcd 0.8 0.8 0.9 0.9 0.8 0.8 1.8 1.8 2.00 2.67 a b y c d truth table abcdy 0x110 x0110 other states 1
samsung asic 3-255 STD111 scg15/scg15d2 2-nand into 3-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg15 scg15d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.167 0.080 + 0.043*sl 0.076 + 0.045*sl 0.071 + 0.045*sl t f 0.186 0.094 + 0.046*sl 0.090 + 0.047*sl 0.085 + 0.047*sl t plh 0.167 0.126 + 0.021*sl 0.129 + 0.020*sl 0.131 + 0.020*sl t phl 0.176 0.130 + 0.023*sl 0.133 + 0.022*sl 0.134 + 0.022*sl b to y t r 0.167 0.081 + 0.043*sl 0.076 + 0.045*sl 0.071 + 0.045*sl t f 0.187 0.096 + 0.045*sl 0.090 + 0.047*sl 0.085 + 0.047*sl t plh 0.163 0.121 + 0.021*sl 0.125 + 0.020*sl 0.126 + 0.020*sl t phl 0.188 0.143 + 0.023*sl 0.146 + 0.022*sl 0.147 + 0.022*sl c to y t r 0.203 0.122 + 0.040*sl 0.112 + 0.043*sl 0.094 + 0.045*sl t f 0.198 0.111 + 0.044*sl 0.101 + 0.046*sl 0.090 + 0.047*sl t plh 0.127 0.087 + 0.020*sl 0.089 + 0.019*sl 0.088 + 0.019*sl t phl 0.111 0.064 + 0.023*sl 0.069 + 0.022*sl 0.069 + 0.022*sl d to y t r 0.229 0.147 + 0.041*sl 0.135 + 0.044*sl 0.117 + 0.046*sl t f 0.192 0.103 + 0.045*sl 0.095 + 0.047*sl 0.088 + 0.047*sl t plh 0.140 0.100 + 0.020*sl 0.100 + 0.020*sl 0.100 + 0.020*sl t phl 0.110 0.064 + 0.023*sl 0.068 + 0.022*sl 0.068 + 0.022*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.120 0.077 + 0.022*sl 0.074 + 0.023*sl 0.066 + 0.023*sl t f 0.132 0.087 + 0.023*sl 0.085 + 0.023*sl 0.078 + 0.024*sl t plh 0.165 0.142 + 0.012*sl 0.147 + 0.010*sl 0.152 + 0.010*sl t phl 0.165 0.140 + 0.012*sl 0.144 + 0.011*sl 0.147 + 0.011*sl b to y t r 0.120 0.076 + 0.022*sl 0.075 + 0.022*sl 0.066 + 0.023*sl t f 0.135 0.090 + 0.023*sl 0.088 + 0.023*sl 0.079 + 0.024*sl t plh 0.160 0.136 + 0.012*sl 0.142 + 0.010*sl 0.146 + 0.010*sl t phl 0.178 0.153 + 0.012*sl 0.158 + 0.011*sl 0.161 + 0.011*sl c to y t r 0.155 0.116 + 0.020*sl 0.109 + 0.021*sl 0.088 + 0.023*sl t f 0.144 0.102 + 0.021*sl 0.095 + 0.023*sl 0.082 + 0.024*sl t plh 0.103 0.081 + 0.011*sl 0.086 + 0.010*sl 0.085 + 0.010*sl t phl 0.081 0.055 + 0.013*sl 0.063 + 0.011*sl 0.066 + 0.011*sl d to y t r 0.179 0.142 + 0.019*sl 0.132 + 0.021*sl 0.110 + 0.023*sl t f 0.136 0.093 + 0.021*sl 0.087 + 0.023*sl 0.079 + 0.024*sl t plh 0.115 0.094 + 0.011*sl 0.096 + 0.010*sl 0.096 + 0.010*sl t phl 0.082 0.057 + 0.013*sl 0.062 + 0.011*sl 0.065 + 0.011*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-256 samsung asic scg16/scg16d2 2-or with one inverted input into 2-nand with 1x/2x drive logic symbol cell data input load (sl) gate count scg16 scg16d2 scg16 scg16d2 abcabc 2.00 2.67 0.8 1.0 1.1 0.8 2.0 2.3 a b y c truth table abc y 0x1 0 x11 0 other states 1
samsung asic 3-257 STD111 scg16/scg16d2 2-or with one inverted input into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg16 scg16d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.226 0.117 + 0.054*sl 0.114 + 0.055*sl 0.111 + 0.056*sl t f 0.166 0.084 + 0.041*sl 0.080 + 0.042*sl 0.077 + 0.042*sl t plh 0.168 0.120 + 0.024*sl 0.120 + 0.024*sl 0.121 + 0.024*sl t phl 0.173 0.131 + 0.021*sl 0.133 + 0.021*sl 0.134 + 0.020*sl b to y t r 0.239 0.134 + 0.052*sl 0.126 + 0.054*sl 0.117 + 0.055*sl t f 0.212 0.138 + 0.037*sl 0.127 + 0.040*sl 0.111 + 0.041*sl t plh 0.128 0.079 + 0.025*sl 0.082 + 0.024*sl 0.082 + 0.024*sl t phl 0.137 0.096 + 0.020*sl 0.097 + 0.020*sl 0.097 + 0.020*sl c to y t r 0.165 0.117 + 0.024*sl 0.108 + 0.026*sl 0.095 + 0.028*sl t f 0.199 0.121 + 0.039*sl 0.115 + 0.041*sl 0.108 + 0.041*sl t plh 0.103 0.075 + 0.014*sl 0.081 + 0.012*sl 0.080 + 0.012*sl t phl 0.129 0.088 + 0.021*sl 0.089 + 0.020*sl 0.090 + 0.020*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.165 0.113 + 0.026*sl 0.107 + 0.028*sl 0.102 + 0.028*sl t f 0.124 0.083 + 0.020*sl 0.080 + 0.021*sl 0.074 + 0.022*sl t plh 0.162 0.137 + 0.012*sl 0.139 + 0.012*sl 0.140 + 0.012*sl t phl 0.171 0.147 + 0.012*sl 0.151 + 0.011*sl 0.154 + 0.011*sl b to y t r 0.178 0.128 + 0.025*sl 0.120 + 0.027*sl 0.109 + 0.028*sl t f 0.171 0.136 + 0.018*sl 0.128 + 0.019*sl 0.107 + 0.021*sl t plh 0.101 0.074 + 0.013*sl 0.079 + 0.012*sl 0.080 + 0.012*sl t phl 0.113 0.091 + 0.011*sl 0.093 + 0.010*sl 0.094 + 0.010*sl c to y t r 0.135 0.112 + 0.011*sl 0.107 + 0.013*sl 0.090 + 0.014*sl t f 0.156 0.118 + 0.019*sl 0.112 + 0.020*sl 0.102 + 0.021*sl t plh 0.084 0.068 + 0.008*sl 0.074 + 0.006*sl 0.076 + 0.006*sl t phl 0.102 0.080 + 0.011*sl 0.083 + 0.010*sl 0.084 + 0.010*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-258 samsung asic scg17/scg17d2 2-and into 2-nor into 2-nand with 1x/2x drive logic symbol cell data input load (sl) gate count scg17 scg17d2 scg17 scg17d2 abcdabcd 0.8 0.8 0.8 1.0 0.8 0.8 0.8 2.1 2.00 2.67 a b c d y truth table abcdy 0x010 x0010 other states 1
samsung asic 3-259 STD111 scg17/scg17d2 2-and into 2-nor into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg17 scg17d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.136 0.073 + 0.031*sl 0.063 + 0.034*sl 0.056 + 0.035*sl t f 0.141 0.075 + 0.033*sl 0.077 + 0.033*sl 0.072 + 0.033*sl t plh 0.172 0.138 + 0.017*sl 0.145 + 0.015*sl 0.148 + 0.015*sl t phl 0.186 0.147 + 0.020*sl 0.156 + 0.017*sl 0.165 + 0.016*sl b to y t r 0.131 0.065 + 0.033*sl 0.061 + 0.034*sl 0.056 + 0.035*sl t f 0.145 0.079 + 0.033*sl 0.081 + 0.032*sl 0.076 + 0.033*sl t plh 0.166 0.131 + 0.017*sl 0.138 + 0.015*sl 0.142 + 0.015*sl t phl 0.202 0.163 + 0.020*sl 0.173 + 0.017*sl 0.182 + 0.016*sl c to y t r 0.128 0.066 + 0.031*sl 0.055 + 0.034*sl 0.049 + 0.035*sl t f 0.146 0.081 + 0.033*sl 0.083 + 0.032*sl 0.076 + 0.033*sl t plh 0.173 0.141 + 0.016*sl 0.144 + 0.015*sl 0.146 + 0.015*sl t phl 0.219 0.179 + 0.020*sl 0.190 + 0.017*sl 0.198 + 0.016*sl d to y t r 0.165 0.106 + 0.029*sl 0.095 + 0.032*sl 0.077 + 0.034*sl t f 0.139 0.079 + 0.030*sl 0.070 + 0.032*sl 0.061 + 0.033*sl t plh 0.102 0.070 + 0.016*sl 0.076 + 0.015*sl 0.074 + 0.015*sl t phl 0.082 0.045 + 0.019*sl 0.053 + 0.016*sl 0.055 + 0.016*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.108 0.075 + 0.016*sl 0.075 + 0.017*sl 0.067 + 0.017*sl t f 0.118 0.086 + 0.016*sl 0.086 + 0.016*sl 0.085 + 0.016*sl t plh 0.186 0.166 + 0.010*sl 0.173 + 0.008*sl 0.183 + 0.008*sl t phl 0.197 0.175 + 0.011*sl 0.183 + 0.009*sl 0.199 + 0.008*sl b to y t r 0.108 0.075 + 0.017*sl 0.076 + 0.017*sl 0.067 + 0.017*sl t f 0.125 0.094 + 0.016*sl 0.093 + 0.016*sl 0.090 + 0.016*sl t plh 0.179 0.159 + 0.010*sl 0.166 + 0.008*sl 0.176 + 0.008*sl t phl 0.212 0.189 + 0.012*sl 0.198 + 0.009*sl 0.215 + 0.008*sl c to y t r 0.098 0.067 + 0.016*sl 0.064 + 0.017*sl 0.053 + 0.017*sl t f 0.126 0.094 + 0.016*sl 0.094 + 0.016*sl 0.091 + 0.016*sl t plh 0.178 0.160 + 0.009*sl 0.164 + 0.008*sl 0.168 + 0.008*sl t phl 0.230 0.207 + 0.012*sl 0.216 + 0.009*sl 0.233 + 0.008*sl d to y t r 0.133 0.106 + 0.013*sl 0.098 + 0.016*sl 0.079 + 0.017*sl t f 0.107 0.076 + 0.016*sl 0.075 + 0.016*sl 0.063 + 0.017*sl t plh 0.083 0.064 + 0.009*sl 0.070 + 0.008*sl 0.072 + 0.007*sl t phl 0.061 0.040 + 0.010*sl 0.047 + 0.009*sl 0.055 + 0.008*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-260 samsung asic scg18/scg18d2 2-and into 2-nor into 3-nand with 1x/2x drive logic symbol cell data input load (sl) gate count scg18 scg18d2 scg18 scg18d2 abcdeabcde 2.33 3.00 0.8 0.8 0.8 0.9 0.9 0.8 0.8 0.8 1.8 1.8 a b c d e y truth table abcdey 0x0110 x00110 other states 1
samsung asic 3-261 STD111 scg18/scg18d2 2-and into 2-nor into 3-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg18 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.173 0.085 + 0.044*sl 0.082 + 0.045*sl 0.074 + 0.046*sl t f 0.198 0.104 + 0.047*sl 0.105 + 0.047*sl 0.099 + 0.047*sl t plh 0.193 0.150 + 0.021*sl 0.155 + 0.020*sl 0.157 + 0.020*sl t phl 0.205 0.156 + 0.025*sl 0.163 + 0.023*sl 0.168 + 0.022*sl b to y t r 0.173 0.085 + 0.044*sl 0.081 + 0.045*sl 0.074 + 0.046*sl t f 0.203 0.110 + 0.046*sl 0.108 + 0.047*sl 0.102 + 0.047*sl t plh 0.187 0.144 + 0.021*sl 0.149 + 0.020*sl 0.151 + 0.020*sl t phl 0.221 0.172 + 0.025*sl 0.180 + 0.023*sl 0.185 + 0.022*sl c to y t r 0.167 0.077 + 0.045*sl 0.074 + 0.046*sl 0.070 + 0.046*sl t f 0.203 0.111 + 0.046*sl 0.109 + 0.046*sl 0.101 + 0.047*sl t plh 0.194 0.153 + 0.021*sl 0.155 + 0.020*sl 0.156 + 0.020*sl t phl 0.238 0.189 + 0.025*sl 0.196 + 0.023*sl 0.202 + 0.022*sl d to y t r 0.206 0.124 + 0.041*sl 0.112 + 0.044*sl 0.095 + 0.046*sl t f 0.199 0.110 + 0.044*sl 0.102 + 0.046*sl 0.092 + 0.048*sl t plh 0.128 0.088 + 0.020*sl 0.090 + 0.020*sl 0.089 + 0.020*sl t phl 0.111 0.064 + 0.024*sl 0.069 + 0.022*sl 0.070 + 0.022*sl e to y t r 0.230 0.149 + 0.041*sl 0.137 + 0.044*sl 0.119 + 0.046*sl t f 0.193 0.102 + 0.045*sl 0.096 + 0.047*sl 0.089 + 0.048*sl t plh 0.140 0.100 + 0.020*sl 0.101 + 0.020*sl 0.101 + 0.020*sl t phl 0.112 0.066 + 0.023*sl 0.070 + 0.022*sl 0.071 + 0.022*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-262 samsung asic scg18/scg18d2 2-and into 2-nor into 3-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg18d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.126 0.083 + 0.022*sl 0.081 + 0.022*sl 0.071 + 0.023*sl t f 0.148 0.100 + 0.024*sl 0.103 + 0.023*sl 0.097 + 0.024*sl t plh 0.193 0.169 + 0.012*sl 0.176 + 0.010*sl 0.183 + 0.010*sl t phl 0.200 0.173 + 0.014*sl 0.180 + 0.012*sl 0.192 + 0.011*sl b to y t r 0.127 0.084 + 0.021*sl 0.081 + 0.022*sl 0.071 + 0.023*sl t f 0.153 0.106 + 0.024*sl 0.108 + 0.023*sl 0.101 + 0.024*sl t plh 0.187 0.162 + 0.012*sl 0.169 + 0.010*sl 0.176 + 0.010*sl t phl 0.216 0.188 + 0.014*sl 0.196 + 0.012*sl 0.208 + 0.011*sl c to y t r 0.117 0.074 + 0.021*sl 0.070 + 0.022*sl 0.061 + 0.023*sl t f 0.154 0.107 + 0.024*sl 0.109 + 0.023*sl 0.101 + 0.024*sl t plh 0.186 0.163 + 0.011*sl 0.167 + 0.010*sl 0.170 + 0.010*sl t phl 0.233 0.205 + 0.014*sl 0.213 + 0.012*sl 0.226 + 0.011*sl d to y t r 0.155 0.116 + 0.019*sl 0.109 + 0.021*sl 0.087 + 0.023*sl t f 0.143 0.100 + 0.021*sl 0.094 + 0.023*sl 0.083 + 0.024*sl t plh 0.100 0.078 + 0.011*sl 0.083 + 0.010*sl 0.082 + 0.010*sl t phl 0.080 0.053 + 0.013*sl 0.061 + 0.011*sl 0.065 + 0.011*sl e to y t r 0.179 0.141 + 0.019*sl 0.132 + 0.021*sl 0.109 + 0.023*sl t f 0.136 0.093 + 0.022*sl 0.086 + 0.024*sl 0.080 + 0.024*sl t plh 0.114 0.093 + 0.011*sl 0.095 + 0.010*sl 0.095 + 0.010*sl t phl 0.082 0.057 + 0.013*sl 0.062 + 0.011*sl 0.067 + 0.011*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-263 STD111 scg19/scg19d2 2-and into 2-and into 2-nor with 1x/2x drive logic symbol cell data input load (sl) gate count scg19 scg19d2 scg19 scg19d2 abcdabcd 0.8 0.8 1.0 1.0 0.8 0.8 2.0 2.2 2.33 3.00 a b c d y truth table abcdy 111x0 xxx10 other states 1
STD111 3-264 samsung asic scg19/scg19d2 2-and into 2-and into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg19 scg19d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.204 0.093 + 0.055*sl 0.091 + 0.056*sl 0.090 + 0.056*sl t f 0.146 0.066 + 0.040*sl 0.062 + 0.041*sl 0.057 + 0.042*sl t plh 0.223 0.174 + 0.025*sl 0.176 + 0.024*sl 0.177 + 0.024*sl t phl 0.210 0.168 + 0.021*sl 0.171 + 0.020*sl 0.173 + 0.020*sl b to y t r 0.204 0.093 + 0.055*sl 0.091 + 0.056*sl 0.090 + 0.056*sl t f 0.145 0.064 + 0.040*sl 0.062 + 0.041*sl 0.057 + 0.042*sl t plh 0.237 0.188 + 0.025*sl 0.190 + 0.024*sl 0.191 + 0.024*sl t phl 0.205 0.163 + 0.021*sl 0.167 + 0.020*sl 0.168 + 0.020*sl c to y t r 0.248 0.146 + 0.051*sl 0.134 + 0.055*sl 0.116 + 0.056*sl t f 0.159 0.084 + 0.037*sl 0.073 + 0.040*sl 0.063 + 0.041*sl t plh 0.130 0.081 + 0.024*sl 0.082 + 0.024*sl 0.080 + 0.024*sl t phl 0.100 0.056 + 0.022*sl 0.063 + 0.020*sl 0.063 + 0.020*sl d to y t r 0.240 0.133 + 0.053*sl 0.125 + 0.055*sl 0.116 + 0.056*sl t f 0.152 0.111 + 0.020*sl 0.103 + 0.023*sl 0.090 + 0.024*sl t plh 0.145 0.096 + 0.025*sl 0.098 + 0.024*sl 0.098 + 0.024*sl t phl 0.109 0.081 + 0.014*sl 0.085 + 0.013*sl 0.086 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.155 0.100 + 0.027*sl 0.099 + 0.028*sl 0.093 + 0.028*sl t f 0.114 0.074 + 0.020*sl 0.072 + 0.020*sl 0.065 + 0.021*sl t plh 0.229 0.204 + 0.013*sl 0.206 + 0.012*sl 0.208 + 0.012*sl t phl 0.218 0.196 + 0.011*sl 0.200 + 0.010*sl 0.204 + 0.010*sl b to y t r 0.155 0.102 + 0.027*sl 0.099 + 0.028*sl 0.093 + 0.028*sl t f 0.115 0.076 + 0.019*sl 0.073 + 0.020*sl 0.066 + 0.021*sl t plh 0.242 0.217 + 0.013*sl 0.219 + 0.012*sl 0.220 + 0.012*sl t phl 0.214 0.191 + 0.011*sl 0.196 + 0.010*sl 0.200 + 0.010*sl c to y t r 0.199 0.150 + 0.025*sl 0.142 + 0.027*sl 0.121 + 0.028*sl t f 0.124 0.088 + 0.018*sl 0.081 + 0.020*sl 0.068 + 0.021*sl t plh 0.107 0.081 + 0.013*sl 0.084 + 0.012*sl 0.082 + 0.012*sl t phl 0.079 0.055 + 0.012*sl 0.062 + 0.010*sl 0.065 + 0.010*sl d to y t r 0.188 0.136 + 0.026*sl 0.131 + 0.028*sl 0.119 + 0.028*sl t f 0.128 0.108 + 0.010*sl 0.106 + 0.011*sl 0.090 + 0.012*sl t plh 0.118 0.091 + 0.013*sl 0.095 + 0.012*sl 0.095 + 0.012*sl t phl 0.091 0.076 + 0.008*sl 0.081 + 0.006*sl 0.083 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-265 STD111 scg20/scg20d2 2-nor into 2-nor with 1x/2x drive logic symbol cell data input load (sl) gate count scg20 scg20d2 scg20 scg20d2 abcabc 1.67 2.33 0.9 0.9 1.1 0.9 0.9 2.3 y c a b truth table abc y 1x0 1 x10 1 other states 0
STD111 3-266 samsung asic scg20/scg20d2 2-nor into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg20 scg20d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.195 0.087 + 0.054*sl 0.083 + 0.055*sl 0.081 + 0.055*sl t f 0.100 0.061 + 0.020*sl 0.062 + 0.019*sl 0.062 + 0.019*sl t plh 0.149 0.101 + 0.024*sl 0.102 + 0.024*sl 0.103 + 0.024*sl t phl 0.175 0.146 + 0.014*sl 0.156 + 0.012*sl 0.168 + 0.011*sl b to y t r 0.196 0.089 + 0.054*sl 0.084 + 0.055*sl 0.082 + 0.055*sl t f 0.100 0.061 + 0.019*sl 0.062 + 0.019*sl 0.062 + 0.019*sl t plh 0.163 0.115 + 0.024*sl 0.116 + 0.024*sl 0.116 + 0.024*sl t phl 0.173 0.144 + 0.015*sl 0.155 + 0.012*sl 0.166 + 0.011*sl c to y t r 0.209 0.106 + 0.052*sl 0.097 + 0.054*sl 0.088 + 0.055*sl t f 0.126 0.094 + 0.016*sl 0.090 + 0.017*sl 0.072 + 0.019*sl t plh 0.118 0.069 + 0.024*sl 0.073 + 0.024*sl 0.071 + 0.024*sl t phl 0.077 0.049 + 0.014*sl 0.061 + 0.011*sl 0.064 + 0.010*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.135 0.082 + 0.027*sl 0.079 + 0.027*sl 0.073 + 0.028*sl t f 0.094 0.072 + 0.011*sl 0.076 + 0.010*sl 0.081 + 0.009*sl t plh 0.144 0.119 + 0.012*sl 0.121 + 0.012*sl 0.121 + 0.012*sl t phl 0.194 0.175 + 0.009*sl 0.185 + 0.007*sl 0.205 + 0.006*sl b to y t r 0.136 0.083 + 0.026*sl 0.080 + 0.027*sl 0.074 + 0.028*sl t f 0.095 0.073 + 0.011*sl 0.079 + 0.010*sl 0.081 + 0.009*sl t plh 0.155 0.131 + 0.012*sl 0.132 + 0.012*sl 0.132 + 0.012*sl t phl 0.192 0.173 + 0.009*sl 0.183 + 0.007*sl 0.203 + 0.006*sl c to y t r 0.150 0.100 + 0.025*sl 0.094 + 0.027*sl 0.081 + 0.028*sl t f 0.107 0.090 + 0.008*sl 0.090 + 0.008*sl 0.073 + 0.009*sl t plh 0.090 0.064 + 0.013*sl 0.069 + 0.012*sl 0.069 + 0.012*sl t phl 0.059 0.042 + 0.008*sl 0.052 + 0.006*sl 0.062 + 0.005*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-267 STD111 scg21/scg21d2 2-nor into 3-nor with 1x/2x drive logic symbol cell data input load (sl) gate count scg21 scg21d2 scg21 scg21d2 abcdabcd 0.9 0.9 1.0 1.0 0.9 0.9 2.1 2.2 2.00 2.67 y c a b d truth table abcdy 1x001 x1001 other states 0
STD111 3-268 samsung asic scg21/scg21d2 2-nor into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg21 scg21d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.317 0.153 + 0.082*sl 0.152 + 0.083*sl 0.154 + 0.082*sl t f 0.116 0.067 + 0.025*sl 0.071 + 0.023*sl 0.065 + 0.024*sl t plh 0.185 0.113 + 0.036*sl 0.114 + 0.036*sl 0.115 + 0.035*sl t phl 0.189 0.156 + 0.016*sl 0.166 + 0.014*sl 0.175 + 0.013*sl b to y t r 0.318 0.154 + 0.082*sl 0.152 + 0.083*sl 0.154 + 0.082*sl t f 0.116 0.068 + 0.024*sl 0.071 + 0.024*sl 0.067 + 0.024*sl t plh 0.198 0.126 + 0.036*sl 0.127 + 0.036*sl 0.128 + 0.035*sl t phl 0.188 0.155 + 0.017*sl 0.164 + 0.014*sl 0.174 + 0.013*sl c to y t r 0.333 0.175 + 0.079*sl 0.167 + 0.081*sl 0.157 + 0.082*sl t f 0.139 0.099 + 0.020*sl 0.092 + 0.022*sl 0.076 + 0.024*sl t plh 0.174 0.102 + 0.036*sl 0.103 + 0.035*sl 0.103 + 0.035*sl t phl 0.094 0.064 + 0.015*sl 0.073 + 0.013*sl 0.073 + 0.013*sl d to y t r 0.329 0.170 + 0.080*sl 0.163 + 0.082*sl 0.156 + 0.082*sl t f 0.160 0.120 + 0.020*sl 0.111 + 0.022*sl 0.098 + 0.024*sl t plh 0.181 0.109 + 0.036*sl 0.111 + 0.036*sl 0.112 + 0.035*sl t phl 0.101 0.071 + 0.015*sl 0.078 + 0.013*sl 0.080 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.216 0.135 + 0.040*sl 0.132 + 0.041*sl 0.131 + 0.041*sl t f 0.101 0.075 + 0.013*sl 0.080 + 0.012*sl 0.081 + 0.012*sl t plh 0.158 0.123 + 0.018*sl 0.122 + 0.018*sl 0.123 + 0.018*sl t phl 0.203 0.182 + 0.010*sl 0.191 + 0.008*sl 0.211 + 0.007*sl b to y t r 0.217 0.136 + 0.040*sl 0.133 + 0.041*sl 0.132 + 0.041*sl t f 0.102 0.077 + 0.012*sl 0.079 + 0.012*sl 0.080 + 0.012*sl t plh 0.171 0.136 + 0.018*sl 0.136 + 0.018*sl 0.136 + 0.018*sl t phl 0.201 0.180 + 0.010*sl 0.190 + 0.008*sl 0.209 + 0.007*sl c to y t r 0.235 0.158 + 0.038*sl 0.151 + 0.040*sl 0.138 + 0.041*sl t f 0.116 0.095 + 0.010*sl 0.094 + 0.010*sl 0.074 + 0.012*sl t plh 0.128 0.090 + 0.019*sl 0.094 + 0.018*sl 0.095 + 0.018*sl t phl 0.074 0.056 + 0.009*sl 0.064 + 0.007*sl 0.070 + 0.006*sl d to y t r 0.230 0.152 + 0.039*sl 0.146 + 0.041*sl 0.136 + 0.041*sl t f 0.136 0.116 + 0.010*sl 0.113 + 0.011*sl 0.096 + 0.012*sl t plh 0.137 0.099 + 0.019*sl 0.103 + 0.018*sl 0.105 + 0.018*sl t phl 0.080 0.062 + 0.009*sl 0.070 + 0.007*sl 0.076 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-269 STD111 scg22/scg22d2 2-nand into 2-or into 2-nand with 1x/2x drive logic symbol cell data input load (sl) gate count scg22 scg22d2 scg22 scg22d2 abcdabcd 0.8 0.9 1.0 1.1 0.8 0.8 2.0 2.3 2.00 3.00 a b c d y truth table abcdy 110x1 xxx01 other states 0
STD111 3-270 samsung asic scg22/scg22d2 2-nand into 2-or into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg22 scg22d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.236 0.128 + 0.054*sl 0.124 + 0.055*sl 0.119 + 0.056*sl t f 0.174 0.090 + 0.042*sl 0.088 + 0.043*sl 0.082 + 0.043*sl t plh 0.182 0.133 + 0.025*sl 0.135 + 0.024*sl 0.136 + 0.024*sl t phl 0.195 0.151 + 0.022*sl 0.154 + 0.021*sl 0.155 + 0.021*sl b to y t r 0.236 0.128 + 0.054*sl 0.124 + 0.055*sl 0.119 + 0.056*sl t f 0.175 0.092 + 0.042*sl 0.088 + 0.043*sl 0.083 + 0.043*sl t plh 0.179 0.129 + 0.025*sl 0.131 + 0.024*sl 0.132 + 0.024*sl t phl 0.207 0.163 + 0.022*sl 0.166 + 0.021*sl 0.168 + 0.021*sl c to y t r 0.245 0.139 + 0.053*sl 0.132 + 0.055*sl 0.123 + 0.056*sl t f 0.214 0.141 + 0.037*sl 0.130 + 0.040*sl 0.113 + 0.041*sl t plh 0.131 0.081 + 0.025*sl 0.085 + 0.024*sl 0.085 + 0.024*sl t phl 0.139 0.098 + 0.020*sl 0.098 + 0.020*sl 0.098 + 0.020*sl d to y t r 0.167 0.118 + 0.024*sl 0.111 + 0.026*sl 0.097 + 0.028*sl t f 0.203 0.124 + 0.039*sl 0.118 + 0.041*sl 0.111 + 0.042*sl t plh 0.104 0.076 + 0.014*sl 0.082 + 0.012*sl 0.081 + 0.012*sl t phl 0.131 0.089 + 0.021*sl 0.091 + 0.020*sl 0.092 + 0.020*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.172 0.119 + 0.026*sl 0.115 + 0.028*sl 0.108 + 0.028*sl t f 0.129 0.087 + 0.021*sl 0.087 + 0.021*sl 0.078 + 0.022*sl t plh 0.174 0.148 + 0.013*sl 0.152 + 0.012*sl 0.154 + 0.012*sl t phl 0.191 0.167 + 0.012*sl 0.171 + 0.011*sl 0.176 + 0.011*sl b to y t r 0.173 0.121 + 0.026*sl 0.115 + 0.027*sl 0.107 + 0.028*sl t f 0.131 0.091 + 0.020*sl 0.088 + 0.021*sl 0.079 + 0.022*sl t plh 0.169 0.143 + 0.013*sl 0.146 + 0.012*sl 0.149 + 0.012*sl t phl 0.201 0.177 + 0.012*sl 0.182 + 0.011*sl 0.186 + 0.011*sl c to y t r 0.178 0.127 + 0.026*sl 0.121 + 0.027*sl 0.110 + 0.028*sl t f 0.169 0.134 + 0.017*sl 0.128 + 0.019*sl 0.107 + 0.021*sl t plh 0.100 0.073 + 0.014*sl 0.078 + 0.012*sl 0.081 + 0.012*sl t phl 0.110 0.088 + 0.011*sl 0.091 + 0.010*sl 0.091 + 0.010*sl d to y t r 0.134 0.112 + 0.011*sl 0.106 + 0.013*sl 0.090 + 0.014*sl t f 0.155 0.118 + 0.018*sl 0.112 + 0.020*sl 0.101 + 0.021*sl t plh 0.085 0.069 + 0.008*sl 0.074 + 0.006*sl 0.077 + 0.006*sl t phl 0.101 0.079 + 0.011*sl 0.082 + 0.010*sl 0.083 + 0.010*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-271 STD111 dl1d2/dl1d4 1ns delay cell with 2x/4x drive logic symbol switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) dl1d2 dl1d4 ay path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.074 0.047 + 0.013*sl 0.047 + 0.013*sl 0.036 + 0.014*sl t f 0.067 0.042 + 0.012*sl 0.047 + 0.011*sl 0.039 + 0.012*sl t plh 0.996 0.981 + 0.008*sl 0.986 + 0.006*sl 0.989 + 0.006*sl t phl 0.998 0.982 + 0.008*sl 0.988 + 0.007*sl 0.995 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.075 0.063 + 0.006*sl 0.062 + 0.006*sl 0.052 + 0.007*sl t f 0.070 0.056 + 0.007*sl 0.060 + 0.006*sl 0.055 + 0.006*sl t plh 1.027 1.018 + 0.005*sl 1.023 + 0.003*sl 1.033 + 0.003*sl t phl 1.025 1.015 + 0.005*sl 1.020 + 0.004*sl 1.036 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl truth table cell data ay 00 11 input load (sl) gate count dl1d2 dl1d4 dl1d2 dl1d4 aa 3.33 4.00 0.7 0.7
STD111 3-272 samsung asic dl2d2/dl2d4 2ns delay cell with 2x/4x drive logic symbol switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) dl2d2 dl2d4 ay path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.076 0.051 + 0.013*sl 0.049 + 0.013*sl 0.038 + 0.014*sl t f 0.074 0.050 + 0.012*sl 0.053 + 0.011*sl 0.043 + 0.012*sl t plh 1.990 1.975 + 0.008*sl 1.979 + 0.006*sl 1.983 + 0.006*sl t phl 2.012 1.995 + 0.009*sl 2.001 + 0.007*sl 2.010 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.078 0.065 + 0.006*sl 0.064 + 0.006*sl 0.053 + 0.007*sl t f 0.077 0.065 + 0.006*sl 0.067 + 0.005*sl 0.060 + 0.006*sl t plh 2.020 2.011 + 0.005*sl 2.016 + 0.003*sl 2.026 + 0.003*sl t phl 2.040 2.030 + 0.005*sl 2.035 + 0.004*sl 2.051 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl truth table cell data ay 00 11 input load (sl) gate count dl2d2 dl2d4 dl2d2 dl2d4 aa 3.67 4.33 0.7 0.7
samsung asic 3-273 STD111 dl3d2/dl3d4 3ns delay cell with 2x/4x drive logic symbol switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) dl3d2 dl3d4 ay path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.076 0.050 + 0.013*sl 0.048 + 0.013*sl 0.038 + 0.014*sl t f 0.072 0.050 + 0.011*sl 0.051 + 0.011*sl 0.042 + 0.012*sl t plh 3.020 3.004 + 0.008*sl 3.009 + 0.006*sl 3.013 + 0.006*sl t phl 3.029 3.012 + 0.008*sl 3.018 + 0.007*sl 3.026 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.076 0.063 + 0.007*sl 0.064 + 0.006*sl 0.053 + 0.007*sl t f 0.075 0.064 + 0.006*sl 0.064 + 0.006*sl 0.059 + 0.006*sl t plh 3.049 3.040 + 0.005*sl 3.044 + 0.003*sl 3.055 + 0.003*sl t phl 3.057 3.047 + 0.005*sl 3.052 + 0.004*sl 3.068 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl truth table cell data ay 00 11 input load (sl) gate count dl3d2 dl3d4 dl3d2 dl3d4 aa 4.67 5.33 0.7 0.7
STD111 3-274 samsung asic dl4d2/dl4d4 4ns delay cell with 2x/4x drive logic symbol switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) dl4d2 dl4d4 ay path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.075 0.050 + 0.013*sl 0.047 + 0.013*sl 0.039 + 0.014*sl t f 0.073 0.049 + 0.012*sl 0.054 + 0.011*sl 0.043 + 0.012*sl t plh 3.997 3.981 + 0.008*sl 3.986 + 0.006*sl 3.990 + 0.006*sl t phl 4.030 4.013 + 0.009*sl 4.020 + 0.007*sl 4.028 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.078 0.064 + 0.007*sl 0.065 + 0.006*sl 0.053 + 0.007*sl t f 0.077 0.065 + 0.006*sl 0.067 + 0.005*sl 0.061 + 0.006*sl t plh 4.027 4.018 + 0.005*sl 4.022 + 0.003*sl 4.033 + 0.003*sl t phl 4.061 4.050 + 0.005*sl 4.056 + 0.004*sl 4.072 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl truth table cell data ay 00 11 input load (sl) gate count dl4d2 dl4d4 dl4d2 dl4d4 aa 5.00 5.67 0.7 0.7
samsung asic 3-275 STD111 dl5d2/dl5d4 5ns delay cell with 2x/4x drive logic symbol switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) dl5d2 dl5d4 ay path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.076 0.051 + 0.013*sl 0.047 + 0.014*sl 0.038 + 0.014*sl t f 0.077 0.053 + 0.012*sl 0.055 + 0.011*sl 0.044 + 0.012*sl t plh 5.043 5.027 + 0.008*sl 5.032 + 0.006*sl 5.037 + 0.006*sl t phl 5.033 5.015 + 0.009*sl 5.022 + 0.007*sl 5.031 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.079 0.066 + 0.007*sl 0.066 + 0.006*sl 0.054 + 0.007*sl t f 0.080 0.068 + 0.006*sl 0.069 + 0.006*sl 0.064 + 0.006*sl t plh 5.074 5.064 + 0.005*sl 5.069 + 0.003*sl 5.080 + 0.003*sl t phl 5.064 5.054 + 0.005*sl 5.059 + 0.004*sl 5.076 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl truth table cell data ay 00 11 input load (sl) gate count dl5d2 dl5d4 dl5d2 dl5d4 aa 5.00 5.67 0.7 0.7
STD111 3-276 samsung asic dl10d2/dl10d4 10ns delay cell with 2x/4x drive logic symbol switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) dl10d2 dl10d4 ay path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.077 0.052 + 0.013*sl 0.048 + 0.013*sl 0.038 + 0.014*sl t f 0.079 0.056 + 0.012*sl 0.058 + 0.011*sl 0.046 + 0.012*sl t plh 10.012 9.997 + 0.008*sl 10.001 + 0.007*sl 10.007 + 0.006*sl t phl 10.056 10.038 + 0.009*sl 10.046 + 0.007*sl 10.054 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.079 0.066 + 0.006*sl 0.066 + 0.006*sl 0.053 + 0.007*sl t f 0.081 0.070 + 0.006*sl 0.070 + 0.006*sl 0.064 + 0.006*sl t plh 10.042 10.033 + 0.005*sl 10.038 + 0.004*sl 10.049 + 0.003*sl t phl 10.088 10.077 + 0.006*sl 10.084 + 0.004*sl 10.100 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl truth table cell data ay 00 11 input load (sl) gate count dl10d2 dl10d4 dl10d2 dl2d4 aa 6.67 4.33 0.7 0.7
samsung asic 3-277 STD111 ivdh/iv/ivd2/ivd3/ivd4/ivd6/ivd8/ivd16 inverter with 0.5x/1x/2x/3x/4x/6x/8x/16x drive logic symbol cell data input load (sl) ivdh iv ivd2 ivd3 ivd4 ivd6 ivd8 ivd16 aaaaaaaa 0.5 1.0 2.0 3.0 4.0 6.0 8.1 16.5 gate count ivdh iv ivd2 ivd3 ivd4 ivd6 ivd8 ivd16 0.67 0.67 1.00 1.33 1.67 2.33 2.67 5.00 a y truth table ay 01 10
STD111 3-278 samsung asic ivdh/iv/ivd2/ivd3/ivd4/ivd6/ivd8/ivd16 inverter with 0.5x/1x/2x/3x/4x/6x/8x/16x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ivdh iv ivd2 ivd3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.191 0.085 + 0.053*sl 0.064 + 0.059*sl 0.042 + 0.061*sl t f 0.177 0.077 + 0.050*sl 0.055 + 0.056*sl 0.033 + 0.058*sl t plh 0.109 0.052 + 0.028*sl 0.061 + 0.026*sl 0.059 + 0.026*sl t phl 0.118 0.056 + 0.031*sl 0.061 + 0.030*sl 0.059 + 0.030*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.132 0.084 + 0.024*sl 0.076 + 0.026*sl 0.061 + 0.028*sl t f 0.117 0.075 + 0.021*sl 0.068 + 0.023*sl 0.052 + 0.025*sl t plh 0.077 0.045 + 0.016*sl 0.058 + 0.012*sl 0.060 + 0.012*sl t phl 0.079 0.046 + 0.017*sl 0.059 + 0.013*sl 0.059 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.096 0.069 + 0.014*sl 0.074 + 0.012*sl 0.052 + 0.014*sl t f 0.087 0.062 + 0.012*sl 0.067 + 0.011*sl 0.046 + 0.012*sl t plh 0.053 0.033 + 0.010*sl 0.045 + 0.007*sl 0.056 + 0.006*sl t phl 0.053 0.032 + 0.011*sl 0.045 + 0.007*sl 0.054 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.091 0.073 + 0.009*sl 0.076 + 0.008*sl 0.053 + 0.009*sl t f 0.082 0.065 + 0.008*sl 0.069 + 0.007*sl 0.045 + 0.008*sl t plh 0.049 0.035 + 0.007*sl 0.045 + 0.005*sl 0.057 + 0.004*sl t phl 0.050 0.035 + 0.007*sl 0.045 + 0.005*sl 0.055 + 0.004*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-279 STD111 ivdh/iv/ivd2/ivd3/ivd4/ivd6/ivd8/ivd16 inverter with 0.5x/1x/2x/3x/4x/6x/8x/16x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ivd4 ivd6 ivd8 ivd16 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.084 0.070 + 0.007*sl 0.073 + 0.006*sl 0.056 + 0.007*sl t f 0.075 0.061 + 0.007*sl 0.066 + 0.006*sl 0.049 + 0.006*sl t plh 0.043 0.031 + 0.006*sl 0.040 + 0.004*sl 0.056 + 0.003*sl t phl 0.043 0.031 + 0.006*sl 0.039 + 0.004*sl 0.055 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.079 0.070 + 0.005*sl 0.071 + 0.004*sl 0.037 + 0.005*sl t f 0.070 0.061 + 0.005*sl 0.064 + 0.004*sl 0.030 + 0.004*sl t plh 0.039 0.030 + 0.004*sl 0.038 + 0.002*sl 0.054 + 0.002*sl t phl 0.038 0.030 + 0.004*sl 0.037 + 0.002*sl 0.053 + 0.002*sl *group1 : sl < 4, *group2 : 4 sl < < = = 85, *group3 : 85 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.077 0.070 + 0.003*sl 0.070 + 0.003*sl 0.046 + 0.004*sl t f 0.068 0.061 + 0.004*sl 0.064 + 0.003*sl 0.038 + 0.003*sl t plh 0.037 0.031 + 0.003*sl 0.037 + 0.002*sl 0.055 + 0.002*sl t phl 0.036 0.030 + 0.003*sl 0.035 + 0.002*sl 0.053 + 0.002*sl *group1 : sl < 4, *group2 : 4 sl < < = = 85, *group3 : 85 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.073 0.069 + 0.002*sl 0.071 + 0.002*sl 0.061 + 0.002*sl t f 0.064 0.061 + 0.002*sl 0.062 + 0.001*sl 0.055 + 0.002*sl t plh 0.033 0.030 + 0.002*sl 0.033 + 0.001*sl 0.056 + 0.001*sl t phl 0.032 0.029 + 0.002*sl 0.031 + 0.001*sl 0.055 + 0.001*sl *group1 : sl < 4, *group2 : 4 sl < < = = 85, *group3 : 85 < sl
STD111 3-280 samsung asic ivcd(11/13)/ivcd(22/26)/ivcd44 1x iv into (1x/3x) iv/2x iv into (2x/6x) iv/4x iv into 4x iv logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ivcd11 ivcd13 input load (sl) gate count ivcd11 ivcd13 ivcd22 ivcd26 ivcd44 ivcd11 ivcd13 ivcd22 ivcd26 ivcd44 aaaaa 1.0 0.9 1.9 1.9 3.7 1.00 1.67 1.67 2.67 2.67 a y yn path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.161 0.114 + 0.024*sl 0.105 + 0.026*sl 0.089 + 0.028*sl t f 0.157 0.107 + 0.025*sl 0.097 + 0.028*sl 0.081 + 0.029*sl t plh 0.090 0.060 + 0.015*sl 0.070 + 0.012*sl 0.070 + 0.012*sl t phl 0.105 0.071 + 0.017*sl 0.076 + 0.015*sl 0.075 + 0.016*sl y to yn t r 0.124 0.074 + 0.025*sl 0.064 + 0.028*sl 0.046 + 0.029*sl t f 0.130 0.083 + 0.024*sl 0.074 + 0.026*sl 0.058 + 0.028*sl t plh 0.087 0.050 + 0.019*sl 0.062 + 0.015*sl 0.060 + 0.016*sl t phl 0.073 0.040 + 0.016*sl 0.055 + 0.013*sl 0.058 + 0.012*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.216 0.168 + 0.024*sl 0.154 + 0.028*sl 0.123 + 0.029*sl t f 0.215 0.163 + 0.026*sl 0.151 + 0.029*sl 0.127 + 0.030*sl t plh 0.117 0.091 + 0.013*sl 0.094 + 0.012*sl 0.093 + 0.012*sl t phl 0.134 0.103 + 0.016*sl 0.103 + 0.016*sl 0.102 + 0.016*sl y to yn t r 0.084 0.065 + 0.010*sl 0.068 + 0.009*sl 0.041 + 0.010*sl t f 0.092 0.074 + 0.009*sl 0.076 + 0.008*sl 0.052 + 0.009*sl t plh 0.056 0.040 + 0.008*sl 0.049 + 0.005*sl 0.057 + 0.005*sl t phl 0.046 0.031 + 0.007*sl 0.041 + 0.005*sl 0.056 + 0.004*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl truth table ayyn 101 010
samsung asic 3-281 STD111 ivcd(11/13)/ivcd(22/26)/ivcd44 1x iv into (1x/3x) iv/2x iv into (2x/6x) iv/4x iv into 4x iv switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ivcd22 ivcd26 ivcd44 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.129 0.106 + 0.012*sl 0.102 + 0.013*sl 0.083 + 0.014*sl t f 0.124 0.101 + 0.012*sl 0.094 + 0.013*sl 0.075 + 0.015*sl t plh 0.069 0.052 + 0.009*sl 0.060 + 0.007*sl 0.067 + 0.006*sl t phl 0.081 0.061 + 0.010*sl 0.068 + 0.008*sl 0.070 + 0.008*sl y to yn t r 0.091 0.064 + 0.014*sl 0.065 + 0.013*sl 0.044 + 0.015*sl t f 0.099 0.073 + 0.013*sl 0.075 + 0.012*sl 0.053 + 0.014*sl t plh 0.061 0.038 + 0.011*sl 0.050 + 0.008*sl 0.056 + 0.008*sl t phl 0.050 0.030 + 0.010*sl 0.043 + 0.007*sl 0.055 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.185 0.163 + 0.011*sl 0.152 + 0.014*sl 0.114 + 0.015*sl t f 0.184 0.159 + 0.013*sl 0.151 + 0.015*sl 0.119 + 0.015*sl t plh 0.100 0.086 + 0.007*sl 0.089 + 0.006*sl 0.090 + 0.006*sl t phl 0.113 0.097 + 0.008*sl 0.098 + 0.008*sl 0.098 + 0.008*sl y to yn t r 0.072 0.062 + 0.005*sl 0.064 + 0.005*sl 0.027 + 0.005*sl t f 0.080 0.070 + 0.005*sl 0.071 + 0.004*sl 0.037 + 0.005*sl t plh 0.045 0.035 + 0.005*sl 0.043 + 0.003*sl 0.055 + 0.003*sl t phl 0.037 0.028 + 0.004*sl 0.036 + 0.002*sl 0.054 + 0.002*sl *group1 : sl < 4, *group2 : 4 sl < < = = 85, *group3 : 85 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.118 0.107 + 0.006*sl 0.106 + 0.006*sl 0.086 + 0.007*sl t f 0.112 0.100 + 0.006*sl 0.099 + 0.007*sl 0.078 + 0.007*sl t plh 0.061 0.051 + 0.005*sl 0.056 + 0.003*sl 0.067 + 0.003*sl t phl 0.071 0.060 + 0.005*sl 0.065 + 0.004*sl 0.070 + 0.004*sl y to yn t r 0.077 0.062 + 0.008*sl 0.066 + 0.007*sl 0.045 + 0.007*sl t f 0.084 0.070 + 0.007*sl 0.074 + 0.006*sl 0.056 + 0.007*sl t plh 0.049 0.036 + 0.007*sl 0.045 + 0.004*sl 0.056 + 0.004*sl t phl 0.040 0.027 + 0.006*sl 0.037 + 0.004*sl 0.055 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-282 samsung asic ivt/ivtd2/ivtd4/ivtd8/ivtd16 inverting tri-state buffer with enable high, 1x/2x/4x/8x/16x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ivt ivtd2 input load (sl) output load (sl) ivt ivtd2 ivtd4 ivtd 8 ivtd 16 ivt ivtd2 ivtd4 ivtd 8 ivtd 16 aeaeaea e a e yyyyy 0.7 1.3 0.7 1.5 0.8 1.7 1.0 2.8 1.0 2.8 0.9 1.1 2.1 4.3 8.3 gate count ivt ivtd2 ivtd4 ivtd 8 ivtd 16 2.67 3.00 3.67 5.67 8.00 a y e path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.105 0.050 + 0.027*sl 0.048 + 0.028*sl 0.044 + 0.028*sl t f 0.097 0.049 + 0.024*sl 0.052 + 0.023*sl 0.049 + 0.024*sl t plh 0.197 0.169 + 0.014*sl 0.175 + 0.013*sl 0.178 + 0.012*sl t phl 0.228 0.196 + 0.016*sl 0.206 + 0.014*sl 0.214 + 0.013*sl e to y t r 0.118 0.063 + 0.028*sl 0.057 + 0.029*sl 0.050 + 0.030*sl t f 0.106 0.056 + 0.025*sl 0.060 + 0.024*sl 0.055 + 0.024*sl t plh 0.120 0.090 + 0.015*sl 0.098 + 0.013*sl 0.101 + 0.013*sl t phl 0.191 0.158 + 0.017*sl 0.169 + 0.014*sl 0.178 + 0.013*sl t plz 0.140 0.140 + 0.000*sl 0.140 + 0.000*sl 0.141 + 0.000*sl t phz 0.142 0.142 + 0.000*sl 0.142 + 0.000*sl 0.142 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.072 0.042 + 0.015*sl 0.046 + 0.014*sl 0.041 + 0.014*sl t f 0.071 0.041 + 0.015*sl 0.053 + 0.012*sl 0.054 + 0.012*sl t plh 0.194 0.177 + 0.009*sl 0.184 + 0.007*sl 0.192 + 0.006*sl t phl 0.219 0.202 + 0.009*sl 0.207 + 0.007*sl 0.223 + 0.006*sl e to y t r 0.082 0.054 + 0.014*sl 0.055 + 0.014*sl 0.045 + 0.014*sl t f 0.075 0.047 + 0.014*sl 0.055 + 0.012*sl 0.054 + 0.012*sl t plh 0.108 0.090 + 0.009*sl 0.099 + 0.007*sl 0.110 + 0.006*sl t phl 0.182 0.160 + 0.011*sl 0.172 + 0.008*sl 0.189 + 0.007*sl t plz 0.150 0.150 + 0.000*sl 0.149 + 0.000*sl 0.149 + 0.000*sl t phz 0.153 0.153 + 0.000*sl 0.153 + 0.000*sl 0.153 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl truth table aey x 0 hi-z 011 110
samsung asic 3-283 STD111 ivt/ivtd2/ivtd4/ivtd8/ivtd16 inverting tri-state buffer with enable high, 1x/2x/4x/8x/16x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ivtd4 ivtd8 ivtd16 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.063 0.046 + 0.008*sl 0.051 + 0.007*sl 0.050 + 0.007*sl t f 0.066 0.054 + 0.006*sl 0.053 + 0.006*sl 0.057 + 0.006*sl t plh 0.200 0.190 + 0.005*sl 0.196 + 0.004*sl 0.212 + 0.003*sl t phl 0.228 0.217 + 0.005*sl 0.222 + 0.004*sl 0.240 + 0.003*sl e to y t r 0.073 0.059 + 0.007*sl 0.060 + 0.007*sl 0.054 + 0.007*sl t f 0.065 0.049 + 0.008*sl 0.056 + 0.006*sl 0.062 + 0.006*sl t plh 0.114 0.101 + 0.006*sl 0.111 + 0.004*sl 0.130 + 0.003*sl t phl 0.175 0.161 + 0.007*sl 0.170 + 0.004*sl 0.196 + 0.003*sl t plz 0.171 0.171 + 0.000*sl 0.171 + 0.000*sl 0.171 + 0.000*sl t phz 0.186 0.186 + 0.000*sl 0.186 + 0.000*sl 0.187 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.055 0.046 + 0.005*sl 0.050 + 0.003*sl 0.046 + 0.004*sl t f 0.061 0.056 + 0.003*sl 0.055 + 0.003*sl 0.051 + 0.003*sl t plh 0.220 0.214 + 0.003*sl 0.218 + 0.002*sl 0.241 + 0.002*sl t phl 0.242 0.237 + 0.003*sl 0.240 + 0.002*sl 0.262 + 0.002*sl e to y t r 0.066 0.058 + 0.004*sl 0.059 + 0.003*sl 0.047 + 0.004*sl t f 0.054 0.046 + 0.004*sl 0.050 + 0.003*sl 0.052 + 0.003*sl t plh 0.107 0.099 + 0.004*sl 0.106 + 0.002*sl 0.132 + 0.002*sl t phl 0.185 0.178 + 0.004*sl 0.184 + 0.002*sl 0.218 + 0.002*sl t plz 0.181 0.181 + 0.000*sl 0.181 + 0.000*sl 0.181 + 0.000*sl t phz 0.181 0.181 + 0.000*sl 0.182 + 0.000*sl 0.182 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 85, *group3 : 85 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.061 0.056 + 0.003*sl 0.059 + 0.002*sl 0.076 + 0.002*sl t f 0.087 0.084 + 0.002*sl 0.085 + 0.001*sl 0.079 + 0.001*sl t plh 0.251 0.247 + 0.002*sl 0.249 + 0.001*sl 0.280 + 0.001*sl t phl 0.280 0.277 + 0.002*sl 0.279 + 0.001*sl 0.298 + 0.001*sl e to y t r 0.074 0.068 + 0.003*sl 0.073 + 0.002*sl 0.079 + 0.002*sl t f 0.061 0.056 + 0.003*sl 0.059 + 0.002*sl 0.079 + 0.001*sl t plh 0.135 0.129 + 0.003*sl 0.134 + 0.001*sl 0.172 + 0.001*sl t phl 0.203 0.198 + 0.002*sl 0.202 + 0.001*sl 0.242 + 0.001*sl t plz 0.215 0.215 + 0.000*sl 0.215 + 0.000*sl 0.216 + 0.000*sl t phz 0.269 0.268 + 0.000*sl 0.269 + 0.000*sl 0.270 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 85, *group3 : 85 < sl
STD111 3-284 samsung asic ivtn/ivtnd2/ivtnd4/ivtnd8/ivtnd16 inverting tri-state buffer with enable low, 1x/2x/4x/8x/16x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ivtn ivtnd2 input load (sl) output load (sl) ivtn ivtnd2 ivtnd4 ivtnd8 ivtnd16 ivtn ivtnd2 ivtnd4 ivtnd8 ivtnd16 a enaenaenaenaen y y y y y 0.7 1.4 0.7 1.6 0.8 1.1 1.0 3.0 1.0 3.0 0.9 1.1 2.1 4.3 8.3 gate count ivtn ivtnd2 ivtnd4 ivtnd8 ivtnd16 2.67 3.00 3.67 5.67 8.00 ay en path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.106 0.050 + 0.028*sl 0.049 + 0.028*sl 0.045 + 0.028*sl t f 0.097 0.048 + 0.024*sl 0.052 + 0.023*sl 0.049 + 0.024*sl t plh 0.198 0.169 + 0.014*sl 0.175 + 0.013*sl 0.179 + 0.012*sl t phl 0.227 0.195 + 0.016*sl 0.204 + 0.013*sl 0.212 + 0.013*sl en to y t r 0.114 0.056 + 0.029*sl 0.054 + 0.029*sl 0.047 + 0.030*sl t f 0.108 0.060 + 0.024*sl 0.061 + 0.024*sl 0.056 + 0.024*sl t plh 0.174 0.145 + 0.015*sl 0.152 + 0.013*sl 0.155 + 0.013*sl t phl 0.147 0.113 + 0.017*sl 0.125 + 0.014*sl 0.134 + 0.013*sl t plz 0.079 0.079 + 0.000*sl 0.079 + 0.000*sl 0.079 + 0.000*sl t phz 0.178 0.178 + 0.000*sl 0.178 + 0.000*sl 0.178 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.072 0.044 + 0.014*sl 0.046 + 0.014*sl 0.042 + 0.014*sl t f 0.070 0.042 + 0.014*sl 0.050 + 0.012*sl 0.049 + 0.012*sl t plh 0.196 0.178 + 0.009*sl 0.185 + 0.007*sl 0.195 + 0.006*sl t phl 0.219 0.200 + 0.009*sl 0.208 + 0.007*sl 0.222 + 0.006*sl en to y t r 0.084 0.059 + 0.012*sl 0.053 + 0.014*sl 0.044 + 0.014*sl t f 0.077 0.049 + 0.014*sl 0.056 + 0.012*sl 0.055 + 0.012*sl t plh 0.166 0.147 + 0.009*sl 0.157 + 0.007*sl 0.167 + 0.006*sl t phl 0.131 0.109 + 0.011*sl 0.121 + 0.008*sl 0.139 + 0.007*sl t plz 0.086 0.086 + 0.000*sl 0.086 + 0.000*sl 0.086 + 0.000*sl t phz 0.203 0.203 + 0.000*sl 0.204 + 0.000*sl 0.202 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl truth table aeny x 1 hi-z 001 100
samsung asic 3-285 STD111 ivtn/ivtnd2/ivtnd4/ivtnd8/ivtnd16 inverting tri-state buffer with enable low, 1x/2x/4x/8x/16x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ivtnd4 ivtnd8 ivtnd16 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.062 0.046 + 0.008*sl 0.050 + 0.007*sl 0.050 + 0.007*sl t f 0.066 0.053 + 0.006*sl 0.054 + 0.006*sl 0.057 + 0.006*sl t plh 0.202 0.191 + 0.005*sl 0.197 + 0.004*sl 0.214 + 0.003*sl t phl 0.226 0.216 + 0.005*sl 0.221 + 0.004*sl 0.238 + 0.003*sl en to y t r 0.070 0.053 + 0.008*sl 0.058 + 0.007*sl 0.053 + 0.007*sl t f 0.066 0.050 + 0.008*sl 0.057 + 0.006*sl 0.063 + 0.006*sl t plh 0.172 0.159 + 0.006*sl 0.168 + 0.004*sl 0.186 + 0.003*sl t phl 0.127 0.113 + 0.007*sl 0.123 + 0.004*sl 0.149 + 0.003*sl t plz 0.100 0.100 + 0.000*sl 0.100 + 0.000*sl 0.101 + 0.000*sl t phz 0.231 0.230 + 0.000*sl 0.231 + 0.000*sl 0.231 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.055 0.045 + 0.005*sl 0.051 + 0.003*sl 0.047 + 0.004*sl t f 0.061 0.056 + 0.003*sl 0.055 + 0.003*sl 0.050 + 0.003*sl t plh 0.221 0.215 + 0.003*sl 0.220 + 0.002*sl 0.243 + 0.002*sl t phl 0.240 0.235 + 0.003*sl 0.238 + 0.002*sl 0.259 + 0.002*sl en to y t r 0.062 0.054 + 0.004*sl 0.057 + 0.003*sl 0.047 + 0.004*sl t f 0.056 0.048 + 0.004*sl 0.053 + 0.003*sl 0.053 + 0.003*sl t plh 0.182 0.175 + 0.004*sl 0.181 + 0.002*sl 0.207 + 0.002*sl t phl 0.115 0.107 + 0.004*sl 0.114 + 0.002*sl 0.149 + 0.002*sl t plz 0.096 0.096 + 0.000*sl 0.096 + 0.000*sl 0.096 + 0.000*sl t phz 0.251 0.251 + 0.000*sl 0.251 + 0.000*sl 0.251 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 85, *group3 : 85 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.062 0.056 + 0.003*sl 0.060 + 0.002*sl 0.077 + 0.002*sl t f 0.089 0.086 + 0.001*sl 0.086 + 0.001*sl 0.080 + 0.001*sl t plh 0.252 0.248 + 0.002*sl 0.251 + 0.001*sl 0.282 + 0.001*sl t phl 0.279 0.275 + 0.002*sl 0.277 + 0.001*sl 0.296 + 0.001*sl en to y t r 0.073 0.067 + 0.003*sl 0.071 + 0.002*sl 0.080 + 0.002*sl t f 0.062 0.056 + 0.003*sl 0.061 + 0.002*sl 0.079 + 0.001*sl t plh 0.209 0.203 + 0.003*sl 0.208 + 0.001*sl 0.246 + 0.001*sl t phl 0.134 0.129 + 0.002*sl 0.133 + 0.001*sl 0.173 + 0.001*sl t plz 0.133 0.133 + 0.000*sl 0.133 + 0.000*sl 0.133 + 0.000*sl t phz 0.339 0.339 + 0.000*sl 0.340 + 0.000*sl 0.340 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 85, *group3 : 85 < sl
STD111 3-286 samsung asic nidh/nid/nid2/nid3/nid4/nid6/nid8/nid16 non-inverting buffer with 0.5x/1x/2x/3x/4x/6x/8x/16x drive logic symbol cell data input load (sl) nidh nid nid2 nid3 nid4 nid6 nid8 nid16 aaaaaaaa 0.3 0.6 0.7 0.8 1.0 1.5 1.9 3.7 gate count nidh nid nid2 nid3 nid4 nid6 nid8 nid16 1.00 1.00 1.33 1.67 2.00 2.67 3.33 6.00 ay truth table ay 00 11
samsung asic 3-287 STD111 nidh/nid/nid2/nid3/nid4/nid6/nid8/nid16 non-inverting buffer with 0.5x/1x/2x/3x/4x/6x/8x/16x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nidh nid nid2 nid3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.169 0.056 + 0.056*sl 0.046 + 0.059*sl 0.040 + 0.060*sl t f 0.166 0.057 + 0.055*sl 0.048 + 0.057*sl 0.039 + 0.058*sl t plh 0.168 0.115 + 0.027*sl 0.118 + 0.026*sl 0.118 + 0.026*sl t phl 0.195 0.132 + 0.032*sl 0.137 + 0.030*sl 0.138 + 0.030*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.104 0.053 + 0.026*sl 0.047 + 0.027*sl 0.039 + 0.028*sl t f 0.104 0.050 + 0.027*sl 0.045 + 0.028*sl 0.038 + 0.029*sl t plh 0.138 0.110 + 0.014*sl 0.115 + 0.012*sl 0.116 + 0.012*sl t phl 0.144 0.110 + 0.017*sl 0.116 + 0.015*sl 0.118 + 0.015*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.080 0.053 + 0.013*sl 0.053 + 0.013*sl 0.041 + 0.014*sl t f 0.077 0.049 + 0.014*sl 0.048 + 0.014*sl 0.038 + 0.015*sl t plh 0.145 0.128 + 0.008*sl 0.135 + 0.007*sl 0.141 + 0.006*sl t phl 0.141 0.121 + 0.010*sl 0.128 + 0.008*sl 0.134 + 0.008*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.079 0.062 + 0.009*sl 0.060 + 0.009*sl 0.047 + 0.009*sl t f 0.073 0.053 + 0.010*sl 0.055 + 0.010*sl 0.044 + 0.010*sl t plh 0.153 0.141 + 0.006*sl 0.147 + 0.005*sl 0.157 + 0.004*sl t phl 0.151 0.136 + 0.007*sl 0.143 + 0.006*sl 0.153 + 0.005*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-288 samsung asic nidh/nid/nid2/nid3/nid4/nid6/nid8/nid16 non-inverting buffer with 0.5x/1x/2x/3x/4x/6x/8x/16x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nid4 nid6 nid8 nid16 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.074 0.062 + 0.006*sl 0.059 + 0.007*sl 0.050 + 0.007*sl t f 0.066 0.051 + 0.008*sl 0.053 + 0.007*sl 0.046 + 0.007*sl t plh 0.152 0.142 + 0.005*sl 0.147 + 0.004*sl 0.160 + 0.003*sl t phl 0.147 0.136 + 0.006*sl 0.141 + 0.004*sl 0.154 + 0.004*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.067 0.057 + 0.005*sl 0.059 + 0.005*sl 0.037 + 0.005*sl t f 0.059 0.049 + 0.005*sl 0.051 + 0.005*sl 0.034 + 0.005*sl t plh 0.143 0.136 + 0.003*sl 0.140 + 0.002*sl 0.153 + 0.002*sl t phl 0.138 0.130 + 0.004*sl 0.134 + 0.003*sl 0.147 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 85, *group3 : 85 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.065 0.058 + 0.003*sl 0.058 + 0.003*sl 0.041 + 0.004*sl t f 0.057 0.048 + 0.004*sl 0.051 + 0.004*sl 0.038 + 0.004*sl t plh 0.141 0.136 + 0.003*sl 0.140 + 0.002*sl 0.154 + 0.002*sl t phl 0.137 0.131 + 0.003*sl 0.134 + 0.002*sl 0.149 + 0.002*sl *group1 : sl < 4, *group2 : 4 sl < < = = 85, *group3 : 85 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.063 0.058 + 0.003*sl 0.062 + 0.002*sl 0.052 + 0.002*sl t f 0.054 0.050 + 0.002*sl 0.050 + 0.002*sl 0.048 + 0.002*sl t plh 0.140 0.137 + 0.001*sl 0.138 + 0.001*sl 0.153 + 0.001*sl t phl 0.135 0.132 + 0.002*sl 0.133 + 0.001*sl 0.148 + 0.001*sl *group1 : sl < 4, *group2 : 4 sl < < = = 85, *group3 : 85 < sl
samsung asic 3-289 STD111 oak_nid10p/oak_nid20p clock buffer for 10pf/20pf drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oak_nid10p oak_nid20p input load (sl) gate count oak_nid10p oak_nid20p oak_nid10p oak_nid20p aa 17.18 31.64 1.0 1.9 ay path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.060 0.058 + 0.001*sl 0.047 + 0.001*sl 0.041 + 0.001*sl t f 0.049 0.047 + 0.001*sl 0.037 + 0.001*sl 0.033 + 0.001*sl t plh 0.346 0.345 + 0.000*sl 0.351 + 0.000*sl 0.351 + 0.000*sl t phl 0.262 0.261 + 0.001*sl 0.265 + 0.001*sl 0.265 + 0.001*sl *group1 : sl < 361, *group2 : 361 sl < < = = 541, *group3 : 541 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.058 0.057 + 0.000*sl 0.047 + 0.000*sl 0.041 + 0.001*sl t f 0.050 0.049 + 0.000*sl 0.040 + 0.000*sl 0.034 + 0.001*sl t plh 0.327 0.326 + 0.000*sl 0.335 + 0.000*sl 0.335 + 0.000*sl t phl 0.248 0.248 + 0.000*sl 0.256 + 0.000*sl 0.257 + 0.000*sl *group1 : sl < 451, *group2 : 451 sl < < = = 902, *group3 : 902 < sl truth table ay 00 11
STD111 3-290 samsung asic nit/nitd2/nitd4/nitd8/nitd16 non-inverting tri-state buffer with enable high, 1x/2x/4x/8x/16x drive logic symbol cell data input load (sl) output load (sl) nit nitd2 nitd4 nitd8 nitd16 nit nitd2 nitd4 nitd8 nitd16 aeaeaeaeae yyyyy 1.6 1.3 1.9 1.5 2.2 1.7 4.6 2.8 4.4 2.9 0.9 1.1 2.2 4.3 8.4 gate count nit nitd2 nitd4 nitd8 nitd16 2.33 2.67 3.33 5.33 7.33 ay e truth table aey x 0 hi-z 010 111
samsung asic 3-291 STD111 nit/nitd2/nitd4/nitd8/nitd16 non-inverting tri-state buffer with enable high, 1x/2x/4x/8x/16x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nit nitd2 nitd4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.106 0.052 + 0.027*sl 0.049 + 0.027*sl 0.044 + 0.028*sl t f 0.099 0.051 + 0.024*sl 0.055 + 0.023*sl 0.050 + 0.023*sl t plh 0.120 0.092 + 0.014*sl 0.098 + 0.013*sl 0.101 + 0.012*sl t phl 0.157 0.125 + 0.016*sl 0.134 + 0.013*sl 0.142 + 0.013*sl e to y t r 0.116 0.061 + 0.027*sl 0.055 + 0.029*sl 0.048 + 0.030*sl t f 0.104 0.055 + 0.025*sl 0.059 + 0.024*sl 0.054 + 0.024*sl t plh 0.119 0.089 + 0.015*sl 0.097 + 0.013*sl 0.101 + 0.012*sl t phl 0.190 0.156 + 0.017*sl 0.168 + 0.014*sl 0.177 + 0.013*sl t plz 0.140 0.140 + 0.000*sl 0.140 + 0.000*sl 0.140 + 0.000*sl t phz 0.142 0.142 + 0.000*sl 0.143 + 0.000*sl 0.143 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.074 0.045 + 0.014*sl 0.048 + 0.014*sl 0.042 + 0.014*sl t f 0.076 0.053 + 0.011*sl 0.051 + 0.012*sl 0.050 + 0.012*sl t plh 0.111 0.093 + 0.009*sl 0.101 + 0.007*sl 0.110 + 0.006*sl t phl 0.144 0.126 + 0.009*sl 0.132 + 0.007*sl 0.146 + 0.006*sl e to y t r 0.082 0.055 + 0.014*sl 0.055 + 0.014*sl 0.045 + 0.014*sl t f 0.075 0.047 + 0.014*sl 0.054 + 0.012*sl 0.053 + 0.012*sl t plh 0.109 0.090 + 0.009*sl 0.100 + 0.007*sl 0.110 + 0.006*sl t phl 0.182 0.160 + 0.011*sl 0.172 + 0.008*sl 0.189 + 0.007*sl t plz 0.150 0.150 + 0.000*sl 0.150 + 0.000*sl 0.149 + 0.000*sl t phz 0.153 0.153 + 0.000*sl 0.153 + 0.000*sl 0.153 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.065 0.048 + 0.008*sl 0.054 + 0.007*sl 0.051 + 0.007*sl t f 0.070 0.058 + 0.006*sl 0.059 + 0.006*sl 0.057 + 0.006*sl t plh 0.118 0.107 + 0.005*sl 0.114 + 0.004*sl 0.130 + 0.003*sl t phl 0.151 0.141 + 0.005*sl 0.145 + 0.004*sl 0.161 + 0.003*sl e to y t r 0.074 0.059 + 0.008*sl 0.063 + 0.007*sl 0.054 + 0.007*sl t f 0.065 0.048 + 0.008*sl 0.056 + 0.006*sl 0.062 + 0.006*sl t plh 0.116 0.103 + 0.006*sl 0.113 + 0.004*sl 0.132 + 0.003*sl t phl 0.180 0.166 + 0.007*sl 0.176 + 0.004*sl 0.202 + 0.003*sl t plz 0.171 0.171 + 0.000*sl 0.171 + 0.000*sl 0.171 + 0.000*sl t phz 0.188 0.187 + 0.000*sl 0.188 + 0.000*sl 0.188 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-292 samsung asic nit/nitd2/nitd4/nitd8/nitd16 non-inverting tri-state buffer with enable high, 1x/2x/4x/8x/16x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nitd8 nitd16 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.056 0.047 + 0.004*sl 0.050 + 0.003*sl 0.045 + 0.004*sl t f 0.065 0.060 + 0.002*sl 0.058 + 0.003*sl 0.049 + 0.003*sl t plh 0.108 0.102 + 0.003*sl 0.106 + 0.002*sl 0.127 + 0.002*sl t phl 0.137 0.132 + 0.003*sl 0.135 + 0.002*sl 0.155 + 0.002*sl e to y t r 0.065 0.057 + 0.004*sl 0.060 + 0.003*sl 0.047 + 0.004*sl t f 0.054 0.046 + 0.004*sl 0.050 + 0.003*sl 0.052 + 0.003*sl t plh 0.107 0.100 + 0.004*sl 0.106 + 0.002*sl 0.132 + 0.002*sl t phl 0.184 0.177 + 0.004*sl 0.183 + 0.002*sl 0.217 + 0.002*sl t plz 0.180 0.180 + 0.000*sl 0.180 + 0.000*sl 0.180 + 0.000*sl t phz 0.181 0.181 + 0.000*sl 0.182 + 0.000*sl 0.182 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 85, *group3 : 85 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.063 0.061 + 0.001*sl 0.057 + 0.002*sl 0.075 + 0.002*sl t f 0.086 0.083 + 0.001*sl 0.083 + 0.001*sl 0.079 + 0.001*sl t plh 0.138 0.134 + 0.002*sl 0.137 + 0.001*sl 0.166 + 0.001*sl t phl 0.175 0.172 + 0.002*sl 0.174 + 0.001*sl 0.192 + 0.001*sl e to y t r 0.073 0.067 + 0.003*sl 0.071 + 0.002*sl 0.079 + 0.002*sl t f 0.060 0.054 + 0.003*sl 0.059 + 0.002*sl 0.078 + 0.001*sl t plh 0.135 0.130 + 0.002*sl 0.134 + 0.001*sl 0.172 + 0.001*sl t phl 0.202 0.198 + 0.002*sl 0.202 + 0.001*sl 0.241 + 0.001*sl t plz 0.215 0.215 + 0.000*sl 0.215 + 0.000*sl 0.215 + 0.000*sl t phz 0.269 0.268 + 0.000*sl 0.269 + 0.000*sl 0.270 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 85, *group3 : 85 < sl
samsung asic 3-293 STD111 nitn/nitnd2/nitnd4/nitnd8/nitnd16 non-inverting tri-state buffer with enable low, 1x/2x/4x/8x/16x drive logic symbol cell data input load (sl) output load (sl) nitn nitnd2 nitnd4 nitnd8 nitnd16 nitn nitnd2 nitnd4 nitnd 8 nitnd 16 aenaenaenaenaenyyyy y 1.6 1.4 1.9 1.6 2.2 1.9 4.6 3.0 4.4 3.0 0.9 1.1 2.2 4.3 8.4 gate count nitn nitnd2 nitnd4 nitnd8 nitnd16 2.33 2.67 3.33 5.33 7.33 ay en truth table aeny x 1 hi-z 000 101
STD111 3-294 samsung asic nitn/nitnd2/nitnd4/nitnd8/nitnd16 non-inverting tri-state buffer with enable low, 1x/2x/4x/8x/16x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nitn nitnd2 nitnd4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.106 0.053 + 0.026*sl 0.049 + 0.027*sl 0.044 + 0.028*sl t f 0.099 0.052 + 0.023*sl 0.054 + 0.023*sl 0.049 + 0.023*sl t plh 0.121 0.092 + 0.014*sl 0.099 + 0.013*sl 0.102 + 0.012*sl t phl 0.156 0.124 + 0.016*sl 0.133 + 0.013*sl 0.141 + 0.012*sl en to y t r 0.111 0.054 + 0.029*sl 0.053 + 0.029*sl 0.046 + 0.030*sl t f 0.106 0.058 + 0.024*sl 0.059 + 0.024*sl 0.054 + 0.024*sl t plh 0.173 0.144 + 0.015*sl 0.151 + 0.013*sl 0.154 + 0.012*sl t phl 0.146 0.112 + 0.017*sl 0.124 + 0.014*sl 0.134 + 0.013*sl t plz 0.079 0.079 + 0.000*sl 0.079 + 0.000*sl 0.079 + 0.000*sl t phz 0.178 0.178 + 0.000*sl 0.178 + 0.000*sl 0.178 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.075 0.048 + 0.014*sl 0.048 + 0.014*sl 0.041 + 0.014*sl t f 0.076 0.053 + 0.011*sl 0.051 + 0.012*sl 0.049 + 0.012*sl t plh 0.111 0.094 + 0.009*sl 0.101 + 0.007*sl 0.111 + 0.006*sl t phl 0.143 0.125 + 0.009*sl 0.132 + 0.007*sl 0.145 + 0.006*sl en to y t r 0.084 0.059 + 0.012*sl 0.053 + 0.014*sl 0.044 + 0.014*sl t f 0.077 0.049 + 0.014*sl 0.057 + 0.012*sl 0.054 + 0.012*sl t plh 0.165 0.146 + 0.009*sl 0.156 + 0.007*sl 0.166 + 0.006*sl t phl 0.130 0.109 + 0.011*sl 0.121 + 0.008*sl 0.138 + 0.007*sl t plz 0.085 0.085 + 0.000*sl 0.085 + 0.000*sl 0.085 + 0.000*sl t phz 0.202 0.202 + 0.000*sl 0.202 + 0.000*sl 0.202 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.064 0.047 + 0.009*sl 0.053 + 0.007*sl 0.052 + 0.007*sl t f 0.071 0.059 + 0.006*sl 0.059 + 0.006*sl 0.057 + 0.006*sl t plh 0.119 0.108 + 0.006*sl 0.114 + 0.004*sl 0.131 + 0.003*sl t phl 0.149 0.138 + 0.005*sl 0.144 + 0.004*sl 0.159 + 0.003*sl en to y t r 0.070 0.054 + 0.008*sl 0.058 + 0.007*sl 0.054 + 0.007*sl t f 0.066 0.050 + 0.008*sl 0.057 + 0.006*sl 0.063 + 0.006*sl t plh 0.175 0.162 + 0.006*sl 0.171 + 0.004*sl 0.189 + 0.003*sl t phl 0.127 0.113 + 0.007*sl 0.123 + 0.004*sl 0.149 + 0.003*sl t plz 0.100 0.100 + 0.000*sl 0.100 + 0.000*sl 0.101 + 0.000*sl t phz 0.235 0.234 + 0.000*sl 0.235 + 0.000*sl 0.235 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-295 STD111 nitn/nitnd2/nitnd4/nitnd8/nitnd16 non-inverting tri-state buffer with enable low, 1x/2x/4x/8x/16x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) nitnd8 nitnd16 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.056 0.047 + 0.004*sl 0.051 + 0.003*sl 0.046 + 0.004*sl t f 0.063 0.056 + 0.003*sl 0.057 + 0.003*sl 0.049 + 0.003*sl t plh 0.109 0.103 + 0.003*sl 0.107 + 0.002*sl 0.129 + 0.002*sl t phl 0.136 0.131 + 0.003*sl 0.134 + 0.002*sl 0.153 + 0.002*sl en to y t r 0.062 0.054 + 0.004*sl 0.057 + 0.003*sl 0.047 + 0.004*sl t f 0.056 0.047 + 0.004*sl 0.052 + 0.003*sl 0.052 + 0.003*sl t plh 0.182 0.175 + 0.004*sl 0.181 + 0.002*sl 0.206 + 0.002*sl t phl 0.114 0.107 + 0.004*sl 0.114 + 0.002*sl 0.148 + 0.002*sl t plz 0.096 0.096 + 0.000*sl 0.096 + 0.000*sl 0.096 + 0.000*sl t phz 0.251 0.250 + 0.000*sl 0.251 + 0.000*sl 0.251 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 85, *group3 : 85 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.064 0.061 + 0.002*sl 0.060 + 0.002*sl 0.076 + 0.002*sl t f 0.087 0.083 + 0.002*sl 0.084 + 0.001*sl 0.079 + 0.001*sl t plh 0.139 0.135 + 0.002*sl 0.138 + 0.001*sl 0.169 + 0.001*sl t phl 0.173 0.170 + 0.002*sl 0.172 + 0.001*sl 0.190 + 0.001*sl en to y t r 0.073 0.068 + 0.003*sl 0.071 + 0.002*sl 0.080 + 0.002*sl t f 0.062 0.057 + 0.002*sl 0.060 + 0.002*sl 0.079 + 0.001*sl t plh 0.210 0.205 + 0.003*sl 0.209 + 0.001*sl 0.247 + 0.001*sl t phl 0.133 0.128 + 0.002*sl 0.132 + 0.001*sl 0.172 + 0.001*sl t plz 0.132 0.132 + 0.000*sl 0.132 + 0.000*sl 0.132 + 0.000*sl t phz 0.341 0.341 + 0.000*sl 0.341 + 0.000*sl 0.342 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 85, *group3 : 85 < sl
STD111 3-296 samsung asic oak_duclk10/oak_duclk16 2 phase clock generator buffer (1ns/1.6ns non-overlapped) logic symbol cell data input load (sl) gate count oak_duclk10 oak_duclk16 oak_duclk10 oak_duclk16 aa 10.67 11.67 2.0 2.0 ckb ck a truth table a ck ckb 001 110
samsung asic 3-297 STD111 oak_duclk10/oak_duclk16 2 phase clock generator buffer (1ns/1.6ns non-overlapped) switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) oak_duclk10 oak_duclk16 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to ck t r 0.083 0.071 + 0.006*sl 0.070 + 0.006*sl 0.056 + 0.006*sl t f 0.080 0.068 + 0.006*sl 0.067 + 0.006*sl 0.061 + 0.006*sl t plh 2.214 2.204 + 0.005*sl 2.210 + 0.003*sl 2.221 + 0.003*sl t phl 1.235 1.224 + 0.005*sl 1.230 + 0.004*sl 1.244 + 0.003*sl a to ckb t r 0.082 0.069 + 0.006*sl 0.071 + 0.006*sl 0.057 + 0.006*sl t f 0.081 0.068 + 0.006*sl 0.069 + 0.006*sl 0.061 + 0.006*sl t plh 2.274 2.265 + 0.005*sl 2.270 + 0.003*sl 2.281 + 0.003*sl t phl 1.165 1.155 + 0.005*sl 1.160 + 0.004*sl 1.174 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to ck t r 0.090 0.079 + 0.006*sl 0.078 + 0.006*sl 0.064 + 0.006*sl t f 0.092 0.081 + 0.006*sl 0.080 + 0.006*sl 0.071 + 0.006*sl t plh 3.167 3.157 + 0.005*sl 3.162 + 0.003*sl 3.176 + 0.003*sl t phl 1.694 1.682 + 0.006*sl 1.688 + 0.004*sl 1.704 + 0.003*sl a to ckb t r 0.090 0.079 + 0.006*sl 0.078 + 0.006*sl 0.063 + 0.006*sl t f 0.092 0.080 + 0.006*sl 0.080 + 0.006*sl 0.070 + 0.006*sl t plh 3.229 3.219 + 0.005*sl 3.225 + 0.003*sl 3.238 + 0.003*sl t phl 1.619 1.608 + 0.006*sl 1.613 + 0.004*sl 1.629 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-298 samsung asic ctsb/ctsbd2/ctsbd3/ctsbd4/ctsbd6/ctsbd8/ctsbd16 clock tree synthesis buffers logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ctsb ctsbd2 ctsbd3 input load (sl) ctsb ctsbd2 ctsbd3 ctsbd4 ctsbd6 ctsbd8 ctsbd16 aaaaaaa 0.6 0.7 0.8 1.0 1.5 1.9 3.7 gate count ctsb ctsbd2 ctsbd3 ctsbd4 ctsbd6 ctsbd8 ctsbd16 1.00 1.33 1.67 2.00 2.67 3.33 6.00 ay path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.104 0.053 + 0.026*sl 0.047 + 0.027*sl 0.039 + 0.028*sl t f 0.104 0.050 + 0.027*sl 0.045 + 0.028*sl 0.038 + 0.029*sl t plh 0.138 0.110 + 0.014*sl 0.115 + 0.012*sl 0.116 + 0.012*sl t phl 0.144 0.110 + 0.017*sl 0.116 + 0.015*sl 0.118 + 0.015*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.080 0.053 + 0.013*sl 0.053 + 0.013*sl 0.041 + 0.014*sl t f 0.077 0.049 + 0.014*sl 0.048 + 0.014*sl 0.038 + 0.015*sl t plh 0.145 0.128 + 0.008*sl 0.135 + 0.007*sl 0.141 + 0.006*sl t phl 0.141 0.121 + 0.010*sl 0.128 + 0.008*sl 0.134 + 0.008*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.079 0.062 + 0.009*sl 0.060 + 0.009*sl 0.047 + 0.009*sl t f 0.073 0.053 + 0.010*sl 0.055 + 0.010*sl 0.044 + 0.010*sl t plh 0.153 0.141 + 0.006*sl 0.147 + 0.005*sl 0.157 + 0.004*sl t phl 0.151 0.136 + 0.007*sl 0.143 + 0.006*sl 0.153 + 0.005*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl truth table ay 00 11
samsung asic 3-299 STD111 ctsb/ctsbd2/ctsbd3/ctsbd4/ctsbd6/ctsbd8/ctsbd16 clock tree synthesis buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ctsbd4 ctsbd6 ctsbd8 ctsbd16 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.074 0.062 + 0.006*sl 0.059 + 0.007*sl 0.050 + 0.007*sl t f 0.066 0.051 + 0.008*sl 0.053 + 0.007*sl 0.046 + 0.007*sl t plh 0.152 0.142 + 0.005*sl 0.147 + 0.004*sl 0.160 + 0.003*sl t phl 0.147 0.136 + 0.006*sl 0.141 + 0.004*sl 0.154 + 0.004*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.067 0.057 + 0.005*sl 0.059 + 0.005*sl 0.037 + 0.005*sl t f 0.059 0.049 + 0.005*sl 0.051 + 0.005*sl 0.034 + 0.005*sl t plh 0.143 0.136 + 0.003*sl 0.140 + 0.002*sl 0.153 + 0.002*sl t phl 0.138 0.130 + 0.004*sl 0.134 + 0.003*sl 0.147 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 85, *group3 : 85 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.065 0.058 + 0.003*sl 0.058 + 0.003*sl 0.041 + 0.004*sl t f 0.057 0.048 + 0.004*sl 0.051 + 0.004*sl 0.038 + 0.004*sl t plh 0.141 0.136 + 0.003*sl 0.140 + 0.002*sl 0.154 + 0.002*sl t phl 0.137 0.131 + 0.003*sl 0.134 + 0.002*sl 0.149 + 0.002*sl *group1 : sl < 4, *group2 : 4 sl < < = = 85, *group3 : 85 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.063 0.058 + 0.003*sl 0.062 + 0.002*sl 0.052 + 0.002*sl t f 0.054 0.050 + 0.002*sl 0.050 + 0.002*sl 0.048 + 0.002*sl t plh 0.140 0.137 + 0.001*sl 0.138 + 0.001*sl 0.153 + 0.001*sl t phl 0.135 0.132 + 0.002*sl 0.133 + 0.001*sl 0.148 + 0.001*sl *group1 : sl < 4, *group2 : 4 sl < < = = 85, *group3 : 85 < sl
STD111 3-300 samsung asic flip-flops cell list cell name function description fd1 d flip-flop fd1d2 d flip-flop with 2x drive fd1cs d flip-flop with scan clock fd1csd2 d flip-flop with scan clock, 2x drive fd1s d flip-flop with scan fd1sd2 d flip-flop with scan, 2x drive fd1sq d flip-flop with scan, q output only fd1sqd2 d flip-flop with scan, q output only, 2x drive fd1q d flip-flop with q output only fd1qd2 d flip-flop with q output only, 2x drive fd2 d flip-flop with reset fd2d2 d flip-flop with reset, 2x drive fd2cs d flip-flop with reset, scan clock fd2csd2 d flip-flop with reset, scan clock, 2x drive fd2s d flip-flop with reset, scan fd2sd2 d flip-flop with reset, scan, 2x drive fd2sq d flip-flop with reset, scan, q output only fd2sqd2 d flip-flop with reset, scan, q output only, 2x drive fd2q d flip-flop with reset, q output only fd2qd2 d flip-flop with reset, q output only, 2x drive fd3 d flip-flop with set fd3d2 d flip-flop with set, 2x drive fd3cs d flip-flop with set, scan clock fd3csd2 d flip-flop with set, scan clock, 2x drive fd3s d flip-flop with set, scan fd3sd2 d flip-flop with set, scan, 2x drive fd3sq d flip-flop with set, scan, q output only fd3sqd2 d flip-flop with set, scan, q output only, 2x drive fd3q d flip-flop with set, q output only fd3qd2 d flip-flop with set, q output only, 2x drive fd4 d flip-flop with reset, set fd4d2 d flip-flop with reset, set, 2x drive fd4cs d flip-flop with reset, set, scan clock fd4csd2 d flip-flop with reset, set, scan clock, 2x drive fd4s d flip-flop with reset, set, scan fd4sd2 d flip-flop with reset, set, scan, 2x drive fd4sq d flip-flop with reset, set, scan, q output only fd4sqd2 d flip-flop with reset, set, scan, q output only, 2x drive
samsung asic 3-301 STD111 flip-flops cell list (cont.) fd4q d flip-flop with reset, set, q output only fd4qd2 d flip-flop with reset, set, q output only, 2x drive fd5 d flip-flop with negative edge trigger fd5d2 d flip-flop with negative edge trigger, 2x drive fd5s d flip-flop with negative edge trigger, scan fd5sd2 d flip-flop with negative edge trigger, scan, 2x drive fd6 d flip-flop with negative edge trigger, reset fd6d2 d flip-flop with negative edge trigger, reset, 2x drive fd6s d flip-flop with negative edge trigger, reset, scan fd6sd2 d flip-flop with negative edge trigger, reset, scan, 2x drive fd7 d flip-flop with negative edge trigger, set fd7d2 d flip-flop with negative edge trigger, set, 2x drive fd7s d flip-flop with negative edge trigger, set, scan fd7sd2 d flip-flop with negative edge trigger, set, scan, 2x drive fd8 d flip-flop with negative edge trigger, reset, set fd8d2 d flip-flop with negative edge trigger, reset, set, 2x drive fd8s d flip-flop with negative edge trigger, reset, set, scan fd8sd2 d flip-flop with negative edge trigger, reset, set, scan, 2x drive fds2 d flip-flop with synchronous clear fds2d2 d flip-flop with synchronous clear, 2x drive fds2cs d flip-flop with synchronous clear, scan clock fds2csd2 d flip-flop with synchronous clear, scan clock, 2x drive fds2s d flip-flop with synchronous clear, scan fds2sd2 d flip-flop with synchronous clear, scan, 2x drive fds3 d flip-flop with synchronous set fds3d2 d flip-flop with synchronous set, 2x drive fds3cs d flip-flop with synchronous set, scan clock fds3csd2 d flip-flop with synchronous set, scan clock, 2x drive fds3s flip-flop with synchronous set, scan fds3sd2 flip-flop with synchronous set, scan, 2x drive fj1 jk flip-flop fj1d2 jk flip-flop with 2x drive fj1s jk flip-flop with scan fj1sd2 jk flip-flop with scan, 2x drive fj2 jk flip-flop with reset fj2d2 jk flip-flop with reset, 2x drive fj2s jk flip-flop with reset, scan fj2sd2 jk flip-flop with reset, scan, 2x drive cell name function description
STD111 3-302 samsung asic flip-flops cell list (cont.) fj4 jk flip-flop with reset, set fj4d2 jk flip-flop with reset, set, 2x drive fj4s jk flip-flop with reset, set, scan fj4sd2 jk flip-flop with reset, set, scan, 2x drive ft2 toggle flip-flop with reset ft2d2 toggle flip-flop with reset, 2x drive cell name function description
samsung asic 3-303 STD111 fd1/fd1d2 d flip-flop with 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd1 fd1d2 fd1 fd1d2 dckdck 0.6 0.7 0.7 0.7 5.00 5.00 parameter symbol value (ns) fd1 fd1d2 input setup time (d to ck) t su 0.180 0.177 input hold time (d to ck) t hd 0.117 0.116 pulse width low (ck) t pwl 0.252 0.255 pulse width high (ck) t pwh 0.244 0.265 d ck q qn cl clb q clb cl qn d ck cl clb clb cl cl clb truth table d ck q (n+1) qn (n+1) 001 110 x q (n) qn (n)
STD111 3-304 samsung asic fd1/fd1d2 d flip-flop with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd1 fd1d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.109 0.056 + 0.027*sl 0.052 + 0.028*sl 0.045 + 0.028*sl t f 0.096 0.050 + 0.023*sl 0.049 + 0.024*sl 0.043 + 0.024*sl t plh 0.304 0.276 + 0.014*sl 0.281 + 0.013*sl 0.285 + 0.012*sl t phl 0.303 0.272 + 0.016*sl 0.279 + 0.013*sl 0.286 + 0.013*sl ck to qn t r 0.100 0.046 + 0.027*sl 0.042 + 0.028*sl 0.037 + 0.029*sl t f 0.089 0.044 + 0.023*sl 0.039 + 0.024*sl 0.035 + 0.024*sl t plh 0.354 0.327 + 0.013*sl 0.331 + 0.012*sl 0.331 + 0.012*sl t phl 0.361 0.332 + 0.015*sl 0.338 + 0.013*sl 0.340 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.084 0.056 + 0.014*sl 0.058 + 0.013*sl 0.047 + 0.014*sl t f 0.075 0.052 + 0.012*sl 0.051 + 0.012*sl 0.049 + 0.012*sl t plh 0.318 0.301 + 0.009*sl 0.308 + 0.007*sl 0.316 + 0.006*sl t phl 0.307 0.289 + 0.009*sl 0.296 + 0.007*sl 0.309 + 0.006*sl ck to qn t r 0.078 0.051 + 0.013*sl 0.050 + 0.013*sl 0.039 + 0.014*sl t f 0.070 0.045 + 0.013*sl 0.049 + 0.012*sl 0.040 + 0.012*sl t plh 0.394 0.377 + 0.008*sl 0.383 + 0.007*sl 0.389 + 0.006*sl t phl 0.402 0.385 + 0.009*sl 0.392 + 0.007*sl 0.401 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-305 STD111 fd1cs/fd1csd2 d flip-flop with scan clock, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd1cs fd1csd2 fd1cs fd1csd2 d si ck sck d si ck sck 0.6 0.6 0.7 1.5 0.7 0.7 0.7 1.5 7.33 7.67 parameter symbol value (ns) fd1cs fd1csd2 input setup time (d to ck) t su 0.180 0.178 input hold time (d to ck) t hd 0.118 0.117 input setup time (si to sck) t su 0.291 0.291 input hold time (si to sck) t hd 0.056 0.056 pulse width low (ck) t pwl 0.252 0.253 pulse width high (ck) t pwh 0.250 0.266 pulse width low (sck) t pwl 0.219 0.219 pulse width high (sck) t pwh 0.307 0.334 q qn si sck d ck cl clb q cl clb clb cl clb cl cl clb qn sck sckb sck sckb sckb sck sck sck sckb d si ck sck sckb truth table si sck d ck q (n+1) qn (n+1) x00 01 x01 10 0 x001 1 x010 x 0 x q(n) qn(n) x x 0 q(n) qn(n)
STD111 3-306 samsung asic fd1cs/fd1csd2 d flip-flop with scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd1cs fd1csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.109 0.056 + 0.026*sl 0.053 + 0.027*sl 0.045 + 0.028*sl t f 0.099 0.052 + 0.023*sl 0.052 + 0.023*sl 0.045 + 0.024*sl t plh 0.309 0.281 + 0.014*sl 0.287 + 0.013*sl 0.290 + 0.012*sl t phl 0.309 0.278 + 0.016*sl 0.286 + 0.013*sl 0.292 + 0.013*sl sck to q t r 0.127 0.077 + 0.025*sl 0.072 + 0.026*sl 0.061 + 0.028*sl t f 0.104 0.058 + 0.023*sl 0.057 + 0.023*sl 0.051 + 0.024*sl t plh 0.396 0.366 + 0.015*sl 0.375 + 0.013*sl 0.380 + 0.012*sl t phl 0.324 0.293 + 0.016*sl 0.301 + 0.014*sl 0.309 + 0.013*sl ck to qn t r 0.110 0.054 + 0.028*sl 0.055 + 0.028*sl 0.051 + 0.028*sl t f 0.097 0.049 + 0.024*sl 0.050 + 0.024*sl 0.047 + 0.024*sl t plh 0.372 0.343 + 0.015*sl 0.349 + 0.013*sl 0.356 + 0.012*sl t phl 0.382 0.351 + 0.016*sl 0.358 + 0.014*sl 0.364 + 0.013*sl sck to qn t r 0.101 0.049 + 0.026*sl 0.043 + 0.028*sl 0.038 + 0.028*sl t f 0.093 0.047 + 0.023*sl 0.043 + 0.024*sl 0.037 + 0.024*sl t plh 0.376 0.349 + 0.013*sl 0.353 + 0.012*sl 0.354 + 0.012*sl t phl 0.455 0.426 + 0.015*sl 0.432 + 0.013*sl 0.435 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.084 0.058 + 0.013*sl 0.056 + 0.013*sl 0.047 + 0.014*sl t f 0.076 0.051 + 0.012*sl 0.054 + 0.012*sl 0.050 + 0.012*sl t plh 0.316 0.299 + 0.009*sl 0.305 + 0.007*sl 0.313 + 0.006*sl t phl 0.311 0.292 + 0.009*sl 0.300 + 0.007*sl 0.313 + 0.007*sl sck to q t r 0.103 0.077 + 0.013*sl 0.078 + 0.013*sl 0.063 + 0.014*sl t f 0.082 0.059 + 0.012*sl 0.059 + 0.012*sl 0.057 + 0.012*sl t plh 0.406 0.388 + 0.009*sl 0.397 + 0.007*sl 0.408 + 0.006*sl t phl 0.327 0.307 + 0.010*sl 0.316 + 0.007*sl 0.330 + 0.006*sl ck to qn t r 0.085 0.056 + 0.014*sl 0.058 + 0.014*sl 0.053 + 0.014*sl t f 0.077 0.052 + 0.013*sl 0.054 + 0.012*sl 0.051 + 0.012*sl t plh 0.410 0.393 + 0.009*sl 0.399 + 0.007*sl 0.411 + 0.006*sl t phl 0.417 0.398 + 0.009*sl 0.406 + 0.007*sl 0.418 + 0.007*sl sck to qn t r 0.078 0.052 + 0.013*sl 0.051 + 0.013*sl 0.039 + 0.014*sl t f 0.072 0.047 + 0.013*sl 0.052 + 0.011*sl 0.042 + 0.012*sl t plh 0.415 0.399 + 0.008*sl 0.405 + 0.007*sl 0.410 + 0.006*sl t phl 0.498 0.480 + 0.009*sl 0.487 + 0.007*sl 0.496 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-307 STD111 fd1s/fd1sd2 d flip-flop with scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd1s fd1sd2 fd1s fd1sd2 d ck ti te d ck ti te 0.6 0.7 0.6 1.4 0.6 0.7 0.6 1.4 6.33 6.67 parameter symbol value (ns) fd1s fd1sd2 input setup time (d to ck) t su 0.268 0.269 input hold time (d to ck) t hd 0.063 0.062 input setup time (ti to ck) t su 0.314 0.315 input hold time (ti to ck) t hd 0.034 0.033 input setup time (te to ck) t su 0.312 0.314 input hold time (te to ck) t hd 0.029 0.029 pulse width low (ck) t pwl 0.330 0.333 pulse width high (ck) t pwh 0.245 0.262 q qn d ti te ck cl clb q clb cl qn d ck cl clb te ti te teb te clb cl cl clb teb truth table dtiteck q (n+1) qn (n+1) 0x0 01 1x0 10 x01 01 x11 10 x x x q(n) qn(n)
STD111 3-308 samsung asic fd1s/fd1sd2 d flip-flop with scan, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd1s fd1sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.109 0.056 + 0.027*sl 0.052 + 0.028*sl 0.045 + 0.028*sl t f 0.097 0.048 + 0.024*sl 0.052 + 0.023*sl 0.045 + 0.024*sl t plh 0.306 0.278 + 0.014*sl 0.283 + 0.013*sl 0.286 + 0.012*sl t phl 0.309 0.278 + 0.015*sl 0.286 + 0.013*sl 0.292 + 0.013*sl ck to qn t r 0.101 0.048 + 0.027*sl 0.043 + 0.028*sl 0.038 + 0.029*sl t f 0.091 0.045 + 0.023*sl 0.042 + 0.024*sl 0.036 + 0.024*sl t plh 0.360 0.333 + 0.014*sl 0.337 + 0.012*sl 0.338 + 0.012*sl t phl 0.364 0.334 + 0.015*sl 0.341 + 0.013*sl 0.343 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.083 0.056 + 0.013*sl 0.056 + 0.013*sl 0.046 + 0.014*sl t f 0.075 0.049 + 0.013*sl 0.053 + 0.012*sl 0.050 + 0.012*sl t plh 0.315 0.298 + 0.009*sl 0.304 + 0.007*sl 0.312 + 0.006*sl t phl 0.312 0.293 + 0.009*sl 0.301 + 0.007*sl 0.314 + 0.006*sl ck to qn t r 0.077 0.051 + 0.013*sl 0.050 + 0.014*sl 0.039 + 0.014*sl t f 0.070 0.046 + 0.012*sl 0.047 + 0.012*sl 0.041 + 0.012*sl t plh 0.398 0.382 + 0.008*sl 0.387 + 0.007*sl 0.392 + 0.006*sl t phl 0.400 0.382 + 0.009*sl 0.389 + 0.007*sl 0.399 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-309 STD111 fd1sq/fd1sqd2 d flip-flop with scan, q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd1sq fd1sqd2 fd1sq fd1sqd2 d ck ti te d ck ti te 0.6 0.7 0.6 1.4 0.6 0.7 0.6 1.4 5.67 6.00 parameter symbol value (ns) fd1sq fd1sqd2 input setup time (d to ck) t su 0.268 0.268 input hold time (d to ck) t hd 0.062 0.063 input setup time (ti to ck) t su 0.310 0.314 input hold time (ti to ck) t hd 0.035 0.035 input setup time (te to ck) t su 0.310 0.312 input hold time (te to ck) t hd 0.030 0.030 pulse width low (ck) t pwl 0.332 0.329 pulse width high (ck) t pwh 0.237 0.243 q d ti te ck cl clb q clb cl clb cl cl clb ck cl clb te teb te d te ti teb truth table dtiteck q (n+1) 0x0 0 1x0 1 x01 0 x11 1 x x x q(n)
STD111 3-310 samsung asic fd1sq/fd1sqd2 d flip-flop with scan, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd1sq fd1sqd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.104 0.050 + 0.027*sl 0.046 + 0.028*sl 0.040 + 0.028*sl t f 0.091 0.043 + 0.024*sl 0.044 + 0.024*sl 0.037 + 0.024*sl t plh 0.292 0.265 + 0.014*sl 0.269 + 0.013*sl 0.271 + 0.012*sl t phl 0.295 0.265 + 0.015*sl 0.272 + 0.013*sl 0.275 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.079 0.052 + 0.013*sl 0.051 + 0.013*sl 0.040 + 0.014*sl t f 0.069 0.045 + 0.012*sl 0.048 + 0.012*sl 0.041 + 0.012*sl t plh 0.296 0.279 + 0.008*sl 0.285 + 0.007*sl 0.291 + 0.006*sl t phl 0.294 0.277 + 0.009*sl 0.284 + 0.007*sl 0.293 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-311 STD111 fd1q/fd1qd2 d flip-flop with q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd1q fd1qd2 fd1q fd1qd2 dckdck 0.7 0.7 0.7 0.7 4.33 4.33 parameter symbol value (ns) fd1q fd1qd2 input setup time (d to ck) t su 0.177 0.178 input hold time (d to ck) t hd 0.113 0.114 pulse width low (ck) t pwl 0.253 0.251 pulse width high (ck) t pwh 0.234 0.243 d ck q cl clb q clb cl cl clb d ck cl clb cl clb truth table d ck q (n+1) 00 11 x q (n)
STD111 3-312 samsung asic fd1q/fd1qd2 d flip-flop with q output only, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd1q fd1qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.103 0.050 + 0.026*sl 0.044 + 0.028*sl 0.038 + 0.029*sl t f 0.089 0.043 + 0.023*sl 0.042 + 0.023*sl 0.036 + 0.024*sl t plh 0.286 0.259 + 0.014*sl 0.263 + 0.013*sl 0.265 + 0.012*sl t phl 0.287 0.258 + 0.015*sl 0.264 + 0.013*sl 0.267 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.077 0.050 + 0.014*sl 0.050 + 0.014*sl 0.039 + 0.014*sl t f 0.068 0.043 + 0.012*sl 0.046 + 0.012*sl 0.041 + 0.012*sl t plh 0.294 0.278 + 0.008*sl 0.284 + 0.007*sl 0.290 + 0.006*sl t phl 0.291 0.273 + 0.009*sl 0.280 + 0.007*sl 0.290 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-313 STD111 fd2/fd2d2 d flip-flop with reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd2 fd2d2 fd2 fd2d2 d ck rn d ck rn 0.6 0.7 1.3 0.7 0.7 1.4 5.33 5.67 parameter symbol value (ns) fd2 fd2d2 input setup time (d to ck) t su 0.185 0.183 input hold time (d to ck) t hd 0.128 0.132 pulse width low (ck) t pwl 0.259 0.371 pulse width high (ck) t pwh 0.251 0.269 pulse width low (rn) t pwl 0.250 0.289 recovery time (rn to ck) t rc 0.000 0.000 removal time (rn to ck) t rm 0.526 0.522 d ck q qn rn cl clb q clb cl clb cl cl clb d ck cl clb rn qn rn rn rn truth table d ck rn q (n+1) qn (n+1) 0 101 1 110 xx001 x 1 q (n) qn (n)
STD111 3-314 samsung asic fd2/fd2d2 d flip-flop with reset, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd2 fd2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.116 0.060 + 0.028*sl 0.061 + 0.028*sl 0.054 + 0.028*sl t f 0.097 0.049 + 0.024*sl 0.053 + 0.023*sl 0.047 + 0.024*sl t plh 0.319 0.289 + 0.015*sl 0.296 + 0.013*sl 0.303 + 0.013*sl t phl 0.317 0.287 + 0.015*sl 0.294 + 0.013*sl 0.301 + 0.013*sl rn to q t f 0.101 0.055 + 0.023*sl 0.053 + 0.023*sl 0.050 + 0.024*sl t phl 0.169 0.138 + 0.016*sl 0.146 + 0.013*sl 0.153 + 0.013*sl ck to qn t r 0.102 0.049 + 0.027*sl 0.044 + 0.028*sl 0.039 + 0.029*sl t f 0.091 0.044 + 0.023*sl 0.045 + 0.023*sl 0.037 + 0.024*sl t plh 0.370 0.343 + 0.013*sl 0.347 + 0.013*sl 0.348 + 0.012*sl t phl 0.377 0.348 + 0.015*sl 0.355 + 0.013*sl 0.357 + 0.013*sl rn to qn t r 0.114 0.056 + 0.029*sl 0.060 + 0.028*sl 0.059 + 0.028*sl t plh 0.244 0.213 + 0.015*sl 0.219 + 0.014*sl 0.229 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.089 0.061 + 0.014*sl 0.063 + 0.013*sl 0.056 + 0.014*sl t f 0.077 0.052 + 0.013*sl 0.055 + 0.012*sl 0.051 + 0.012*sl t plh 0.326 0.307 + 0.009*sl 0.315 + 0.007*sl 0.327 + 0.006*sl t phl 0.322 0.303 + 0.010*sl 0.311 + 0.007*sl 0.325 + 0.007*sl rn to q t f 0.079 0.053 + 0.013*sl 0.057 + 0.012*sl 0.056 + 0.012*sl t phl 0.171 0.151 + 0.010*sl 0.160 + 0.007*sl 0.174 + 0.007*sl ck to qn t r 0.076 0.050 + 0.013*sl 0.048 + 0.014*sl 0.039 + 0.014*sl t f 0.073 0.050 + 0.012*sl 0.051 + 0.012*sl 0.042 + 0.012*sl t plh 0.407 0.391 + 0.008*sl 0.397 + 0.007*sl 0.402 + 0.006*sl t phl 0.415 0.397 + 0.009*sl 0.405 + 0.007*sl 0.414 + 0.006*sl rn to qn t r 0.088 0.059 + 0.014*sl 0.061 + 0.014*sl 0.058 + 0.014*sl t plh 0.278 0.261 + 0.009*sl 0.267 + 0.007*sl 0.279 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-315 STD111 fd2cs/fd2csd2 d flip-flop with reset, scan clock, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count fd2cs fd2csd2 fd2cs fd2csd2 d si ck sck rn d si ck sck rn 0.7 0.6 0.7 1.6 1.9 0.7 0.6 0.7 1.6 1.9 8.33 8.67 q qn si sck d ck rn d q cl clb cl cl clb qn clb sck sckb sck sckb sckb sck si rn rn rn cl clb sck sck sckb ck rn rn cl clb sckb sck truth table si sck d ck rn q (n+1) qn (n+1) x00 1 0 1 x01 1 1 0 0x0101 1x0110 xxxx0 0 1 x x 0 1 q(n) qn(n) x 0 x 1 q(n) qn(n)
STD111 3-316 samsung asic fd2cs/fd2csd2 d flip-flop with reset, scan clock, 1x/2x drive timing requirements (typical process, 25 c, 2.5v, unit = ns) parameter symbol value (ns) fd2cs fd2csd2 input setup time (d to ck) t su 0.186 0.186 input hold time (d to ck) t hd 0.132 0.131 input setup time (si to sck) t su 0.291 0.291 input hold time (si to sck) t hd 0.053 0.053 pulse width low (ck) t pwl 0.257 0.257 pulse width high (ck) t pwh 0.254 0.269 pulse width low (sck) t pwl 0.223 0.224 pulse width high (sck) t pwh 0.315 0.344 pulse width low (rn) t pwl 0.324 0.355 recovery time (rn to ck) t rc 0.000 0.000 removal time (rn to ck) t rm 0.524 0.524 recovery time (rn to sck) t rc 0.000 0.000 removal time (rn to sck) t rm 0.493 0.491
samsung asic 3-317 STD111 fd2cs/fd2csd2 d flip-flop with reset, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd2cs path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.116 0.062 + 0.027*sl 0.061 + 0.027*sl 0.055 + 0.028*sl t f 0.098 0.052 + 0.023*sl 0.053 + 0.023*sl 0.048 + 0.023*sl t plh 0.320 0.290 + 0.015*sl 0.298 + 0.013*sl 0.305 + 0.012*sl t phl 0.319 0.288 + 0.016*sl 0.297 + 0.013*sl 0.304 + 0.012*sl sck to q t r 0.132 0.079 + 0.026*sl 0.078 + 0.026*sl 0.069 + 0.027*sl t f 0.103 0.058 + 0.023*sl 0.058 + 0.023*sl 0.053 + 0.023*sl t plh 0.411 0.379 + 0.016*sl 0.389 + 0.013*sl 0.398 + 0.012*sl t phl 0.342 0.311 + 0.016*sl 0.320 + 0.013*sl 0.329 + 0.012*sl rn to q t f 0.101 0.053 + 0.024*sl 0.057 + 0.023*sl 0.050 + 0.023*sl t phl 0.172 0.140 + 0.016*sl 0.149 + 0.013*sl 0.156 + 0.013*sl ck to qn t r 0.111 0.055 + 0.028*sl 0.056 + 0.028*sl 0.052 + 0.028*sl t f 0.096 0.048 + 0.024*sl 0.048 + 0.024*sl 0.046 + 0.024*sl t plh 0.385 0.354 + 0.015*sl 0.361 + 0.013*sl 0.369 + 0.013*sl t phl 0.394 0.363 + 0.016*sl 0.370 + 0.014*sl 0.376 + 0.013*sl sck to qn t r 0.102 0.049 + 0.026*sl 0.043 + 0.028*sl 0.038 + 0.029*sl t f 0.092 0.045 + 0.023*sl 0.044 + 0.024*sl 0.037 + 0.024*sl t plh 0.395 0.368 + 0.014*sl 0.372 + 0.012*sl 0.373 + 0.012*sl t phl 0.468 0.439 + 0.015*sl 0.445 + 0.013*sl 0.448 + 0.013*sl rn to qn t r 0.114 0.056 + 0.029*sl 0.054 + 0.030*sl 0.063 + 0.029*sl t plh 0.242 0.211 + 0.015*sl 0.216 + 0.014*sl 0.223 + 0.014*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-318 samsung asic fd2cs/fd2csd2 d flip-flop with reset, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd2csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.090 0.062 + 0.014*sl 0.063 + 0.014*sl 0.058 + 0.014*sl t f 0.077 0.054 + 0.012*sl 0.055 + 0.012*sl 0.052 + 0.012*sl t plh 0.324 0.306 + 0.009*sl 0.314 + 0.007*sl 0.326 + 0.006*sl t phl 0.319 0.301 + 0.009*sl 0.309 + 0.007*sl 0.322 + 0.006*sl sck to q t r 0.108 0.080 + 0.014*sl 0.083 + 0.013*sl 0.072 + 0.014*sl t f 0.084 0.061 + 0.012*sl 0.061 + 0.011*sl 0.058 + 0.012*sl t plh 0.421 0.402 + 0.010*sl 0.411 + 0.007*sl 0.426 + 0.006*sl t phl 0.346 0.326 + 0.010*sl 0.335 + 0.007*sl 0.350 + 0.006*sl rn to q t f 0.079 0.053 + 0.013*sl 0.058 + 0.011*sl 0.054 + 0.012*sl t phl 0.170 0.151 + 0.010*sl 0.159 + 0.007*sl 0.174 + 0.006*sl ck to qn t r 0.086 0.057 + 0.014*sl 0.059 + 0.014*sl 0.054 + 0.014*sl t f 0.078 0.053 + 0.012*sl 0.056 + 0.012*sl 0.051 + 0.012*sl t plh 0.419 0.402 + 0.009*sl 0.408 + 0.007*sl 0.420 + 0.006*sl t phl 0.428 0.409 + 0.009*sl 0.417 + 0.007*sl 0.429 + 0.007*sl sck to qn t r 0.077 0.052 + 0.013*sl 0.049 + 0.014*sl 0.040 + 0.014*sl t f 0.074 0.051 + 0.011*sl 0.051 + 0.011*sl 0.043 + 0.012*sl t plh 0.434 0.418 + 0.008*sl 0.424 + 0.007*sl 0.429 + 0.006*sl t phl 0.512 0.494 + 0.009*sl 0.501 + 0.007*sl 0.511 + 0.006*sl rn to qn t r 0.089 0.060 + 0.014*sl 0.060 + 0.014*sl 0.061 + 0.014*sl t plh 0.276 0.258 + 0.009*sl 0.264 + 0.007*sl 0.273 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-319 STD111 fd2s/fd2sd2 d flip-flop with reset, scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd2s fd2sd2 fd2s fd2sd2 d ck rn ti te d ck rn ti te 0.6 0.7 1.3 0.6 1.4 0.6 0.7 1.4 0.6 1.4 7.00 7.33 parameter symbol value (ns) fd2s fd2sd2 input setup time (d to ck) t su 0.286 0.283 input hold time (d to ck) t hd 0.081 0.087 input setup time (ti to ck) t su 0.330 0.333 input hold time (ti to ck) t hd 0.052 0.057 input setup time (te to ck) t su 0.322 0.321 input hold time (te to ck) t hd 0.053 0.058 pulse width low (ck) t pwl 0.353 0.342 pulse width high (ck) t pwh 0.254 0.271 pulse width low (rn) t pwl 0.250 0.290 recovery time (rn to ck) t rc 0.000 0.000 removal time (rn to ck) t rm 0.532 0.524 q qn d ti te ck rn cl clb q clb cl qn ck cl clb te teb te rn rn rn d te ti teb clb cl rn cl clb truth table dtiteckrn q (n+1) qn (n+1) 0x0 10 1 1x0 11 0 x01 10 1 x11 11 0 xxxx00 1 x x x 1 q(n) qn(n)
STD111 3-320 samsung asic fd2s/fd2sd2 d flip-flop with reset, scan, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd2s fd2sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.116 0.061 + 0.027*sl 0.060 + 0.028*sl 0.055 + 0.028*sl t f 0.098 0.052 + 0.023*sl 0.050 + 0.023*sl 0.046 + 0.024*sl t plh 0.324 0.294 + 0.015*sl 0.301 + 0.013*sl 0.308 + 0.013*sl t phl 0.323 0.292 + 0.015*sl 0.300 + 0.013*sl 0.307 + 0.013*sl rn to q t f 0.101 0.055 + 0.023*sl 0.053 + 0.023*sl 0.050 + 0.024*sl t phl 0.169 0.138 + 0.016*sl 0.146 + 0.013*sl 0.153 + 0.013*sl ck to qn t r 0.102 0.048 + 0.027*sl 0.044 + 0.028*sl 0.039 + 0.028*sl t f 0.092 0.047 + 0.022*sl 0.043 + 0.023*sl 0.038 + 0.024*sl t plh 0.376 0.349 + 0.014*sl 0.353 + 0.012*sl 0.354 + 0.012*sl t phl 0.382 0.353 + 0.015*sl 0.360 + 0.013*sl 0.363 + 0.013*sl rn to qn t r 0.114 0.056 + 0.029*sl 0.060 + 0.028*sl 0.059 + 0.028*sl t plh 0.244 0.213 + 0.015*sl 0.219 + 0.014*sl 0.229 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.090 0.063 + 0.014*sl 0.063 + 0.013*sl 0.057 + 0.014*sl t f 0.076 0.051 + 0.013*sl 0.055 + 0.012*sl 0.051 + 0.012*sl t plh 0.330 0.312 + 0.009*sl 0.319 + 0.007*sl 0.331 + 0.006*sl t phl 0.327 0.307 + 0.010*sl 0.316 + 0.007*sl 0.329 + 0.007*sl rn to q t f 0.079 0.053 + 0.013*sl 0.057 + 0.012*sl 0.056 + 0.012*sl t phl 0.171 0.151 + 0.010*sl 0.160 + 0.007*sl 0.174 + 0.007*sl ck to qn t r 0.077 0.052 + 0.013*sl 0.049 + 0.013*sl 0.040 + 0.014*sl t f 0.072 0.046 + 0.013*sl 0.051 + 0.012*sl 0.042 + 0.012*sl t plh 0.413 0.397 + 0.008*sl 0.402 + 0.007*sl 0.408 + 0.006*sl t phl 0.420 0.402 + 0.009*sl 0.409 + 0.007*sl 0.419 + 0.006*sl rn to qn t r 0.088 0.060 + 0.014*sl 0.062 + 0.014*sl 0.059 + 0.014*sl t plh 0.280 0.262 + 0.009*sl 0.268 + 0.007*sl 0.281 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-321 STD111 fd2sq/fd2sqd2 d flip-flop with reset, scan, q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd2sq fd2sqd2 fd2sq fd2sqd2 d ck rn ti te d ck rn ti te 0.6 0.7 1.4 0.6 1.4 0.6 0.7 1.4 0.6 1.4 6.33 6.67 parameter symbol value (ns) fd2sq fd2sqd2 input setup time (d to ck) t su 0.284 0.281 input hold time (d to ck) t hd 0.084 0.084 input setup time (ti to ck) t su 0.335 0.333 input hold time (ti to ck) t hd 0.055 0.056 input setup time (te to ck) t su 0.324 0.323 input hold time (te to ck) t hd 0.054 0.054 pulse width low (ck) t pwl 0.344 0.342 pulse width high (ck) t pwh 0.247 0.255 pulse width low (rn) t pwl 0.254 0.266 recovery time (rn to ck) t rc 0.000 0.000 removal time (rn to ck) t rm 0.527 0.526 q d ti te ck rn cl clb q clb cl clb cl cl clb ck cl clb te teb te rn rn rn d te ti teb rn truth table d ti te ck rn q (n+1) 0x0 1 0 1x0 1 1 x01 1 0 x11 1 1 xxxx00 x x x 1 q(n)
STD111 3-322 samsung asic fd2sq/fd2sqd2 d flip-flop with reset, scan, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd2sq fd2sqd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.110 0.057 + 0.027*sl 0.053 + 0.028*sl 0.048 + 0.028*sl t f 0.093 0.045 + 0.024*sl 0.046 + 0.024*sl 0.040 + 0.024*sl t plh 0.312 0.283 + 0.014*sl 0.289 + 0.013*sl 0.293 + 0.012*sl t phl 0.311 0.281 + 0.015*sl 0.288 + 0.013*sl 0.292 + 0.013*sl rn to q t f 0.097 0.051 + 0.023*sl 0.048 + 0.024*sl 0.044 + 0.024*sl t phl 0.157 0.126 + 0.015*sl 0.134 + 0.013*sl 0.137 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.084 0.057 + 0.014*sl 0.057 + 0.014*sl 0.051 + 0.014*sl t f 0.071 0.046 + 0.013*sl 0.051 + 0.011*sl 0.045 + 0.012*sl t plh 0.319 0.302 + 0.009*sl 0.308 + 0.007*sl 0.319 + 0.006*sl t phl 0.314 0.296 + 0.009*sl 0.304 + 0.007*sl 0.315 + 0.006*sl rn to q t f 0.076 0.052 + 0.012*sl 0.053 + 0.011*sl 0.048 + 0.012*sl t phl 0.157 0.138 + 0.009*sl 0.147 + 0.007*sl 0.158 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-323 STD111 fd2q/fd2qd2 d flip-flop with reset, q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd2q fd2qd2 fd2q fd2qd2 d ck rn d ck rn 0.7 0.7 1.4 0.7 0.7 1.4 4.67 5.00 parameter symbol value (ns) fd2q fd2qd2 input setup time (d to ck) t su 0.184 0.281 input hold time (d to ck) t hd 0.132 0.084 pulse width low (ck) t pwl 0.260 0.342 pulse width high (ck) t pwh 0.245 0.255 pulse width low (rn) t pwl 0.256 0.266 recovery time (rn to ck) t rc 0.000 0.000 removal time (rn to ck) t rm 0.516 0.526 d ck q rn cl clb q clb cl cl clb d ck cl clb rn rn rn rn clb cl truth table d ck rn q (n+1) 010 111 xx00 x x q (n)
STD111 3-324 samsung asic fd2q/fd2qd2 d flip-flop with reset, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd2q fd2qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.110 0.056 + 0.027*sl 0.053 + 0.028*sl 0.048 + 0.028*sl t f 0.092 0.045 + 0.024*sl 0.045 + 0.024*sl 0.039 + 0.024*sl t plh 0.307 0.279 + 0.014*sl 0.285 + 0.013*sl 0.289 + 0.012*sl t phl 0.309 0.279 + 0.015*sl 0.286 + 0.013*sl 0.289 + 0.013*sl rn to q t f 0.097 0.051 + 0.023*sl 0.048 + 0.024*sl 0.043 + 0.024*sl t phl 0.157 0.127 + 0.015*sl 0.134 + 0.013*sl 0.138 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.085 0.056 + 0.014*sl 0.059 + 0.013*sl 0.050 + 0.014*sl t f 0.071 0.046 + 0.012*sl 0.049 + 0.012*sl 0.044 + 0.012*sl t plh 0.311 0.294 + 0.009*sl 0.301 + 0.007*sl 0.311 + 0.006*sl t phl 0.307 0.289 + 0.009*sl 0.296 + 0.007*sl 0.307 + 0.006*sl rn to q t f 0.076 0.052 + 0.012*sl 0.053 + 0.012*sl 0.049 + 0.012*sl t phl 0.158 0.140 + 0.009*sl 0.148 + 0.007*sl 0.160 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-325 STD111 fd3/fd3d2 d flip-flop with set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd3 fd3d2 fd3 fd3d2 d ck sn d ck sn 0.7 0.7 1.7 0.7 0.7 1.7 5.67 6.00 parameter symbol value (ns) fd3 fd3d2 input setup time (d to ck) t su 0.178 0.178 input hold time (d to ck) t hd 0.111 0.111 pulse width low (ck) t pwl 0.274 0.274 pulse width high (ck) t pwh 0.254 0.272 pulse width low (sn) t pwl 0.285 0.322 recovery time (sn to ck) t rc 0.004 0.004 removal time (sn to ck) t rm 0.227 0.227 d ck q qn sn q clb cl clb cl qn d ck cl clb cl clb sn sn sn clb cl sn truth table d ck sn q (n+1) qn (n+1) 0 101 1 110 xx010 x 1 q (n) qn (n)
STD111 3-326 samsung asic fd3/fd3d2 d flip-flop with set, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd3 fd3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.110 0.057 + 0.026*sl 0.053 + 0.028*sl 0.045 + 0.028*sl t f 0.099 0.052 + 0.024*sl 0.053 + 0.024*sl 0.049 + 0.024*sl t plh 0.314 0.285 + 0.014*sl 0.291 + 0.013*sl 0.294 + 0.012*sl t phl 0.327 0.295 + 0.016*sl 0.303 + 0.014*sl 0.311 + 0.013*sl sn to q t r 0.120 0.069 + 0.025*sl 0.063 + 0.027*sl 0.052 + 0.028*sl t plh 0.365 0.336 + 0.015*sl 0.343 + 0.013*sl 0.347 + 0.012*sl ck to qn t r 0.108 0.054 + 0.027*sl 0.051 + 0.028*sl 0.045 + 0.028*sl t f 0.092 0.044 + 0.024*sl 0.046 + 0.023*sl 0.039 + 0.024*sl t plh 0.395 0.366 + 0.015*sl 0.373 + 0.013*sl 0.377 + 0.012*sl t phl 0.384 0.354 + 0.015*sl 0.361 + 0.013*sl 0.365 + 0.013*sl sn to qn t f 0.105 0.056 + 0.025*sl 0.059 + 0.024*sl 0.058 + 0.024*sl t phl 0.178 0.145 + 0.016*sl 0.154 + 0.014*sl 0.163 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.085 0.059 + 0.013*sl 0.059 + 0.013*sl 0.048 + 0.014*sl t f 0.078 0.053 + 0.012*sl 0.056 + 0.012*sl 0.053 + 0.012*sl t plh 0.321 0.303 + 0.009*sl 0.310 + 0.007*sl 0.319 + 0.006*sl t phl 0.327 0.308 + 0.010*sl 0.317 + 0.007*sl 0.329 + 0.007*sl sn to q t r 0.098 0.074 + 0.012*sl 0.069 + 0.013*sl 0.058 + 0.014*sl t plh 0.405 0.387 + 0.009*sl 0.395 + 0.007*sl 0.406 + 0.006*sl ck to qn t r 0.084 0.056 + 0.014*sl 0.057 + 0.014*sl 0.050 + 0.014*sl t f 0.073 0.047 + 0.013*sl 0.052 + 0.012*sl 0.046 + 0.012*sl t plh 0.428 0.410 + 0.009*sl 0.417 + 0.007*sl 0.428 + 0.006*sl t phl 0.419 0.401 + 0.009*sl 0.408 + 0.007*sl 0.420 + 0.006*sl sn to qn t f 0.084 0.057 + 0.013*sl 0.062 + 0.012*sl 0.061 + 0.012*sl t phl 0.178 0.158 + 0.010*sl 0.167 + 0.008*sl 0.182 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-327 STD111 fd3cs/fd3csd2 d flip-flop with set, scan clock, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count fd3cs fd3csd2 fd3cs fd3csd2 d si ck sck sn d si ck sck sn 0.7 0.7 0.7 1.6 2.6 0.7 0.7 0.7 1.5 2.6 8.33 8.67 q qn si sck d ck sn d cl clb q cl clb cl cl clb qn clb sn sn sck sckb sn sckb sck si cl clb sck sck sckb ck sn sn sckb sck sckb sck truth table si sck d ck sn q (n+1) qn (n+1) x00 1 0 1 x01 1 1 0 0x0101 1x0110 xxxx0 1 0 x 0 x 1 q(n) qn(n) x x 0 1 q(n) qn(n)
STD111 3-328 samsung asic fd3cs/fd3csd2 d flip-flop with set, scan clock, 1x/2x drive timing requirements (typical process, 25 c, 2.5v, unit = ns) parameter symbol value (ns) fd3cs fd3csd2 input setup time (d to ck) t su 0.179 0.179 input hold time (d to ck) t hd 0.111 0.111 input setup time (si to sck) t su 0.301 0.301 input hold time (si to sck) t hd 0.060 0.060 pulse width low (ck) t pwl 0.275 0.273 pulse width high (ck) t pwh 0.260 0.279 pulse width low (sck) t pwl 0.245 0.245 pulse width high (sck) t pwh 0.325 0.361 pulse width low (sn) t pwl 0.411 0.454 recovery time (sn to ck) t rc 0.003 0.001 removal time (sn to ck) t rm 0.227 0.229 recovery time (sn to sck) t rc 0.130 0.130 removal time (sn to sck) t rm 0.098 0.099
samsung asic 3-329 STD111 fd3cs/fd3csd2 d flip-flop with set, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd3cs path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.111 0.059 + 0.026*sl 0.055 + 0.027*sl 0.046 + 0.028*sl t f 0.101 0.055 + 0.023*sl 0.055 + 0.023*sl 0.048 + 0.024*sl t plh 0.318 0.290 + 0.014*sl 0.296 + 0.013*sl 0.299 + 0.012*sl t phl 0.329 0.298 + 0.015*sl 0.306 + 0.013*sl 0.313 + 0.013*sl sck to q t r 0.128 0.077 + 0.026*sl 0.074 + 0.026*sl 0.061 + 0.028*sl t f 0.105 0.058 + 0.023*sl 0.060 + 0.023*sl 0.054 + 0.024*sl t plh 0.410 0.380 + 0.015*sl 0.388 + 0.013*sl 0.394 + 0.012*sl t phl 0.361 0.329 + 0.016*sl 0.337 + 0.014*sl 0.346 + 0.013*sl sn to q t r 0.141 0.091 + 0.025*sl 0.087 + 0.026*sl 0.077 + 0.027*sl t plh 0.549 0.517 + 0.016*sl 0.527 + 0.013*sl 0.535 + 0.012*sl ck to qn t r 0.123 0.067 + 0.028*sl 0.069 + 0.027*sl 0.067 + 0.028*sl t f 0.102 0.055 + 0.024*sl 0.056 + 0.024*sl 0.053 + 0.024*sl t plh 0.417 0.385 + 0.016*sl 0.394 + 0.014*sl 0.406 + 0.013*sl t phl 0.408 0.376 + 0.016*sl 0.385 + 0.014*sl 0.392 + 0.013*sl sck to qn t r 0.111 0.058 + 0.027*sl 0.056 + 0.027*sl 0.050 + 0.028*sl t f 0.096 0.050 + 0.023*sl 0.051 + 0.023*sl 0.044 + 0.024*sl t plh 0.436 0.407 + 0.015*sl 0.414 + 0.013*sl 0.418 + 0.012*sl t phl 0.488 0.458 + 0.015*sl 0.465 + 0.013*sl 0.470 + 0.013*sl sn to qn t f 0.109 0.059 + 0.025*sl 0.061 + 0.024*sl 0.063 + 0.024*sl t phl 0.185 0.152 + 0.017*sl 0.160 + 0.014*sl 0.169 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-330 samsung asic fd3cs/fd3csd2 d flip-flop with set, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd3csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.087 0.060 + 0.013*sl 0.060 + 0.013*sl 0.050 + 0.014*sl t f 0.079 0.054 + 0.012*sl 0.058 + 0.012*sl 0.055 + 0.012*sl t plh 0.327 0.309 + 0.009*sl 0.317 + 0.007*sl 0.326 + 0.006*sl t phl 0.330 0.311 + 0.010*sl 0.320 + 0.007*sl 0.333 + 0.006*sl sck to q t r 0.108 0.082 + 0.013*sl 0.081 + 0.013*sl 0.070 + 0.014*sl t f 0.086 0.062 + 0.012*sl 0.065 + 0.011*sl 0.061 + 0.012*sl t plh 0.430 0.411 + 0.010*sl 0.420 + 0.007*sl 0.433 + 0.006*sl t phl 0.363 0.343 + 0.010*sl 0.353 + 0.007*sl 0.367 + 0.006*sl sn to q t r 0.126 0.101 + 0.013*sl 0.101 + 0.013*sl 0.089 + 0.014*sl t plh 0.601 0.579 + 0.011*sl 0.591 + 0.007*sl 0.609 + 0.006*sl ck to qn t r 0.094 0.065 + 0.014*sl 0.067 + 0.014*sl 0.068 + 0.014*sl t f 0.080 0.056 + 0.012*sl 0.057 + 0.012*sl 0.055 + 0.012*sl t plh 0.448 0.429 + 0.010*sl 0.437 + 0.008*sl 0.454 + 0.006*sl t phl 0.441 0.422 + 0.010*sl 0.430 + 0.007*sl 0.444 + 0.007*sl sck to qn t r 0.085 0.057 + 0.014*sl 0.060 + 0.013*sl 0.051 + 0.014*sl t f 0.076 0.052 + 0.012*sl 0.055 + 0.011*sl 0.047 + 0.012*sl t plh 0.468 0.451 + 0.009*sl 0.458 + 0.007*sl 0.468 + 0.006*sl t phl 0.534 0.516 + 0.009*sl 0.523 + 0.007*sl 0.535 + 0.006*sl sn to qn t f 0.085 0.059 + 0.013*sl 0.064 + 0.012*sl 0.063 + 0.012*sl t phl 0.181 0.160 + 0.010*sl 0.170 + 0.008*sl 0.185 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-331 STD111 fd3s/fd3sd2 d flip-flop with set, scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd3s fd3sd2 fd3s fd3sd2 d ck sn ti te d ck sn ti te 0.6 0.7 1.7 0.7 1.4 0.6 0.7 1.7 0.7 1.4 7.33 7.33 parameter symbol value (ns) fd3s fd3sd2 input setup time (d to ck) t su 0.310 0.311 input hold time (d to ck) t hd 0.051 0.051 pulse width low (ck) t pwl 0.369 0.371 pulse width high (ck) t pwh 0.257 0.278 pulse width low (sn) t pwl 0.285 0.327 recovery time (sn to ck) t rc 0.001 0.003 removal time (sn to ck) t rm 0.230 0.228 input setup time (ti to ck) t su 0.312 0.312 input hold time (ti to ck) t hd 0.024 0.022 input setup time (te to ck) t su 0.327 0.328 input hold time (te to ck) t hd 0.013 0.013 q qn d ti te ck sn cl clb qn clb cl clb cl q ck cl clb te teb te sn sn sn d te ti teb cl clb sn truth table dtitecksn q (n+1) qn (n+1) 0x0 101 1x0 110 x01 101 x11 110 xxxx010 x x x 1 q (n) qn (n)
STD111 3-332 samsung asic fd3s/fd3sd2 d flip-flop with set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd3s fd3sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.109 0.056 + 0.026*sl 0.053 + 0.027*sl 0.046 + 0.028*sl t f 0.099 0.051 + 0.024*sl 0.055 + 0.023*sl 0.048 + 0.023*sl t plh 0.318 0.289 + 0.014*sl 0.295 + 0.013*sl 0.298 + 0.012*sl t phl 0.328 0.298 + 0.015*sl 0.305 + 0.013*sl 0.313 + 0.013*sl sn to q t r 0.119 0.069 + 0.025*sl 0.063 + 0.027*sl 0.052 + 0.028*sl t plh 0.364 0.335 + 0.015*sl 0.342 + 0.013*sl 0.346 + 0.012*sl ck to qn t r 0.108 0.054 + 0.027*sl 0.052 + 0.027*sl 0.046 + 0.028*sl t f 0.092 0.046 + 0.023*sl 0.047 + 0.023*sl 0.039 + 0.024*sl t plh 0.398 0.369 + 0.014*sl 0.376 + 0.013*sl 0.379 + 0.012*sl t phl 0.389 0.359 + 0.015*sl 0.367 + 0.013*sl 0.371 + 0.012*sl sn to qn t f 0.104 0.056 + 0.024*sl 0.058 + 0.023*sl 0.057 + 0.023*sl t phl 0.177 0.145 + 0.016*sl 0.153 + 0.014*sl 0.163 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.085 0.058 + 0.014*sl 0.060 + 0.013*sl 0.049 + 0.014*sl t f 0.080 0.055 + 0.012*sl 0.058 + 0.012*sl 0.054 + 0.012*sl t plh 0.331 0.313 + 0.009*sl 0.320 + 0.007*sl 0.329 + 0.006*sl t phl 0.337 0.318 + 0.010*sl 0.326 + 0.007*sl 0.339 + 0.007*sl sn to q t r 0.099 0.074 + 0.012*sl 0.071 + 0.013*sl 0.059 + 0.014*sl t plh 0.408 0.390 + 0.009*sl 0.399 + 0.007*sl 0.410 + 0.006*sl ck to qn t r 0.083 0.054 + 0.014*sl 0.057 + 0.014*sl 0.050 + 0.014*sl t f 0.073 0.047 + 0.013*sl 0.052 + 0.012*sl 0.046 + 0.012*sl t plh 0.438 0.421 + 0.009*sl 0.428 + 0.007*sl 0.438 + 0.006*sl t phl 0.431 0.412 + 0.009*sl 0.420 + 0.007*sl 0.432 + 0.006*sl sn to qn t f 0.083 0.057 + 0.013*sl 0.061 + 0.012*sl 0.060 + 0.012*sl t phl 0.176 0.156 + 0.010*sl 0.165 + 0.008*sl 0.180 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-333 STD111 fd3sq/fd3sqd2 d flip-flop with set, scan, q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd3sq fd3sqd2 fd3sq fd3sqd2 d ck sn ti te d ck sn ti te 0.6 0.7 1.1 0.7 1.4 0.6 0.7 1.0 0.7 1.4 6.33 6.67 parameter symbol value (ns) fd3sq fd3sqd2 input setup time (d to ck) t su 0.313 0.310 input hold time (d to ck) t hd 0.049 0.051 pulse width low (ck) t pwl 0.375 0.370 pulse width high (ck) t pwh 0.241 0.252 pulse width low (sn) t pwl 0.683 0.731 recovery time (sn to ck) t rc 0.000 0.001 removal time (sn to ck) t rm 0.231 0.230 input setup time (ti to ck) t su 0.316 0.313 input hold time (ti to ck) t hd 0.021 0.025 input setup time (te to ck) t su 0.327 0.327 input hold time (te to ck) t hd 0.010 0.015 q d ti te ck sn cl clb clb cl cl clb ck cl clb te teb te sn sn sn q d te ti teb clb cl sn truth table d ti te ck sn q (n+1) 0x0 10 1x0 11 x01 10 x11 11 xxxx01 x x x 1 q (n)
STD111 3-334 samsung asic fd3sq/fd3sqd2 d flip-flop with set, scan, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd3sq fd3sqd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.104 0.051 + 0.026*sl 0.046 + 0.028*sl 0.039 + 0.029*sl t f 0.093 0.047 + 0.023*sl 0.045 + 0.024*sl 0.039 + 0.024*sl t plh 0.299 0.271 + 0.014*sl 0.276 + 0.013*sl 0.277 + 0.012*sl t phl 0.311 0.281 + 0.015*sl 0.288 + 0.013*sl 0.291 + 0.013*sl sn to q t r 0.134 0.083 + 0.025*sl 0.080 + 0.026*sl 0.065 + 0.028*sl t plh 0.718 0.687 + 0.015*sl 0.696 + 0.013*sl 0.702 + 0.012*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.079 0.054 + 0.013*sl 0.051 + 0.013*sl 0.041 + 0.014*sl t f 0.074 0.049 + 0.012*sl 0.052 + 0.012*sl 0.045 + 0.012*sl t plh 0.310 0.293 + 0.008*sl 0.299 + 0.007*sl 0.305 + 0.006*sl t phl 0.319 0.301 + 0.009*sl 0.309 + 0.007*sl 0.319 + 0.006*sl sn to q t r 0.115 0.091 + 0.012*sl 0.090 + 0.013*sl 0.074 + 0.014*sl t plh 0.762 0.743 + 0.010*sl 0.753 + 0.007*sl 0.765 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-335 STD111 fd3q/fd3qd2 d flip-flop with set, q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 2.5v, unit = ns) input load (sl) gate count fd3q fd3qd2 fd3q fd3qd2 d ck sn d ck sn 0.7 0.7 1.0 0.7 0.7 1.0 5.00 5.33 parameter symbol value (ns) fd3q fd3qd2 input setup time (d to ck) t su 0.180 0.179 input hold time (d to ck) t hd 0.110 0.110 pulse width low (ck) t pwl 0.273 0.273 pulse width high (ck) t pwh 0.237 0.246 pulse width low (sn) t pwl 0.678 0.708 recovery time (sn to ck) t rc 0.003 0.003 removal time (sn to ck) t rm 0.227 0.227 d ck q sn q clb cl clb cl cl clb d ck cl clb cl clb sn sn sn sn truth table d ck sn q (n+1) 010 111 xx01 x x q (n)
STD111 3-336 samsung asic fd3q/fd3qd2 d flip-flop with set, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd3q fd3qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.104 0.051 + 0.026*sl 0.046 + 0.028*sl 0.039 + 0.029*sl t f 0.092 0.046 + 0.023*sl 0.044 + 0.024*sl 0.038 + 0.024*sl t plh 0.293 0.265 + 0.014*sl 0.270 + 0.013*sl 0.271 + 0.012*sl t phl 0.303 0.273 + 0.015*sl 0.280 + 0.013*sl 0.283 + 0.013*sl sn to q t r 0.133 0.083 + 0.025*sl 0.078 + 0.026*sl 0.064 + 0.028*sl t plh 0.705 0.674 + 0.016*sl 0.684 + 0.013*sl 0.690 + 0.012*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.080 0.054 + 0.013*sl 0.051 + 0.014*sl 0.041 + 0.014*sl t f 0.072 0.047 + 0.013*sl 0.050 + 0.012*sl 0.044 + 0.012*sl t plh 0.301 0.285 + 0.008*sl 0.291 + 0.007*sl 0.297 + 0.006*sl t phl 0.309 0.291 + 0.009*sl 0.298 + 0.007*sl 0.308 + 0.006*sl sn to q t r 0.113 0.088 + 0.013*sl 0.088 + 0.013*sl 0.071 + 0.014*sl t plh 0.727 0.707 + 0.010*sl 0.719 + 0.007*sl 0.732 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-337 STD111 fd4/fd4d2 d flip-flop with reset, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd4 fd4d2 fd4 fd4d2 d ck rn sn d ck rn sn 0.7 0.7 1.4 1.7 0.7 0.7 1.4 1.7 6.00 6.33 parameter symbol value (ns) fd4 fd4d2 input setup time (d to ck) t su 0.183 0.183 input hold time (d to ck) t hd 0.125 0.125 pulse width low (ck) t pwl 0.271 0.271 pulse width high (ck) t pwh 0.266 0.283 pulse width low (rn) t pwl 0.268 0.304 pulse width low (sn) t pwl 0.299 0.332 recovery time (rn to ck) t rc 0.000 0.000 removal time (rn to ck) t rm 0.558 0.558 recovery time (sn to ck) t rc 0.000 0.000 removal time (sn to ck) t rm 0.263 0.263 removal time (sn to rn) t rm 0.137 0.136 recovery time (sn to rn) t rc 0.083 0.084 d ck q qn rn sn d ck cl clb q cl clb cl clb cl cl clb qn clb sn sn rn rn rn rn sn sn truth table dckrnsn q (n+1) qn (n+1) 01101 11110 xx1010 xx0101 xx0000 x 1 1 q (n) qn (n)
STD111 3-338 samsung asic fd4/fd4d2 d flip-flop with reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.118 0.064 + 0.027*sl 0.063 + 0.028*sl 0.056 + 0.028*sl t f 0.104 0.056 + 0.024*sl 0.059 + 0.023*sl 0.052 + 0.024*sl t plh 0.334 0.304 + 0.015*sl 0.312 + 0.013*sl 0.318 + 0.013*sl t phl 0.350 0.318 + 0.016*sl 0.326 + 0.014*sl 0.335 + 0.013*sl rn to q t r 0.115 0.060 + 0.027*sl 0.059 + 0.028*sl 0.052 + 0.028*sl t f 0.104 0.057 + 0.024*sl 0.056 + 0.024*sl 0.052 + 0.024*sl t plh 0.147 0.117 + 0.015*sl 0.125 + 0.013*sl 0.130 + 0.012*sl t phl 0.174 0.142 + 0.016*sl 0.151 + 0.014*sl 0.158 + 0.013*sl sn to q t r 0.126 0.074 + 0.026*sl 0.070 + 0.027*sl 0.062 + 0.028*sl t plh 0.387 0.356 + 0.016*sl 0.364 + 0.013*sl 0.371 + 0.012*sl ck to qn t r 0.109 0.055 + 0.027*sl 0.053 + 0.028*sl 0.047 + 0.028*sl t f 0.094 0.046 + 0.024*sl 0.047 + 0.024*sl 0.041 + 0.024*sl t plh 0.419 0.390 + 0.015*sl 0.397 + 0.013*sl 0.401 + 0.012*sl t phl 0.409 0.378 + 0.015*sl 0.386 + 0.013*sl 0.390 + 0.013*sl rn to qn t r 0.123 0.064 + 0.029*sl 0.068 + 0.028*sl 0.072 + 0.028*sl t plh 0.267 0.234 + 0.017*sl 0.242 + 0.015*sl 0.256 + 0.013*sl sn to qn t r 0.121 0.063 + 0.029*sl 0.066 + 0.028*sl 0.068 + 0.028*sl t f 0.107 0.056 + 0.025*sl 0.061 + 0.024*sl 0.060 + 0.024*sl t plh 0.152 0.119 + 0.016*sl 0.127 + 0.014*sl 0.140 + 0.013*sl t phl 0.182 0.148 + 0.017*sl 0.157 + 0.014*sl 0.167 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-339 STD111 fd4/fd4d2 d flip-flop with reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.092 0.064 + 0.014*sl 0.067 + 0.014*sl 0.061 + 0.014*sl t f 0.083 0.059 + 0.012*sl 0.059 + 0.012*sl 0.059 + 0.012*sl t plh 0.339 0.321 + 0.009*sl 0.328 + 0.007*sl 0.341 + 0.006*sl t phl 0.352 0.333 + 0.010*sl 0.341 + 0.007*sl 0.355 + 0.007*sl rn to q t r 0.089 0.062 + 0.013*sl 0.062 + 0.014*sl 0.056 + 0.014*sl t f 0.081 0.055 + 0.013*sl 0.060 + 0.012*sl 0.058 + 0.012*sl t plh 0.151 0.134 + 0.009*sl 0.141 + 0.007*sl 0.153 + 0.006*sl t phl 0.173 0.153 + 0.010*sl 0.162 + 0.007*sl 0.176 + 0.007*sl sn to q t r 0.103 0.076 + 0.013*sl 0.078 + 0.013*sl 0.067 + 0.014*sl t plh 0.423 0.404 + 0.009*sl 0.413 + 0.007*sl 0.427 + 0.006*sl ck to qn t r 0.086 0.058 + 0.014*sl 0.060 + 0.013*sl 0.051 + 0.014*sl t f 0.076 0.053 + 0.012*sl 0.054 + 0.011*sl 0.048 + 0.012*sl t plh 0.455 0.438 + 0.009*sl 0.445 + 0.007*sl 0.456 + 0.006*sl t phl 0.443 0.425 + 0.009*sl 0.433 + 0.007*sl 0.445 + 0.006*sl rn to qn t r 0.097 0.069 + 0.014*sl 0.068 + 0.014*sl 0.075 + 0.014*sl t plh 0.299 0.279 + 0.010*sl 0.287 + 0.008*sl 0.305 + 0.007*sl sn to qn t r 0.093 0.063 + 0.015*sl 0.065 + 0.014*sl 0.070 + 0.014*sl t f 0.085 0.059 + 0.013*sl 0.064 + 0.012*sl 0.063 + 0.012*sl t plh 0.154 0.135 + 0.010*sl 0.142 + 0.008*sl 0.159 + 0.007*sl t phl 0.181 0.160 + 0.010*sl 0.170 + 0.008*sl 0.186 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-340 samsung asic fd4cs/fd4csd2 d flip-flop with reset, set, scan clock, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count fd4cs fd4csd2 fd4cs fd4csd2 d si ck sck sn rn d si ck sck sn rn 0.6 0.7 0.7 1.4 2.7 1.8 0.7 0.7 0.7 1.5 2.7 1.8 9.33 9.67 q qn si sck d ck rn sn d cl clb q cl clb cl cl clb qn clb sn sn rn rn sck sckb si sck sckb sck sckb sn rn sckb sck cl clb sck sck sckb ck rn rn sn sn truth table si sck d ck rn sn q (n+1) qn (n+1) x00 11 0 1 x01 11 1 0 0x01101 1x01110 xxxx10 1 0 xxxx01 0 1 xxxx00 0 0 x 0 x 1 1 q(n) qn(n) x x 0 1 1 q(n) qn(n)
samsung asic 3-341 STD111 fd4cs/fd4csd2 d flip-flop with reset, set, scan clock, 1x/2x drive timing requirements (typical process, 25 c, 2.5v, unit = ns) parameter symbol value (ns) fd4cs fd4csd2 input setup time (d to ck) t su 0.185 0.185 input hold time (d to ck) t hd 0.122 0.123 input setup time (si to sck) t su 0.301 0.300 input hold time (si to sck) t hd 0.057 0.057 pulse width low (ck) t pwl 0.270 0.270 pulse width high (ck) t pwh 0.267 0.285 pulse width low (sck) t pwl 0.242 0.242 pulse width high (sck) t pwh 0.333 0.363 pulse width low (sn) t pwl 0.420 0.451 recovery time (sn to ck) t rc 0.000 0.000 removal time (sn to ck) t rm 0.260 0.260 recovery time (sn to sck) t rc 0.116 0.116 removal time (sn to sck) t rm 0.129 0.129 pulse width low (rn) t pwl 0.341 0.371 recovery time (rn to ck) t rc 0.000 0.000 removal time (rn to ck) t rm 0.553 0.553 recovery time (rn to sck) t rc 0.000 0.000 removal time (rn to sck) t rm 0.549 0.549 removal time (sn to rn) t rm 0.136 0.135 recovery time (sn to rn) t rc 0.084 0.085
STD111 3-342 samsung asic fd4cs/fd4csd2 d flip-flop with reset, set, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd4cs path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.118 0.064 + 0.027*sl 0.063 + 0.027*sl 0.056 + 0.028*sl t f 0.103 0.056 + 0.023*sl 0.058 + 0.023*sl 0.051 + 0.023*sl t plh 0.335 0.304 + 0.015*sl 0.312 + 0.013*sl 0.319 + 0.013*sl t phl 0.344 0.312 + 0.016*sl 0.321 + 0.013*sl 0.329 + 0.013*sl sck to q t r 0.134 0.081 + 0.026*sl 0.079 + 0.027*sl 0.070 + 0.028*sl t f 0.108 0.061 + 0.023*sl 0.065 + 0.022*sl 0.057 + 0.023*sl t plh 0.424 0.392 + 0.016*sl 0.401 + 0.014*sl 0.411 + 0.013*sl t phl 0.383 0.352 + 0.016*sl 0.360 + 0.014*sl 0.371 + 0.013*sl sn to q t r 0.146 0.093 + 0.027*sl 0.093 + 0.027*sl 0.085 + 0.028*sl t plh 0.555 0.521 + 0.017*sl 0.532 + 0.014*sl 0.542 + 0.013*sl rn to q t r 0.114 0.059 + 0.027*sl 0.059 + 0.027*sl 0.051 + 0.028*sl t f 0.102 0.056 + 0.023*sl 0.055 + 0.023*sl 0.051 + 0.023*sl t plh 0.148 0.118 + 0.015*sl 0.126 + 0.013*sl 0.131 + 0.012*sl t phl 0.173 0.141 + 0.016*sl 0.150 + 0.013*sl 0.157 + 0.013*sl ck to qn t r 0.120 0.063 + 0.029*sl 0.067 + 0.028*sl 0.063 + 0.028*sl t f 0.103 0.055 + 0.024*sl 0.056 + 0.024*sl 0.053 + 0.024*sl t plh 0.429 0.396 + 0.016*sl 0.405 + 0.014*sl 0.417 + 0.013*sl t phl 0.426 0.394 + 0.016*sl 0.403 + 0.014*sl 0.410 + 0.013*sl sck to qn t r 0.111 0.057 + 0.027*sl 0.054 + 0.028*sl 0.047 + 0.028*sl t f 0.098 0.053 + 0.023*sl 0.050 + 0.023*sl 0.043 + 0.024*sl t plh 0.456 0.427 + 0.015*sl 0.434 + 0.013*sl 0.438 + 0.012*sl t phl 0.502 0.471 + 0.015*sl 0.479 + 0.013*sl 0.484 + 0.013*sl sn to qn t r 0.123 0.064 + 0.030*sl 0.064 + 0.030*sl 0.072 + 0.029*sl t f 0.109 0.058 + 0.025*sl 0.061 + 0.025*sl 0.062 + 0.024*sl t plh 0.153 0.120 + 0.016*sl 0.127 + 0.015*sl 0.136 + 0.014*sl t phl 0.185 0.151 + 0.017*sl 0.160 + 0.015*sl 0.169 + 0.014*sl rn to qn t r 0.124 0.065 + 0.030*sl 0.064 + 0.030*sl 0.075 + 0.029*sl t plh 0.264 0.230 + 0.017*sl 0.237 + 0.015*sl 0.247 + 0.014*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-343 STD111 fd4cs/fd4csd2 d flip-flop with reset, set, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd4csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.092 0.065 + 0.014*sl 0.065 + 0.014*sl 0.060 + 0.014*sl t f 0.082 0.059 + 0.011*sl 0.059 + 0.012*sl 0.058 + 0.012*sl t plh 0.341 0.322 + 0.009*sl 0.330 + 0.007*sl 0.343 + 0.006*sl t phl 0.347 0.328 + 0.010*sl 0.337 + 0.007*sl 0.351 + 0.006*sl sck to q t r 0.111 0.085 + 0.013*sl 0.084 + 0.013*sl 0.077 + 0.014*sl t f 0.088 0.065 + 0.012*sl 0.066 + 0.011*sl 0.063 + 0.012*sl t plh 0.436 0.416 + 0.010*sl 0.425 + 0.007*sl 0.440 + 0.006*sl t phl 0.390 0.370 + 0.010*sl 0.379 + 0.007*sl 0.394 + 0.006*sl sn to q t r 0.127 0.102 + 0.013*sl 0.100 + 0.013*sl 0.094 + 0.014*sl t plh 0.596 0.575 + 0.010*sl 0.586 + 0.008*sl 0.603 + 0.006*sl rn to q t r 0.089 0.062 + 0.014*sl 0.062 + 0.014*sl 0.056 + 0.014*sl t f 0.080 0.054 + 0.013*sl 0.059 + 0.011*sl 0.056 + 0.012*sl t plh 0.152 0.134 + 0.009*sl 0.141 + 0.007*sl 0.153 + 0.006*sl t phl 0.172 0.153 + 0.010*sl 0.161 + 0.007*sl 0.175 + 0.006*sl ck to qn t r 0.095 0.068 + 0.014*sl 0.067 + 0.014*sl 0.068 + 0.014*sl t f 0.083 0.059 + 0.012*sl 0.061 + 0.012*sl 0.058 + 0.012*sl t plh 0.464 0.445 + 0.010*sl 0.453 + 0.008*sl 0.469 + 0.006*sl t phl 0.460 0.441 + 0.010*sl 0.450 + 0.007*sl 0.464 + 0.006*sl sck to qn t r 0.087 0.059 + 0.014*sl 0.061 + 0.013*sl 0.052 + 0.014*sl t f 0.078 0.053 + 0.012*sl 0.058 + 0.011*sl 0.051 + 0.012*sl t plh 0.495 0.478 + 0.009*sl 0.485 + 0.007*sl 0.496 + 0.006*sl t phl 0.545 0.526 + 0.009*sl 0.534 + 0.007*sl 0.547 + 0.006*sl sn to qn t r 0.096 0.070 + 0.013*sl 0.064 + 0.015*sl 0.071 + 0.014*sl t f 0.087 0.061 + 0.013*sl 0.066 + 0.012*sl 0.065 + 0.012*sl t plh 0.155 0.135 + 0.010*sl 0.143 + 0.008*sl 0.156 + 0.007*sl t phl 0.183 0.163 + 0.010*sl 0.172 + 0.008*sl 0.187 + 0.007*sl rn to qn t r 0.098 0.069 + 0.015*sl 0.069 + 0.015*sl 0.074 + 0.014*sl t plh 0.295 0.276 + 0.010*sl 0.283 + 0.008*sl 0.296 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-344 samsung asic fd4s/fd4sd2 d flip-flop with reset, set, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count fd4s fd4sd2 fd4s fd4sd2 d ck rn sn ti ie d ck rn sn ti ie 0.6 0.7 1.4 1.7 0.7 1.4 0.6 0.7 1.4 1.7 0.7 1.4 7.67 8.00 q qn d ti te ck rn sn cl clb clb cl clb cl cl clb ck cl clb te teb te sn rn rn rn rn sn q qn sn sn d te ti teb truth table dtiteckrnsn q (n+1) qn (n+1) 0x0 11 0 1 1x0 11 1 0 x01 11 0 1 x11 11 1 0 xxxx10 1 0 xxxx01 0 1 xxxx00 0 0 x x x 1 1 q (n) qn (n)
samsung asic 3-345 STD111 fd4s/fd4sd2 d flip-flop with reset, set, scan, 1x/2x drive timing requirements (typical process, 25 c, 2.5v, unit = ns) parameter symbol value (ns) fd4s fd4sd2 input setup time (d to ck) t su 0.303 0.303 input hold time (d to ck) t hd 0.071 0.070 pulse width low (ck) t pwl 0.364 0.364 pulse width high (ck) t pwh 0.268 0.285 pulse width low (rn) t pwl 0.268 0.304 pulse width low (sn) t pwl 0.300 0.332 recovery time (rn to ck) t rc 0.000 0.000 removal time (rn to ck) t rm 0.564 0.564 recovery time (sn to ck) t rc 0.000 0.000 removal time (sn to ck) t rm 0.265 0.265 input setup time (ti to ck) t su 0.323 0.323 input hold time (ti to ck) t hd 0.042 0.042 input setup time (te to ck) t su 0.319 0.319 input hold time (te to ck) t hd 0.034 0.034 recovery time (sn to rn) t rc 0.083 0.084 removal time (sn to rn) t rm 0.137 0.136
STD111 3-346 samsung asic fd4s/fd4sd2 d flip-flop with reset, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd4s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.117 0.062 + 0.028*sl 0.063 + 0.028*sl 0.056 + 0.028*sl t f 0.104 0.056 + 0.024*sl 0.058 + 0.023*sl 0.053 + 0.024*sl t plh 0.339 0.308 + 0.015*sl 0.316 + 0.013*sl 0.323 + 0.013*sl t phl 0.354 0.322 + 0.016*sl 0.330 + 0.014*sl 0.339 + 0.013*sl rn to q t r 0.114 0.060 + 0.027*sl 0.059 + 0.027*sl 0.052 + 0.028*sl t f 0.104 0.057 + 0.024*sl 0.056 + 0.024*sl 0.052 + 0.024*sl t plh 0.148 0.117 + 0.015*sl 0.125 + 0.013*sl 0.130 + 0.012*sl t phl 0.174 0.142 + 0.016*sl 0.151 + 0.014*sl 0.158 + 0.013*sl sn to q t r 0.126 0.074 + 0.026*sl 0.070 + 0.027*sl 0.062 + 0.028*sl t plh 0.387 0.356 + 0.016*sl 0.365 + 0.013*sl 0.372 + 0.012*sl ck to qn t r 0.109 0.055 + 0.027*sl 0.053 + 0.028*sl 0.047 + 0.028*sl t f 0.095 0.048 + 0.023*sl 0.049 + 0.023*sl 0.041 + 0.024*sl t plh 0.423 0.394 + 0.015*sl 0.401 + 0.013*sl 0.405 + 0.012*sl t phl 0.413 0.383 + 0.015*sl 0.390 + 0.013*sl 0.395 + 0.013*sl rn to qn t r 0.123 0.064 + 0.029*sl 0.068 + 0.028*sl 0.072 + 0.028*sl t plh 0.267 0.234 + 0.017*sl 0.242 + 0.015*sl 0.256 + 0.013*sl sn to qn t r 0.121 0.063 + 0.029*sl 0.066 + 0.028*sl 0.068 + 0.028*sl t f 0.107 0.056 + 0.025*sl 0.061 + 0.024*sl 0.060 + 0.024*sl t plh 0.152 0.119 + 0.016*sl 0.127 + 0.014*sl 0.140 + 0.013*sl t phl 0.182 0.149 + 0.017*sl 0.157 + 0.014*sl 0.167 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-347 STD111 fd4s/fd4sd2 d flip-flop with reset, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd4sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.092 0.066 + 0.013*sl 0.065 + 0.014*sl 0.061 + 0.014*sl t f 0.082 0.057 + 0.013*sl 0.060 + 0.012*sl 0.058 + 0.012*sl t plh 0.344 0.325 + 0.009*sl 0.333 + 0.007*sl 0.346 + 0.006*sl t phl 0.356 0.337 + 0.010*sl 0.345 + 0.007*sl 0.359 + 0.007*sl rn to q t r 0.089 0.062 + 0.014*sl 0.062 + 0.014*sl 0.056 + 0.014*sl t f 0.081 0.055 + 0.013*sl 0.060 + 0.012*sl 0.058 + 0.012*sl t plh 0.151 0.134 + 0.009*sl 0.141 + 0.007*sl 0.153 + 0.006*sl t phl 0.173 0.153 + 0.010*sl 0.162 + 0.007*sl 0.176 + 0.007*sl sn to q t r 0.103 0.076 + 0.014*sl 0.078 + 0.013*sl 0.067 + 0.014*sl t plh 0.423 0.404 + 0.009*sl 0.413 + 0.007*sl 0.427 + 0.006*sl ck to qn t r 0.086 0.059 + 0.013*sl 0.059 + 0.013*sl 0.051 + 0.014*sl t f 0.076 0.052 + 0.012*sl 0.055 + 0.011*sl 0.048 + 0.012*sl t plh 0.459 0.442 + 0.009*sl 0.449 + 0.007*sl 0.459 + 0.006*sl t phl 0.447 0.429 + 0.009*sl 0.437 + 0.007*sl 0.449 + 0.006*sl rn to qn t r 0.097 0.069 + 0.014*sl 0.068 + 0.014*sl 0.075 + 0.014*sl t plh 0.299 0.279 + 0.010*sl 0.287 + 0.008*sl 0.305 + 0.007*sl sn to qn t r 0.093 0.063 + 0.015*sl 0.065 + 0.014*sl 0.070 + 0.014*sl t f 0.085 0.059 + 0.013*sl 0.064 + 0.012*sl 0.063 + 0.012*sl t plh 0.154 0.135 + 0.010*sl 0.142 + 0.008*sl 0.159 + 0.007*sl t phl 0.180 0.160 + 0.010*sl 0.170 + 0.008*sl 0.186 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-348 samsung asic fd4sq/fd4sqd2 d flip-flop with reset, set, scan, q output only, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count fd4sq fd4sqd2 fd4sq fd4sqd2 d ck rn sn ti te d ck rn sn ti te 0.6 0.9 1.5 1.4 0.7 1.7 0.6 0.9 1.5 1.4 0.7 1.7 7.00 7.33 q d ti te ck rn sn cl clb clb cl clb cl cl clb ck cl clb te teb te sn rn rn rn sn q sn rn sn d te ti teb truth table d ti te ck rn sn q (n+1) 0x0 11 0 1x0 11 1 x01 11 0 x11 11 1 xxxx10 1 xxxx01 0 xxxx00 0 x x x 1 1 q (n)
samsung asic 3-349 STD111 fd4sq/fd4sqd2 d flip-flop with reset, set, scan, q output only, 1x/2x drive timing requirements (typical process, 25 c, 1.8v, unit = ns) parameter symbol value (ns) fd4sq fd4sqd2 input setup time (d to ck) t su 0.303 0.303 input hold time (d to ck) t hd 0.069 0.069 pulse width low (ck) t pwl 0.362 0.362 pulse width high (ck) t pwh 0.247 0.255 pulse width low (rn) t pwl 0.311 0.316 pulse width low (sn) t pwl 0.699 0.726 recovery time (rn to ck) t rc 0.000 0.000 removal time (rn to ck) t rm 0.563 0.563 recovery time (sn to ck) t rc 0.000 0.000 removal time (sn to ck) t rm 0.268 0.268 input setup time (ti to ck) t su 0.323 0.323 input hold time (ti to ck) t hd 0.041 0.041 input setup time (te to ck) t su 0.319 0.319 input hold time (te to ck) t hd 0.035 0.035 removal time (sn to rn) t rm 0.139 0.137 recovery time (sn to rn) t rc 0.081 0.083
STD111 3-350 samsung asic fd4sq/fd4sqd2 d flip-flop with reset, set, scan, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd4sq fd4sqd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.110 0.056 + 0.027*sl 0.053 + 0.028*sl 0.047 + 0.028*sl t f 0.095 0.048 + 0.023*sl 0.049 + 0.023*sl 0.041 + 0.024*sl t plh 0.315 0.285 + 0.015*sl 0.292 + 0.013*sl 0.296 + 0.012*sl t phl 0.326 0.296 + 0.015*sl 0.303 + 0.013*sl 0.308 + 0.013*sl rn to q t r 0.110 0.056 + 0.027*sl 0.053 + 0.028*sl 0.046 + 0.028*sl t f 0.096 0.052 + 0.022*sl 0.047 + 0.023*sl 0.042 + 0.024*sl t plh 0.134 0.105 + 0.015*sl 0.111 + 0.013*sl 0.115 + 0.012*sl t phl 0.157 0.127 + 0.015*sl 0.135 + 0.013*sl 0.138 + 0.013*sl sn to q t r 0.139 0.087 + 0.026*sl 0.085 + 0.026*sl 0.073 + 0.028*sl t plh 0.741 0.710 + 0.016*sl 0.718 + 0.013*sl 0.727 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.085 0.057 + 0.014*sl 0.059 + 0.013*sl 0.050 + 0.014*sl t f 0.074 0.050 + 0.012*sl 0.053 + 0.011*sl 0.047 + 0.012*sl t plh 0.322 0.304 + 0.009*sl 0.311 + 0.007*sl 0.322 + 0.006*sl t phl 0.330 0.312 + 0.009*sl 0.320 + 0.007*sl 0.332 + 0.006*sl rn to q t r 0.085 0.055 + 0.015*sl 0.061 + 0.013*sl 0.050 + 0.014*sl t f 0.075 0.052 + 0.012*sl 0.053 + 0.011*sl 0.047 + 0.012*sl t plh 0.139 0.122 + 0.008*sl 0.128 + 0.007*sl 0.139 + 0.006*sl t phl 0.158 0.139 + 0.009*sl 0.148 + 0.007*sl 0.159 + 0.006*sl sn to q t r 0.117 0.092 + 0.013*sl 0.091 + 0.013*sl 0.080 + 0.014*sl t plh 0.758 0.738 + 0.010*sl 0.748 + 0.007*sl 0.763 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-351 STD111 fd4q/fd4qd2 d flip-flop with reset, set, q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd4q fd4qd2 fd4q fd4qd2 d ck rn sn d ck rn sn 0.7 0.7 1.4 1.0 0.7 0.7 1.4 1.0 5.33 5.67 parameter symbol value (ns) fd4q fd4qd2 input setup time (d to ck) t su 0.184 0.184 input hold time (d to ck) t hd 0.122 0.122 pulse width low (ck) t pwl 0.270 0.270 pulse width high (ck) t pwh 0.244 0.252 pulse width low (rn) t pwl 0.311 0.316 pulse width low (sn) t pwl 0.699 0.726 recovery time (rn to ck) t rc 0.000 0.000 removal time (rn to ck) t rm 0.557 0.557 recovery time (sn to ck) t rc 0.000 0.000 removal time (sn to ck) t rm 0.262 0.262 recovery time (sn to rn) t rc 0.081 0.083 removal time (sn to rn) t rm 0.139 0.137 d ck q sn rn d ck cl clb q cl clb cl clb cl cl clb clb sn sn rn rn rn rn sn sn truth table d ck rn sn q (n+1) 0110 1111 xx101 xx010 xx000 x 1 1 q (n)
STD111 3-352 samsung asic fd4q/fd4qd2 d flip-flop with reset, set, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd4q fd4qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.110 0.057 + 0.027*sl 0.053 + 0.028*sl 0.047 + 0.028*sl t f 0.095 0.048 + 0.023*sl 0.048 + 0.023*sl 0.041 + 0.024*sl t plh 0.311 0.282 + 0.015*sl 0.288 + 0.013*sl 0.292 + 0.012*sl t phl 0.321 0.291 + 0.015*sl 0.299 + 0.013*sl 0.303 + 0.013*sl rn to q t r 0.110 0.056 + 0.027*sl 0.053 + 0.028*sl 0.046 + 0.028*sl t f 0.097 0.053 + 0.022*sl 0.047 + 0.023*sl 0.042 + 0.024*sl t plh 0.134 0.105 + 0.015*sl 0.111 + 0.013*sl 0.115 + 0.012*sl t phl 0.157 0.127 + 0.015*sl 0.135 + 0.013*sl 0.138 + 0.013*sl sn to q t r 0.138 0.087 + 0.025*sl 0.082 + 0.027*sl 0.074 + 0.028*sl t plh 0.735 0.702 + 0.016*sl 0.713 + 0.014*sl 0.722 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.085 0.057 + 0.014*sl 0.058 + 0.014*sl 0.051 + 0.014*sl t f 0.074 0.049 + 0.012*sl 0.052 + 0.011*sl 0.047 + 0.012*sl t plh 0.318 0.300 + 0.009*sl 0.307 + 0.007*sl 0.318 + 0.006*sl t phl 0.325 0.307 + 0.009*sl 0.315 + 0.007*sl 0.327 + 0.006*sl rn to q t r 0.085 0.055 + 0.015*sl 0.061 + 0.013*sl 0.050 + 0.014*sl t f 0.075 0.051 + 0.012*sl 0.053 + 0.011*sl 0.047 + 0.012*sl t plh 0.139 0.122 + 0.008*sl 0.128 + 0.007*sl 0.139 + 0.006*sl t phl 0.158 0.139 + 0.009*sl 0.148 + 0.007*sl 0.159 + 0.006*sl sn to q t r 0.117 0.091 + 0.013*sl 0.091 + 0.013*sl 0.079 + 0.014*sl t plh 0.752 0.731 + 0.010*sl 0.743 + 0.007*sl 0.758 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-353 STD111 fd5/fd5d2 d flip-flop with negative edge trigger, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd5 fd5d2 fd5 fd5d2 d ckn d ckn 0.7 0.7 0.7 0.7 5.00 5.00 parameter symbol value (ns) fd5 fd5d2 input setup time (d to ckn) t su 0.196 0.191 input hold time (d to ckn) t hd 0.138 0.140 pulse width low (ckn) t pwl 0.227 0.245 pulse width high (ckn) t pwh 0.227 0.245 d ckn q qn cln clbn clbn cln cln clbn clbn cln d ckn cln clbn qn q truth table d ckn q (n+1) qn (n+1) 001 110 x q (n) qn (n)
STD111 3-354 samsung asic fd5/fd5d2 d flip-flop with negative edge trigger, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd5 fd5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t r 0.109 0.055 + 0.027*sl 0.052 + 0.028*sl 0.045 + 0.028*sl t f 0.096 0.049 + 0.023*sl 0.049 + 0.024*sl 0.044 + 0.024*sl t plh 0.322 0.294 + 0.014*sl 0.299 + 0.013*sl 0.303 + 0.012*sl t phl 0.284 0.253 + 0.015*sl 0.261 + 0.013*sl 0.267 + 0.013*sl ckn to qn t r 0.100 0.046 + 0.027*sl 0.043 + 0.028*sl 0.038 + 0.029*sl t f 0.088 0.041 + 0.024*sl 0.041 + 0.024*sl 0.035 + 0.024*sl t plh 0.335 0.308 + 0.013*sl 0.311 + 0.012*sl 0.312 + 0.012*sl t phl 0.379 0.350 + 0.015*sl 0.356 + 0.013*sl 0.358 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t r 0.084 0.057 + 0.013*sl 0.056 + 0.013*sl 0.046 + 0.014*sl t f 0.074 0.048 + 0.013*sl 0.052 + 0.012*sl 0.048 + 0.012*sl t plh 0.335 0.318 + 0.009*sl 0.325 + 0.007*sl 0.333 + 0.006*sl t phl 0.289 0.270 + 0.009*sl 0.279 + 0.007*sl 0.291 + 0.006*sl ckn to qn t r 0.077 0.052 + 0.013*sl 0.049 + 0.014*sl 0.039 + 0.014*sl t f 0.071 0.047 + 0.012*sl 0.048 + 0.012*sl 0.040 + 0.012*sl t plh 0.376 0.360 + 0.008*sl 0.366 + 0.007*sl 0.371 + 0.006*sl t phl 0.420 0.403 + 0.009*sl 0.410 + 0.007*sl 0.419 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-355 STD111 fd5s/fd5sd2 d flip-flop with negative edge trigger, scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd5s fd5sd2 fd5s fd5sd2 d ckn ti te d ckn ti te 0.6 0.7 0.6 1.4 0.6 0.7 0.6 1.4 6.33 6.67 parameter symbol value (ns) fd5s fd5sd2 input setup time (d to ckn) t su 0.349 0.347 input hold time (d to ckn) t hd 0.091 0.091 pulse width low (ckn) t pwl 0.231 0.244 pulse width high (ckn) t pwh 0.231 0.244 input setup time (ti to ckn) t su 0.334 0.333 input hold time (ti to ckn) t hd 0.083 0.082 input setup time (te to ckn) t su 0.352 0.352 input hold time (te to ckn) t hd 0.107 0.109 q qn d ti te ckn cln clbn clbn cln cln clbn cln clbn te teb te q qn d te ti teb cln clbn ckn truth table d ti te ckn q (n+1) qn (n+1) 0x0 01 1x0 10 x01 01 x11 10 x x x q (n) qn (n)
STD111 3-356 samsung asic fd5s/fd5sd2 d flip-flop with negative edge trigger, scan, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd5s fd5sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t r 0.109 0.056 + 0.027*sl 0.053 + 0.028*sl 0.046 + 0.028*sl t f 0.096 0.048 + 0.024*sl 0.050 + 0.024*sl 0.045 + 0.024*sl t plh 0.331 0.303 + 0.014*sl 0.308 + 0.013*sl 0.311 + 0.012*sl t phl 0.292 0.261 + 0.015*sl 0.268 + 0.013*sl 0.275 + 0.013*sl ckn to qn t r 0.102 0.048 + 0.027*sl 0.043 + 0.028*sl 0.038 + 0.029*sl t f 0.090 0.045 + 0.023*sl 0.040 + 0.024*sl 0.036 + 0.024*sl t plh 0.343 0.316 + 0.013*sl 0.319 + 0.013*sl 0.321 + 0.012*sl t phl 0.388 0.359 + 0.015*sl 0.365 + 0.013*sl 0.368 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t r 0.083 0.057 + 0.013*sl 0.055 + 0.014*sl 0.046 + 0.014*sl t f 0.075 0.049 + 0.013*sl 0.054 + 0.012*sl 0.049 + 0.012*sl t plh 0.336 0.319 + 0.009*sl 0.326 + 0.007*sl 0.333 + 0.006*sl t phl 0.293 0.274 + 0.010*sl 0.283 + 0.007*sl 0.296 + 0.006*sl ckn to qn t r 0.078 0.051 + 0.013*sl 0.050 + 0.013*sl 0.039 + 0.014*sl t f 0.070 0.046 + 0.012*sl 0.047 + 0.012*sl 0.041 + 0.012*sl t plh 0.380 0.364 + 0.008*sl 0.369 + 0.007*sl 0.375 + 0.006*sl t phl 0.421 0.403 + 0.009*sl 0.411 + 0.007*sl 0.420 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-357 STD111 fd6/fd6d2 d flip-flop with negative edge trigger, reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd6 fd6d2 fd6 fd6d2 d ckn rn d ckn rn 0.7 0.7 1.3 0.7 0.7 1.3 5.33 5.67 parameter symbol value (ns) fd6 fd6d2 input setup time (d to ckn) t su 0.203 0.195 input hold time (d to ckn) t hd 0.134 0.136 pulse width low (ckn) t pwl 0.232 0.247 pulse width high (ckn) t pwh 0.232 0.247 pulse width low (rn) t pwl 0.486 0.484 recovery time (rn to ck) t rc 0.000 0.000 removal time (rn to ck) t rm 0.601 0.600 d ckn q qn rn cln clbn cln clbn d ckn cln clbn clbn cln rn rn qn q rn cln clbn rn truth table d ckn rn q (n+1) qn (n+1) 0 101 1 110 xx001 x 1 q (n) qn (n)
STD111 3-358 samsung asic fd6/fd6d2 d flip-flop with negative edge trigger, reset, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd6 fd6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t r 0.116 0.061 + 0.027*sl 0.061 + 0.028*sl 0.055 + 0.028*sl t f 0.098 0.051 + 0.023*sl 0.053 + 0.023*sl 0.046 + 0.024*sl t plh 0.337 0.307 + 0.015*sl 0.314 + 0.013*sl 0.321 + 0.013*sl t phl 0.299 0.268 + 0.015*sl 0.276 + 0.013*sl 0.283 + 0.013*sl rn to q t f 0.101 0.056 + 0.023*sl 0.054 + 0.023*sl 0.050 + 0.024*sl t phl 0.170 0.138 + 0.016*sl 0.146 + 0.013*sl 0.153 + 0.013*sl ckn to qn t r 0.102 0.049 + 0.027*sl 0.044 + 0.028*sl 0.039 + 0.029*sl t f 0.091 0.047 + 0.022*sl 0.042 + 0.023*sl 0.038 + 0.024*sl t plh 0.351 0.324 + 0.014*sl 0.328 + 0.012*sl 0.329 + 0.012*sl t phl 0.395 0.366 + 0.015*sl 0.373 + 0.013*sl 0.376 + 0.013*sl rn to qn t r 0.115 0.057 + 0.029*sl 0.059 + 0.028*sl 0.059 + 0.028*sl t plh 0.244 0.213 + 0.015*sl 0.219 + 0.014*sl 0.229 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t r 0.089 0.062 + 0.014*sl 0.063 + 0.013*sl 0.057 + 0.014*sl t f 0.077 0.054 + 0.012*sl 0.053 + 0.012*sl 0.051 + 0.012*sl t plh 0.343 0.325 + 0.009*sl 0.333 + 0.007*sl 0.345 + 0.006*sl t phl 0.302 0.283 + 0.009*sl 0.291 + 0.007*sl 0.305 + 0.007*sl rn to q t f 0.079 0.053 + 0.013*sl 0.057 + 0.012*sl 0.056 + 0.012*sl t phl 0.170 0.151 + 0.010*sl 0.160 + 0.007*sl 0.173 + 0.007*sl ckn to qn t r 0.077 0.051 + 0.013*sl 0.049 + 0.013*sl 0.039 + 0.014*sl t f 0.073 0.050 + 0.012*sl 0.051 + 0.012*sl 0.043 + 0.012*sl t plh 0.387 0.372 + 0.008*sl 0.377 + 0.007*sl 0.383 + 0.006*sl t phl 0.433 0.415 + 0.009*sl 0.422 + 0.007*sl 0.432 + 0.006*sl rn to qn t r 0.088 0.059 + 0.014*sl 0.061 + 0.014*sl 0.058 + 0.014*sl t plh 0.278 0.260 + 0.009*sl 0.266 + 0.007*sl 0.279 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-359 STD111 fd6s/fd6sd2 d flip-flop with negative edge trigger, reset, scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd6s fd6sd2 fd6s fd6sd2 d ckn rn ti te d ckn rn ti te 0.6 0.7 1.3 0.7 1.4 0.7 0.7 1.4 0.6 1.4 7.00 7.33 parameter symbol value (ns) fd6s fd6sd2 input setup time (d to ckn) t su 0.359 0.357 input hold time (d to ckn) t hd 0.082 0.080 pulse width low (ckn) t pwl 0.236 0.249 pulse width high (ckn) t pwh 0.236 0.249 pulse width low (rn) t pwl 0.500 0.500 recovery time (rn to ckn) t rc 0.000 0.000 removal time (rn to ckn) t rm 0.610 0.619 input setup time (ti to ckn) t su 0.345 0.344 input hold time (ti to ckn) t hd 0.073 0.072 input setup time (te to ckn) t su 0.361 0.362 input hold time (te to ckn) t hd 0.099 0.094 q qn d ti te ckn rn clbn cln cln clbn cln clbn cln clbn te teb te rn rn rn qn q ckn d te ti teb cln clbn rn truth table d ti te ckn rn q (n+1) qn (n+1) 0x0 101 1x0 110 x01 101 x11 110 xxxx001 x x x 1 q (n) qn (n)
STD111 3-360 samsung asic fd6s/fd6sd2 d flip-flop with negative edge trigger, reset, scan, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd6s fd6sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t r 0.116 0.061 + 0.027*sl 0.061 + 0.028*sl 0.055 + 0.028*sl t f 0.098 0.051 + 0.023*sl 0.052 + 0.023*sl 0.046 + 0.024*sl t plh 0.343 0.313 + 0.015*sl 0.320 + 0.013*sl 0.327 + 0.013*sl t phl 0.300 0.270 + 0.015*sl 0.277 + 0.013*sl 0.284 + 0.013*sl rn to q t f 0.101 0.055 + 0.023*sl 0.053 + 0.023*sl 0.050 + 0.024*sl t phl 0.169 0.138 + 0.016*sl 0.146 + 0.013*sl 0.153 + 0.013*sl ckn to qn t r 0.102 0.049 + 0.027*sl 0.044 + 0.028*sl 0.039 + 0.028*sl t f 0.092 0.046 + 0.023*sl 0.044 + 0.023*sl 0.038 + 0.024*sl t plh 0.353 0.326 + 0.014*sl 0.330 + 0.012*sl 0.331 + 0.012*sl t phl 0.402 0.372 + 0.015*sl 0.379 + 0.013*sl 0.382 + 0.013*sl rn to qn t r 0.114 0.056 + 0.029*sl 0.060 + 0.028*sl 0.059 + 0.028*sl t plh 0.244 0.213 + 0.015*sl 0.219 + 0.014*sl 0.229 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t r 0.089 0.061 + 0.014*sl 0.064 + 0.013*sl 0.057 + 0.014*sl t f 0.077 0.053 + 0.012*sl 0.053 + 0.012*sl 0.051 + 0.012*sl t plh 0.349 0.331 + 0.009*sl 0.338 + 0.007*sl 0.350 + 0.006*sl t phl 0.304 0.285 + 0.009*sl 0.293 + 0.007*sl 0.307 + 0.007*sl rn to q t f 0.079 0.053 + 0.013*sl 0.057 + 0.012*sl 0.056 + 0.012*sl t phl 0.170 0.151 + 0.010*sl 0.160 + 0.007*sl 0.173 + 0.007*sl ckn to qn t r 0.078 0.052 + 0.013*sl 0.051 + 0.013*sl 0.040 + 0.014*sl t f 0.073 0.050 + 0.012*sl 0.050 + 0.012*sl 0.043 + 0.012*sl t plh 0.392 0.376 + 0.008*sl 0.382 + 0.007*sl 0.388 + 0.006*sl t phl 0.438 0.420 + 0.009*sl 0.428 + 0.007*sl 0.438 + 0.006*sl rn to qn t r 0.089 0.060 + 0.014*sl 0.062 + 0.014*sl 0.060 + 0.014*sl t plh 0.282 0.264 + 0.009*sl 0.270 + 0.007*sl 0.283 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-361 STD111 fd7/fd7d2 d flip-flop with negative edge trigger, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd7 fd7d2 fd7 fd7d2 d ckn sn d ckn sn 0.7 0.7 1.7 0.7 0.7 1.7 5.67 6.00 parameter symbol value (ns) fd7 fd7d2 input setup time (d to ckn) t su 0.213 0.214 input hold time (d to ckn) t hd 0.142 0.143 pulse width low (ckn) t pwl 0.237 0.253 pulse width high (ckn) t pwh 0.237 0.253 pulse width low (sn) t pwl 0.256 0.254 recovery time (sn to ckn) t rc 0.046 0.047 removal time (sn to ckn) t rm 0.182 0.181 d ckn q qn sn cln clbn cln clbn clbn cln d ckn cln clbn clbn cln sn sn sn qn q sn truth table d ckn sn q (n+1) qn (n+1) 0 101 1 110 xx010 x 1 q (n) qn (n)
STD111 3-362 samsung asic fd7/fd7d2 d flip-flop with negative edge trigger, set, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd7 fd7d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t r 0.110 0.057 + 0.026*sl 0.053 + 0.028*sl 0.046 + 0.028*sl t f 0.099 0.052 + 0.024*sl 0.053 + 0.024*sl 0.049 + 0.024*sl t plh 0.333 0.304 + 0.014*sl 0.310 + 0.013*sl 0.313 + 0.012*sl t phl 0.306 0.275 + 0.016*sl 0.282 + 0.014*sl 0.290 + 0.013*sl sn to q t r 0.119 0.068 + 0.025*sl 0.062 + 0.027*sl 0.051 + 0.028*sl t plh 0.365 0.336 + 0.015*sl 0.343 + 0.013*sl 0.347 + 0.012*sl ckn to qn t r 0.109 0.055 + 0.027*sl 0.052 + 0.028*sl 0.046 + 0.028*sl t f 0.092 0.043 + 0.024*sl 0.046 + 0.023*sl 0.039 + 0.024*sl t plh 0.374 0.345 + 0.015*sl 0.352 + 0.013*sl 0.356 + 0.012*sl t phl 0.404 0.373 + 0.015*sl 0.381 + 0.013*sl 0.385 + 0.013*sl sn to qn t f 0.105 0.056 + 0.025*sl 0.059 + 0.024*sl 0.058 + 0.024*sl t phl 0.178 0.145 + 0.016*sl 0.154 + 0.014*sl 0.163 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t r 0.085 0.059 + 0.013*sl 0.059 + 0.013*sl 0.049 + 0.014*sl t f 0.078 0.053 + 0.012*sl 0.055 + 0.012*sl 0.052 + 0.012*sl t plh 0.340 0.323 + 0.009*sl 0.330 + 0.007*sl 0.338 + 0.006*sl t phl 0.307 0.288 + 0.010*sl 0.296 + 0.007*sl 0.309 + 0.007*sl sn to q t r 0.098 0.074 + 0.012*sl 0.069 + 0.013*sl 0.058 + 0.014*sl t plh 0.405 0.387 + 0.009*sl 0.395 + 0.007*sl 0.406 + 0.006*sl ckn to qn t r 0.084 0.056 + 0.014*sl 0.056 + 0.014*sl 0.050 + 0.014*sl t f 0.073 0.049 + 0.012*sl 0.051 + 0.012*sl 0.046 + 0.012*sl t plh 0.408 0.390 + 0.009*sl 0.397 + 0.007*sl 0.408 + 0.006*sl t phl 0.439 0.420 + 0.009*sl 0.428 + 0.007*sl 0.439 + 0.006*sl sn to qn t f 0.084 0.058 + 0.013*sl 0.062 + 0.012*sl 0.061 + 0.012*sl t phl 0.178 0.158 + 0.010*sl 0.167 + 0.008*sl 0.182 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-363 STD111 fd7s/fd7sd2 d flip-flop with negative edge trigger, set, scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd7s fd7sd2 fd7s fd7sd2 d ckn sn ti te d ckn sn ti te 0.6 0.7 1.7 0.7 1.4 0.6 0.7 1.7 0.7 1.4 7.33 7.33 parameter symbol value (ns) fd7s fd7sd2 input setup time (d to ckn) t su 0.376 0.377 input hold time (d to ckn) t hd 0.090 0.089 pulse width low (ckn) t pwl 0.237 0.256 pulse width high (ckn) t pwh 0.237 0.256 pulse width low (sn) t pwl 0.257 0.257 recovery time (sn to ckn) t rc 0.041 0.044 removal time (sn to ckn) t rm 0.189 0.186 input setup time (ti to ckn) t su 0.358 0.359 input hold time (ti to ckn) t hd 0.082 0.080 input setup time (te to ckn) t su 0.376 0.377 input hold time (te to ckn) t hd 0.106 0.106 q qn d ti te ckn sn clbn cln qn cln clbn cln clbn q ckn cln clbn te teb te sn sn sn d te ti teb cln clbn sn truth table d ti te ckn sn q (n+1) qn (n+1) 0x0 101 1x0 110 x01 101 x11 110 xxxx010 x x x 1 q (n) qn (n)
STD111 3-364 samsung asic fd7s/fd7sd2 d flip-flop with negative edge trigger, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd7s fd7sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t r 0.110 0.057 + 0.026*sl 0.053 + 0.027*sl 0.046 + 0.028*sl t f 0.098 0.051 + 0.024*sl 0.054 + 0.023*sl 0.048 + 0.023*sl t plh 0.334 0.306 + 0.014*sl 0.312 + 0.013*sl 0.315 + 0.012*sl t phl 0.307 0.276 + 0.015*sl 0.284 + 0.013*sl 0.291 + 0.013*sl sn to q t r 0.119 0.068 + 0.025*sl 0.063 + 0.027*sl 0.052 + 0.028*sl t plh 0.364 0.335 + 0.015*sl 0.343 + 0.013*sl 0.346 + 0.012*sl ckn to qn t r 0.110 0.057 + 0.027*sl 0.054 + 0.027*sl 0.047 + 0.028*sl t f 0.092 0.045 + 0.024*sl 0.048 + 0.023*sl 0.041 + 0.024*sl t plh 0.377 0.348 + 0.014*sl 0.355 + 0.013*sl 0.359 + 0.012*sl t phl 0.407 0.377 + 0.015*sl 0.385 + 0.013*sl 0.389 + 0.012*sl sn to qn t f 0.105 0.057 + 0.024*sl 0.060 + 0.023*sl 0.059 + 0.023*sl t phl 0.179 0.147 + 0.016*sl 0.155 + 0.014*sl 0.164 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t r 0.087 0.061 + 0.013*sl 0.059 + 0.013*sl 0.049 + 0.014*sl t f 0.079 0.054 + 0.012*sl 0.057 + 0.012*sl 0.054 + 0.012*sl t plh 0.345 0.328 + 0.009*sl 0.335 + 0.007*sl 0.344 + 0.006*sl t phl 0.314 0.295 + 0.010*sl 0.304 + 0.007*sl 0.317 + 0.007*sl sn to q t r 0.099 0.074 + 0.012*sl 0.071 + 0.013*sl 0.059 + 0.014*sl t plh 0.409 0.391 + 0.009*sl 0.399 + 0.007*sl 0.411 + 0.006*sl ckn to qn t r 0.085 0.057 + 0.014*sl 0.058 + 0.014*sl 0.050 + 0.014*sl t f 0.073 0.047 + 0.013*sl 0.052 + 0.012*sl 0.046 + 0.012*sl t plh 0.416 0.398 + 0.009*sl 0.405 + 0.007*sl 0.416 + 0.006*sl t phl 0.446 0.427 + 0.009*sl 0.435 + 0.007*sl 0.447 + 0.006*sl sn to qn t f 0.083 0.057 + 0.013*sl 0.061 + 0.012*sl 0.060 + 0.012*sl t phl 0.177 0.157 + 0.010*sl 0.165 + 0.008*sl 0.181 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-365 STD111 fd8/fd8d2 d flip-flop with negative edge trigger, reset, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fd8 fd8d2 fd8 fd8d2 d ckn rn sn d ckn rn sn 0.7 0.7 1.4 1.7 0.7 0.7 1.4 1.7 6.00 6.33 parameter symbol value (ns) fd8 fd8d2 input setup time (d to ckn) t su 0.206 0.206 input hold time (d to ckn) t hd 0.139 0.139 pulse width low (ckn) t pwl 0.253 0.267 pulse width high (ckn) t pwh 0.253 0.267 pulse width low (rn) t pwl 0.508 0.508 pulse width low (sn) t pwl 0.298 0.297 recovery time (rn to ckn) t rc 0.000 0.000 removal time (rn to ckn) t rm 0.632 0.632 recovery time (sn to ckn) t rc 0.026 0.026 removal time (sn to ckn) t rm 0.222 0.221 recovery time (sn to rn) t rc 0.083 0.084 removal time (sn to rn) t rm 0.137 0.136 d ckn q qn rn sn d ckn clbn cln q cln clbn clbn cln clbn clbn cln qn cln sn sn rn rn rn rn sn sn truth table d ckn rn sn q (n+1) qn (n+1) 01101 11110 xx1010 xx0101 xx0000 x 1 1 q (n) qn (n)
STD111 3-366 samsung asic fd8/fd8d2 d flip-flop with negative edge trigger, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t r 0.118 0.063 + 0.028*sl 0.063 + 0.027*sl 0.056 + 0.028*sl t f 0.103 0.055 + 0.024*sl 0.057 + 0.023*sl 0.053 + 0.024*sl t plh 0.357 0.326 + 0.015*sl 0.334 + 0.013*sl 0.341 + 0.013*sl t phl 0.331 0.299 + 0.016*sl 0.308 + 0.014*sl 0.317 + 0.013*sl rn to q t r 0.114 0.059 + 0.027*sl 0.059 + 0.027*sl 0.052 + 0.028*sl t f 0.104 0.057 + 0.024*sl 0.057 + 0.024*sl 0.052 + 0.024*sl t plh 0.148 0.118 + 0.015*sl 0.125 + 0.013*sl 0.130 + 0.012*sl t phl 0.174 0.142 + 0.016*sl 0.151 + 0.014*sl 0.158 + 0.013*sl sn to q t r 0.126 0.074 + 0.026*sl 0.070 + 0.027*sl 0.062 + 0.028*sl t plh 0.385 0.354 + 0.016*sl 0.363 + 0.013*sl 0.370 + 0.012*sl ckn to qn t r 0.109 0.056 + 0.027*sl 0.053 + 0.028*sl 0.047 + 0.028*sl t f 0.096 0.049 + 0.023*sl 0.049 + 0.023*sl 0.041 + 0.024*sl t plh 0.401 0.372 + 0.015*sl 0.379 + 0.013*sl 0.383 + 0.012*sl t phl 0.430 0.400 + 0.015*sl 0.408 + 0.013*sl 0.412 + 0.013*sl rn to qn t r 0.123 0.064 + 0.029*sl 0.068 + 0.028*sl 0.072 + 0.028*sl t plh 0.267 0.234 + 0.017*sl 0.242 + 0.015*sl 0.256 + 0.013*sl sn to qn t r 0.121 0.063 + 0.029*sl 0.066 + 0.028*sl 0.068 + 0.028*sl t f 0.107 0.056 + 0.025*sl 0.061 + 0.024*sl 0.059 + 0.024*sl t plh 0.152 0.119 + 0.016*sl 0.127 + 0.014*sl 0.140 + 0.013*sl t phl 0.181 0.148 + 0.017*sl 0.156 + 0.014*sl 0.166 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-367 STD111 fd8/fd8d2 d flip-flop with negative edge trigger, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t r 0.094 0.067 + 0.013*sl 0.066 + 0.014*sl 0.060 + 0.014*sl t f 0.082 0.059 + 0.012*sl 0.058 + 0.012*sl 0.058 + 0.012*sl t plh 0.362 0.343 + 0.009*sl 0.351 + 0.007*sl 0.364 + 0.006*sl t phl 0.333 0.314 + 0.010*sl 0.323 + 0.007*sl 0.337 + 0.007*sl rn to q t r 0.089 0.062 + 0.014*sl 0.062 + 0.014*sl 0.056 + 0.014*sl t f 0.081 0.055 + 0.013*sl 0.060 + 0.012*sl 0.058 + 0.012*sl t plh 0.152 0.134 + 0.009*sl 0.141 + 0.007*sl 0.153 + 0.006*sl t phl 0.173 0.153 + 0.010*sl 0.162 + 0.007*sl 0.176 + 0.007*sl sn to q t r 0.103 0.076 + 0.014*sl 0.078 + 0.013*sl 0.066 + 0.014*sl t plh 0.421 0.402 + 0.009*sl 0.411 + 0.007*sl 0.425 + 0.006*sl ckn to qn t r 0.085 0.058 + 0.013*sl 0.057 + 0.014*sl 0.051 + 0.014*sl t f 0.076 0.052 + 0.012*sl 0.055 + 0.011*sl 0.048 + 0.012*sl t plh 0.437 0.420 + 0.009*sl 0.427 + 0.007*sl 0.437 + 0.006*sl t phl 0.465 0.447 + 0.009*sl 0.454 + 0.007*sl 0.467 + 0.006*sl rn to qn t r 0.097 0.069 + 0.014*sl 0.068 + 0.014*sl 0.074 + 0.014*sl t plh 0.299 0.279 + 0.010*sl 0.287 + 0.008*sl 0.305 + 0.007*sl sn to qn t r 0.093 0.064 + 0.015*sl 0.065 + 0.014*sl 0.070 + 0.014*sl t f 0.084 0.058 + 0.013*sl 0.063 + 0.012*sl 0.063 + 0.012*sl t plh 0.154 0.135 + 0.010*sl 0.142 + 0.008*sl 0.159 + 0.007*sl t phl 0.179 0.159 + 0.010*sl 0.169 + 0.008*sl 0.185 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-368 samsung asic fd8s/fd8sd2 d flip-flop with negative edge trigger, reset, set, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count fd8s fd8sd2 fd8s fd8sd2 d ckn rn sn ti te d ckn rn sn ti te 0.6 0.7 1.4 1.7 0.7 1.4 0.6 0.7 1.4 1.7 0.7 1.4 7.67 8.00 q qn d ti te ckn rn sn clbn cln cln clbn cln clbn clbn cln ckn cln clbn te teb te sn rn rn sn q qn d te ti teb sn sn rn rn truth table d ti te ckn rn sn q (n+1) qn (n+1) 0x0 11 0 1 1x0 11 1 0 x01 11 0 1 x11 11 1 0 xxxx10 1 0 xxxx01 0 1 xxxx00 0 0 x x x 1 1 q (n) qn (n)
samsung asic 3-369 STD111 fd8s/fd8sd2 d flip-flop with negative edge trigger, reset, set, scan, 1x/2x drive timing requirements (typical process, 25 c, 2.5v, unit = ns) parameter symbol value (ns) fd8s fd8sd2 input setup time (d to ckn) t su 0.366 0.367 input hold time (d to ckn) t hd 0.086 0.086 pulse width low (ckn) t pwl 0.254 0.267 pulse width high (ckn) t pwh 0.254 0.267 pulse width low (rn) t pwl 0.509 0.509 pulse width low (sn) t pwl 0.299 0.298 recovery time (rn to ckn) t rc 0.000 0.000 removal time (rn to ckn) t rm 0.636 0.635 recovery time (sn to ckn) t rc 0.026 0.026 removal time (sn to ckn) t rm 0.224 0.224 input setup time (ti to ckn) t su 0.349 0.350 input hold time (ti to ckn) t hd 0.077 0.077 input setup time (te to ckn) t su 0.366 0.366 input hold time (te to ckn) t hd 0.103 0.103 recovery time (sn to rn) t rc 0.082 0.084 removal time (sn to rn) t rm 0.138 0.136
STD111 3-370 samsung asic fd8s/fd8sd2 d flip-flop with negative edge trigger, reset, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd8s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t r 0.118 0.064 + 0.027*sl 0.062 + 0.028*sl 0.057 + 0.028*sl t f 0.103 0.055 + 0.024*sl 0.058 + 0.023*sl 0.053 + 0.024*sl t plh 0.359 0.329 + 0.015*sl 0.336 + 0.013*sl 0.343 + 0.013*sl t phl 0.333 0.301 + 0.016*sl 0.309 + 0.014*sl 0.319 + 0.013*sl rn to q t r 0.114 0.059 + 0.027*sl 0.059 + 0.027*sl 0.052 + 0.028*sl t f 0.104 0.057 + 0.024*sl 0.056 + 0.024*sl 0.052 + 0.024*sl t plh 0.148 0.118 + 0.015*sl 0.125 + 0.013*sl 0.130 + 0.012*sl t phl 0.174 0.142 + 0.016*sl 0.151 + 0.014*sl 0.158 + 0.013*sl sn to q t r 0.126 0.074 + 0.026*sl 0.070 + 0.027*sl 0.062 + 0.028*sl t plh 0.385 0.354 + 0.016*sl 0.363 + 0.013*sl 0.370 + 0.012*sl ckn to qn t r 0.109 0.055 + 0.027*sl 0.053 + 0.028*sl 0.046 + 0.028*sl t f 0.095 0.049 + 0.023*sl 0.046 + 0.024*sl 0.041 + 0.024*sl t plh 0.403 0.374 + 0.015*sl 0.381 + 0.013*sl 0.385 + 0.012*sl t phl 0.433 0.402 + 0.015*sl 0.410 + 0.013*sl 0.415 + 0.013*sl rn to qn t r 0.123 0.064 + 0.029*sl 0.068 + 0.028*sl 0.072 + 0.028*sl t plh 0.267 0.233 + 0.017*sl 0.242 + 0.015*sl 0.256 + 0.013*sl sn to qn t r 0.121 0.063 + 0.029*sl 0.066 + 0.028*sl 0.068 + 0.028*sl t f 0.106 0.056 + 0.025*sl 0.061 + 0.024*sl 0.059 + 0.024*sl t plh 0.152 0.119 + 0.016*sl 0.127 + 0.014*sl 0.140 + 0.013*sl t phl 0.181 0.148 + 0.017*sl 0.156 + 0.014*sl 0.166 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-371 STD111 fd8s/fd8sd2 d flip-flop with negative edge trigger, reset, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fd8sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t r 0.094 0.067 + 0.013*sl 0.066 + 0.014*sl 0.060 + 0.014*sl t f 0.082 0.059 + 0.011*sl 0.058 + 0.012*sl 0.058 + 0.012*sl t plh 0.365 0.346 + 0.009*sl 0.354 + 0.007*sl 0.367 + 0.006*sl t phl 0.336 0.317 + 0.010*sl 0.325 + 0.007*sl 0.339 + 0.007*sl rn to q t r 0.089 0.061 + 0.014*sl 0.062 + 0.014*sl 0.056 + 0.014*sl t f 0.081 0.055 + 0.013*sl 0.060 + 0.012*sl 0.058 + 0.012*sl t plh 0.152 0.134 + 0.009*sl 0.141 + 0.007*sl 0.153 + 0.006*sl t phl 0.173 0.153 + 0.010*sl 0.162 + 0.007*sl 0.176 + 0.007*sl sn to q t r 0.103 0.076 + 0.014*sl 0.078 + 0.013*sl 0.066 + 0.014*sl t plh 0.421 0.402 + 0.009*sl 0.411 + 0.007*sl 0.425 + 0.006*sl ckn to qn t r 0.085 0.058 + 0.014*sl 0.059 + 0.013*sl 0.051 + 0.014*sl t f 0.076 0.052 + 0.012*sl 0.055 + 0.011*sl 0.048 + 0.012*sl t plh 0.439 0.422 + 0.009*sl 0.429 + 0.007*sl 0.440 + 0.006*sl t phl 0.468 0.449 + 0.009*sl 0.457 + 0.007*sl 0.470 + 0.006*sl rn to qn t r 0.097 0.069 + 0.014*sl 0.068 + 0.014*sl 0.074 + 0.014*sl t plh 0.299 0.279 + 0.010*sl 0.287 + 0.008*sl 0.305 + 0.007*sl sn to qn t r 0.093 0.063 + 0.015*sl 0.065 + 0.014*sl 0.070 + 0.014*sl t f 0.084 0.058 + 0.013*sl 0.063 + 0.012*sl 0.063 + 0.012*sl t plh 0.154 0.135 + 0.010*sl 0.142 + 0.008*sl 0.159 + 0.007*sl t phl 0.179 0.159 + 0.010*sl 0.169 + 0.008*sl 0.185 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-372 samsung asic fds2/fds2d2 d flip-flop with synchronous clear, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fds2 fds2d2 fds2 fds2d2 d crn ck d crn ck 0.6 0.6 0.7 0.6 0.6 0.7 5.33 5.33 parameter symbol value (ns) fds2 fds2d2 input setup time (d to ck) t su 0.240 0.235 input hold time (d to ck) t hd 0.100 0.111 pulse width low (ck) t pwl 0.272 0.274 pulse width high (ck) t pwh 0.244 0.268 input setup time (crn to ck) t su 0.238 0.233 input hold time (crn to ck) t hd 0.097 0.106 d crn ck q qn d ck cl clb q cl clb clb cl clb cl cl clb qn crn truth table d crn ck q (n+1) qn (n+1) 01 01 11 10 x0 01 x x q (n) qn (n)
samsung asic 3-373 STD111 fds2/fds2d2 d flip-flop with synchronous clear, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fds2 fds2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.109 0.056 + 0.027*sl 0.052 + 0.028*sl 0.045 + 0.028*sl t f 0.095 0.047 + 0.024*sl 0.050 + 0.023*sl 0.044 + 0.024*sl t plh 0.305 0.277 + 0.014*sl 0.282 + 0.013*sl 0.286 + 0.012*sl t phl 0.304 0.273 + 0.015*sl 0.280 + 0.013*sl 0.287 + 0.013*sl ck to qn t r 0.101 0.048 + 0.027*sl 0.042 + 0.028*sl 0.037 + 0.029*sl t f 0.090 0.043 + 0.023*sl 0.042 + 0.024*sl 0.035 + 0.024*sl t plh 0.354 0.327 + 0.013*sl 0.331 + 0.012*sl 0.332 + 0.012*sl t phl 0.361 0.332 + 0.015*sl 0.338 + 0.013*sl 0.341 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.085 0.058 + 0.013*sl 0.058 + 0.013*sl 0.047 + 0.014*sl t f 0.075 0.050 + 0.012*sl 0.052 + 0.012*sl 0.048 + 0.012*sl t plh 0.326 0.309 + 0.009*sl 0.316 + 0.007*sl 0.324 + 0.006*sl t phl 0.310 0.292 + 0.009*sl 0.300 + 0.007*sl 0.312 + 0.006*sl ck to qn t r 0.078 0.052 + 0.013*sl 0.051 + 0.013*sl 0.039 + 0.014*sl t f 0.071 0.046 + 0.013*sl 0.049 + 0.012*sl 0.041 + 0.012*sl t plh 0.397 0.381 + 0.008*sl 0.386 + 0.007*sl 0.392 + 0.006*sl t phl 0.412 0.394 + 0.009*sl 0.401 + 0.007*sl 0.410 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-374 samsung asic fds2cs/fds2csd2 d flip-flop with synchronous clear, scan clock, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fds2cs fds2csd2 fds2cs fds2csd2 d si ck sck crn d si ck sck crn 0.6 0.6 0.7 1.5 0.6 0.6 0.6 0.8 1.5 0.6 7.67 8.00 parameter symbol value (ns) fds2cs fds2csd2 input setup time (d to ck) t su 0.241 0.238 input hold time (d to ck) t hd 0.101 0.107 input setup time (si to sck) t su 0.290 0.290 input hold time (si to sck) t hd 0.056 0.056 pulse width low (ck) t pwl 0.272 0.273 pulse width high (ck) t pwh 0.249 0.268 pulse width low (sck) t pwl 0.218 0.219 pulse width high (sck) t pwh 0.304 0.339 input setup time (crn to ck) t su 0.238 0.236 input hold time (crn to ck) t hd 0.097 0.102 q qn si crn ck sck d d cl clb q clb cl clb cl cl clb qn crn sck sckb sck sckb sckb sck sckb sck si cl clb sck sck sckb ck truth table si sck d crn ck q (n+1) qn (n+1) x001 0 1 x011 1 0 0xx001 1xx010 x0x0 0 1 x 0 x x q(n) qn(n) x x x 0 q(n) qn(n)
samsung asic 3-375 STD111 fds2cs/fds2csd2 d flip-flop with synchronous clear, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fds2cs fds2csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.109 0.056 + 0.026*sl 0.053 + 0.027*sl 0.045 + 0.028*sl t f 0.098 0.051 + 0.024*sl 0.051 + 0.024*sl 0.045 + 0.024*sl t plh 0.307 0.279 + 0.014*sl 0.285 + 0.013*sl 0.288 + 0.012*sl t phl 0.309 0.278 + 0.016*sl 0.287 + 0.013*sl 0.292 + 0.013*sl sck to q t r 0.126 0.075 + 0.025*sl 0.071 + 0.026*sl 0.060 + 0.028*sl t f 0.104 0.057 + 0.023*sl 0.057 + 0.023*sl 0.050 + 0.024*sl t plh 0.393 0.362 + 0.015*sl 0.371 + 0.013*sl 0.377 + 0.012*sl t phl 0.321 0.289 + 0.016*sl 0.298 + 0.014*sl 0.305 + 0.013*sl ck to qn t r 0.110 0.053 + 0.028*sl 0.056 + 0.028*sl 0.052 + 0.028*sl t f 0.097 0.049 + 0.024*sl 0.049 + 0.024*sl 0.047 + 0.024*sl t plh 0.372 0.343 + 0.015*sl 0.349 + 0.013*sl 0.357 + 0.012*sl t phl 0.380 0.348 + 0.016*sl 0.357 + 0.014*sl 0.362 + 0.013*sl sck to qn t r 0.101 0.049 + 0.026*sl 0.043 + 0.028*sl 0.038 + 0.028*sl t f 0.092 0.045 + 0.023*sl 0.044 + 0.024*sl 0.037 + 0.024*sl t plh 0.373 0.346 + 0.013*sl 0.350 + 0.012*sl 0.351 + 0.012*sl t phl 0.452 0.422 + 0.015*sl 0.428 + 0.013*sl 0.431 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.085 0.058 + 0.014*sl 0.058 + 0.013*sl 0.049 + 0.014*sl t f 0.077 0.051 + 0.013*sl 0.055 + 0.012*sl 0.051 + 0.012*sl t plh 0.318 0.301 + 0.009*sl 0.308 + 0.007*sl 0.316 + 0.006*sl t phl 0.315 0.295 + 0.010*sl 0.304 + 0.007*sl 0.317 + 0.007*sl sck to q t r 0.105 0.080 + 0.013*sl 0.078 + 0.013*sl 0.066 + 0.014*sl t f 0.083 0.059 + 0.012*sl 0.061 + 0.012*sl 0.057 + 0.012*sl t plh 0.411 0.392 + 0.010*sl 0.401 + 0.007*sl 0.413 + 0.006*sl t phl 0.331 0.312 + 0.010*sl 0.320 + 0.007*sl 0.335 + 0.007*sl ck to qn t r 0.087 0.058 + 0.014*sl 0.060 + 0.014*sl 0.055 + 0.014*sl t f 0.078 0.053 + 0.012*sl 0.054 + 0.012*sl 0.052 + 0.012*sl t plh 0.416 0.398 + 0.009*sl 0.404 + 0.007*sl 0.417 + 0.006*sl t phl 0.422 0.403 + 0.009*sl 0.411 + 0.007*sl 0.422 + 0.007*sl sck to qn t r 0.079 0.053 + 0.013*sl 0.051 + 0.014*sl 0.040 + 0.014*sl t f 0.073 0.048 + 0.012*sl 0.051 + 0.012*sl 0.043 + 0.012*sl t plh 0.422 0.406 + 0.008*sl 0.411 + 0.007*sl 0.417 + 0.006*sl t phl 0.504 0.486 + 0.009*sl 0.494 + 0.007*sl 0.503 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-376 samsung asic fds2s/fds2sd2 d flip-flop with synchronous clear, scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fds2s fds2sd2 fds2s fds2sd2 d crn ck ti te d crn ck ti te 0.6 0.7 0.7 0.6 1.4 0.7 0.6 0.7 0.7 1.4 7.67 8.00 parameter symbol value (ns) fds2s fds2sd2 input setup time (d to ck) t su 0.338 0.343 input hold time (d to ck) t hd 0.000 0.000 input setup time (crn to ck) t su 0.339 0.343 input hold time (crn to ck) t hd 0.000 0.000 pulse width low (ck) t pwl 0.316 0.319 pulse width high (ck) t pwh 0.246 0.259 input setup time (ti to ck) t su 0.375 0.377 input hold time (ti to ck) t hd 0.000 0.000 input setup time (te to ck) t su 0.315 0.315 input hold time (te to ck) t hd 0.018 0.016 q qn d te ck crn ti qn q cl clb cl clb clb cl crn cl ck clb d ti teb te te te teb cl clb truth table d crn ti te ck q (n+1) qn (n+1) 01x0 01 11x0 10 x0x0 01 xx01 01 xx11 10 x x x x q (n) qn (n)
samsung asic 3-377 STD111 fds2s/fds2sd2 d flip-flop with synchronous clear, scan, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fds2s fds2sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.101 0.047 + 0.027*sl 0.043 + 0.028*sl 0.038 + 0.029*sl t f 0.090 0.042 + 0.024*sl 0.043 + 0.024*sl 0.035 + 0.024*sl t plh 0.362 0.335 + 0.014*sl 0.339 + 0.012*sl 0.340 + 0.012*sl t phl 0.365 0.336 + 0.015*sl 0.342 + 0.013*sl 0.345 + 0.013*sl ck to qn t r 0.109 0.055 + 0.027*sl 0.052 + 0.028*sl 0.046 + 0.028*sl t f 0.097 0.049 + 0.024*sl 0.052 + 0.023*sl 0.045 + 0.024*sl t plh 0.308 0.279 + 0.014*sl 0.285 + 0.013*sl 0.288 + 0.012*sl t phl 0.311 0.280 + 0.015*sl 0.288 + 0.013*sl 0.294 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.078 0.051 + 0.013*sl 0.051 + 0.013*sl 0.039 + 0.014*sl t f 0.071 0.047 + 0.012*sl 0.048 + 0.012*sl 0.041 + 0.012*sl t plh 0.395 0.379 + 0.008*sl 0.385 + 0.007*sl 0.390 + 0.006*sl t phl 0.397 0.380 + 0.009*sl 0.387 + 0.007*sl 0.396 + 0.006*sl ck to qn t r 0.083 0.056 + 0.014*sl 0.056 + 0.013*sl 0.046 + 0.014*sl t f 0.074 0.049 + 0.013*sl 0.053 + 0.012*sl 0.049 + 0.012*sl t plh 0.312 0.294 + 0.009*sl 0.301 + 0.007*sl 0.309 + 0.006*sl t phl 0.309 0.290 + 0.009*sl 0.298 + 0.007*sl 0.311 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-378 samsung asic fds3/fds3d2 d flip-flop with synchronous set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fds3 fds3d2 fds3 fds3d2 d csn ck d csn ck 0.7 0.6 0.7 0.7 0.6 0.7 5.67 6.00 parameter symbol value (ns) fds3 fds3d2 input setup time (d to ck) t su 0.297 0.293 input hold time (d to ck) t hd 0.052 0.057 input setup time (csn to ck) t su 0.238 0.234 input hold time (csn to ck) t hd 0.100 0.105 pulse width low (ck) t pwl 0.276 0.277 pulse width high (ck) t pwh 0.247 0.265 d csn ck q qn cl clb q clb cl clb cl qn d ck cl clb csn cl clb truth table d csn ck q (n+1) qn (n+1) 01 01 11 10 x0 10 x x q (n) qn (n)
samsung asic 3-379 STD111 fds3/fds3d2 d flip-flop with synchronous set, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fds3 fds3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.101 0.048 + 0.026*sl 0.042 + 0.028*sl 0.037 + 0.029*sl t f 0.089 0.041 + 0.024*sl 0.043 + 0.024*sl 0.035 + 0.024*sl t plh 0.360 0.333 + 0.014*sl 0.337 + 0.013*sl 0.338 + 0.012*sl t phl 0.366 0.337 + 0.014*sl 0.342 + 0.013*sl 0.345 + 0.013*sl ck to qn t r 0.109 0.055 + 0.027*sl 0.053 + 0.028*sl 0.046 + 0.028*sl t f 0.097 0.049 + 0.024*sl 0.051 + 0.023*sl 0.045 + 0.024*sl t plh 0.308 0.280 + 0.014*sl 0.285 + 0.013*sl 0.289 + 0.012*sl t phl 0.308 0.277 + 0.016*sl 0.284 + 0.013*sl 0.291 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.078 0.052 + 0.013*sl 0.051 + 0.014*sl 0.040 + 0.014*sl t f 0.070 0.047 + 0.012*sl 0.048 + 0.012*sl 0.041 + 0.012*sl t plh 0.398 0.382 + 0.008*sl 0.387 + 0.007*sl 0.393 + 0.006*sl t phl 0.406 0.389 + 0.009*sl 0.396 + 0.007*sl 0.405 + 0.006*sl ck to qn t r 0.083 0.057 + 0.013*sl 0.056 + 0.013*sl 0.045 + 0.014*sl t f 0.075 0.050 + 0.013*sl 0.053 + 0.012*sl 0.049 + 0.012*sl t plh 0.322 0.305 + 0.008*sl 0.311 + 0.007*sl 0.319 + 0.006*sl t phl 0.312 0.293 + 0.009*sl 0.301 + 0.007*sl 0.313 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-380 samsung asic fds3cs/fds3csd2 d flip-flop with synchronous set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c,2.5v, unit = ns) input load (sl) gate count fds3cs fds3csd2 fds3cs fds3csd2 d si ck sck csn d si ck sck csn 0.7 0.7 0.8 1.8 0.6 0.7 0.7 0.7 1.7 0.7 8.67 9.00 parameter symbol value (ns) fds3cs fds3csd2 input setup time (d to ck) t su 0.299 0.300 input hold time (d to ck) t hd 0.045 0.047 input setup time (si to sck) t su 0.343 0.342 input hold time (si to sck) t hd 0.003 0.003 pulse width low (ck) t pwl 0.278 0.276 pulse width high (ck) t pwh 0.250 0.266 pulse width low (sck) t pwl 0.222 0.221 pulse width high (sck) t pwh 0.309 0.339 input setup time (csn to ck) t su 0.240 0.239 input hold time (csn to ck) t hd 0.096 0.097 q qn si csn ck sck d cl clb qn clb cl clb cl q d ck cl clb csn cl clb sck sckb sck sckb sckb sck sckb sck si sck sck sckb truth table si sck d csn ck q(n+1) qn(n+1) x001 0 1 x011 1 0 0xx001 1xx010 x0x0 1 0 x 0 x x q(n) qn(n) x x x 0 q(n) qn(n)
samsung asic 3-381 STD111 fds3cs/fds3csd2 d flip-flop with synchronous set, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fds3cs fds3csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.111 0.055 + 0.028*sl 0.056 + 0.028*sl 0.053 + 0.028*sl t f 0.097 0.049 + 0.024*sl 0.049 + 0.024*sl 0.048 + 0.024*sl t plh 0.375 0.345 + 0.015*sl 0.351 + 0.013*sl 0.360 + 0.012*sl t phl 0.384 0.353 + 0.015*sl 0.360 + 0.013*sl 0.366 + 0.013*sl sck to q t r 0.102 0.050 + 0.026*sl 0.044 + 0.028*sl 0.039 + 0.028*sl t f 0.092 0.048 + 0.022*sl 0.042 + 0.023*sl 0.038 + 0.024*sl t plh 0.387 0.360 + 0.013*sl 0.364 + 0.012*sl 0.365 + 0.012*sl t phl 0.458 0.429 + 0.014*sl 0.436 + 0.013*sl 0.438 + 0.013*sl ck to qn t r 0.109 0.056 + 0.027*sl 0.053 + 0.027*sl 0.046 + 0.028*sl t f 0.098 0.052 + 0.023*sl 0.051 + 0.023*sl 0.046 + 0.024*sl t plh 0.309 0.281 + 0.014*sl 0.287 + 0.013*sl 0.290 + 0.012*sl t phl 0.309 0.278 + 0.015*sl 0.287 + 0.013*sl 0.293 + 0.013*sl sck to qn t r 0.127 0.076 + 0.025*sl 0.072 + 0.026*sl 0.061 + 0.028*sl t f 0.103 0.055 + 0.024*sl 0.059 + 0.023*sl 0.050 + 0.024*sl t plh 0.399 0.369 + 0.015*sl 0.377 + 0.013*sl 0.383 + 0.012*sl t phl 0.332 0.301 + 0.016*sl 0.310 + 0.013*sl 0.318 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.086 0.058 + 0.014*sl 0.060 + 0.014*sl 0.055 + 0.014*sl t f 0.078 0.053 + 0.012*sl 0.054 + 0.012*sl 0.052 + 0.012*sl t plh 0.412 0.395 + 0.009*sl 0.401 + 0.007*sl 0.413 + 0.006*sl t phl 0.420 0.401 + 0.009*sl 0.409 + 0.007*sl 0.421 + 0.007*sl sck to q t r 0.079 0.053 + 0.013*sl 0.052 + 0.013*sl 0.040 + 0.014*sl t f 0.074 0.051 + 0.012*sl 0.051 + 0.012*sl 0.043 + 0.012*sl t plh 0.425 0.408 + 0.008*sl 0.414 + 0.007*sl 0.420 + 0.006*sl t phl 0.505 0.487 + 0.009*sl 0.494 + 0.007*sl 0.503 + 0.006*sl ck to qn t r 0.084 0.057 + 0.014*sl 0.057 + 0.014*sl 0.048 + 0.014*sl t f 0.077 0.053 + 0.012*sl 0.053 + 0.012*sl 0.052 + 0.012*sl t plh 0.316 0.299 + 0.009*sl 0.306 + 0.007*sl 0.314 + 0.006*sl t phl 0.310 0.291 + 0.010*sl 0.299 + 0.007*sl 0.313 + 0.007*sl sck to qn t r 0.105 0.080 + 0.013*sl 0.079 + 0.013*sl 0.065 + 0.014*sl t f 0.083 0.057 + 0.013*sl 0.061 + 0.012*sl 0.057 + 0.012*sl t plh 0.411 0.392 + 0.010*sl 0.401 + 0.007*sl 0.413 + 0.006*sl t phl 0.333 0.313 + 0.010*sl 0.322 + 0.007*sl 0.337 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-382 samsung asic fds3s/fds3sd2 flip-flop with synchronous set, scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fds3s fds3sd2 fds3s fds3sd2 d csn ck ti te d csn ck ti te 0.6 0.6 0.7 0.7 1.4 0.6 0.6 0.7 0.7 1.3 7.67 8.00 parameter symbol value (ns) fds3s fds3sd2 input setup time (d to ck) t su 0.387 0.392 input hold time (d to ck) t hd 0.000 0.000 input setup time (csn to ck) t su 0.340 0.344 input hold time (csn to ck) t hd 0.000 0.000 pulse width low (ck) t pwl 0.317 0.320 pulse width high (ck) t pwh 0.246 0.259 input setup time (ti to ck) t su 0.316 0.317 input hold time (ti to ck) t hd 0.037 0.033 input setup time (te to ck) t su 0.315 0.316 input hold time (te to ck) t hd 0.017 0.016 q qn d te ck csn ti clb cl clb cl qn q d csn ti ck cl clb te te teb clb cl teb te clb cl truth table d csn ti te ck q(n+1) qn(n+1) 01x0 0 1 11x0 1 0 xx01 0 1 xx11 1 0 x0x0 1 0 x x x x q(n) qn(n+1)
samsung asic 3-383 STD111 fds3s/fds3sd2 flip-flop with synchronous set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fds3s fds3sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.109 0.055 + 0.027*sl 0.052 + 0.028*sl 0.046 + 0.028*sl t f 0.097 0.048 + 0.024*sl 0.051 + 0.024*sl 0.045 + 0.024*sl t plh 0.308 0.279 + 0.014*sl 0.285 + 0.013*sl 0.288 + 0.012*sl t phl 0.311 0.280 + 0.015*sl 0.288 + 0.013*sl 0.294 + 0.013*sl ck to qn t r 0.102 0.048 + 0.027*sl 0.043 + 0.028*sl 0.038 + 0.029*sl t f 0.090 0.042 + 0.024*sl 0.043 + 0.024*sl 0.035 + 0.024*sl t plh 0.362 0.335 + 0.014*sl 0.339 + 0.013*sl 0.340 + 0.012*sl t phl 0.365 0.336 + 0.015*sl 0.342 + 0.013*sl 0.345 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.083 0.056 + 0.014*sl 0.056 + 0.013*sl 0.046 + 0.014*sl t f 0.075 0.052 + 0.012*sl 0.051 + 0.012*sl 0.049 + 0.012*sl t plh 0.311 0.294 + 0.009*sl 0.301 + 0.007*sl 0.309 + 0.006*sl t phl 0.309 0.290 + 0.009*sl 0.298 + 0.007*sl 0.311 + 0.006*sl ck to qn t r 0.078 0.051 + 0.013*sl 0.051 + 0.013*sl 0.039 + 0.014*sl t f 0.071 0.047 + 0.012*sl 0.048 + 0.012*sl 0.041 + 0.012*sl t plh 0.395 0.379 + 0.008*sl 0.385 + 0.007*sl 0.390 + 0.006*sl t phl 0.397 0.380 + 0.009*sl 0.387 + 0.007*sl 0.396 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-384 samsung asic fj1/fj1d2 jk flip-flop with 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fj1 fj1d2 fj1 fj1d2 jkckjkck 0.5 0.6 0.7 0.5 0.6 0.7 6.67 7.00 parameter symbol value (ns) fj1 fj1d2 input setup time (j to ck) t su 0.287 0.291 input hold time (j to ck) t hd 0.037 0.034 input setup time (k to ck) t su 0.287 0.291 input hold time (k to ck) t hd 0.037 0.034 pulse width low (ck) t pwl 0.310 0.312 pulse width high (ck) t pwh 0.253 0.271 j ck k q qn cl clb clb cl clb cl qn q k j cl clb ck cl clb truth table j ck k q (n+1) qn (n+1) 0 101 1 010 0 0 q (n) qn (n) 1 1 qn (n) q (n) x x q (n) qn (n)
samsung asic 3-385 STD111 fj1/fj1d2 jk flip-flop with 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fj1 fj1d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.111 0.057 + 0.027*sl 0.055 + 0.028*sl 0.048 + 0.028*sl t f 0.099 0.052 + 0.024*sl 0.054 + 0.023*sl 0.046 + 0.024*sl t plh 0.399 0.372 + 0.014*sl 0.374 + 0.013*sl 0.378 + 0.012*sl t phl 0.397 0.366 + 0.016*sl 0.375 + 0.013*sl 0.381 + 0.013*sl ck to qn t r 0.108 0.056 + 0.026*sl 0.051 + 0.028*sl 0.044 + 0.028*sl t f 0.096 0.049 + 0.024*sl 0.048 + 0.024*sl 0.043 + 0.024*sl t plh 0.310 0.282 + 0.014*sl 0.288 + 0.013*sl 0.290 + 0.012*sl t phl 0.315 0.284 + 0.015*sl 0.292 + 0.013*sl 0.297 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.086 0.059 + 0.013*sl 0.060 + 0.013*sl 0.050 + 0.014*sl t f 0.078 0.053 + 0.013*sl 0.057 + 0.011*sl 0.053 + 0.012*sl t plh 0.433 0.415 + 0.009*sl 0.422 + 0.007*sl 0.432 + 0.006*sl t phl 0.431 0.412 + 0.010*sl 0.421 + 0.007*sl 0.435 + 0.006*sl ck to qn t r 0.085 0.057 + 0.014*sl 0.059 + 0.013*sl 0.047 + 0.014*sl t f 0.076 0.051 + 0.013*sl 0.055 + 0.012*sl 0.050 + 0.012*sl t plh 0.320 0.302 + 0.009*sl 0.309 + 0.007*sl 0.318 + 0.006*sl t phl 0.318 0.299 + 0.010*sl 0.308 + 0.007*sl 0.320 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-386 samsung asic fj1s/fj1sd2 jk flip-flop with scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count fj1s fj1sd2 fj1s fj1sd2 j k ck ti te j k ck ti te 0.6 0.5 0.7 0.7 1.4 0.6 0.5 0.7 0.7 1.4 8.67 9.00 q qn j ti te ck k cl clb clb cl clb cl te teb q qn k j ti ck cl clb te te teb cl clb truth table j ck k ti te q (n+1) qn (n+1) 01x001 10x010 0 0 x 0 q (n) qn (n) 1 1 x 0 qn (n) q (n) x x x x q (n) qn (n) x x0101 x x1110
samsung asic 3-387 STD111 fj1s/fj1sd2 jk flip-flop with scan, 1x/2x drive timing requirements (typical process, 25 c, 2.5v, unit = ns) switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fj1s fj1sd2 parameter symbol value (ns) fj1s fj1sd2 input setup time (j to ck) t su 0.452 0.452 input hold time (j to ck) t hd 0.000 0.000 input setup time (k to ck) t su 0.452 0.452 input hold time (k to ck) t hd 0.000 0.000 pulse width low (ck) t pwl 0.318 0.318 pulse width high (ck) t pwh 0.261 0.278 input setup time (ti to ck) t su 0.318 0.317 input hold time (ti to ck) t hd 0.034 0.034 input setup time (te to ck) t su 0.318 0.317 input hold time (te to ck) t hd 0.015 0.016 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.120 0.067 + 0.026*sl 0.065 + 0.027*sl 0.056 + 0.028*sl t f 0.107 0.059 + 0.024*sl 0.063 + 0.023*sl 0.056 + 0.024*sl t plh 0.344 0.313 + 0.015*sl 0.321 + 0.013*sl 0.327 + 0.012*sl t phl 0.341 0.308 + 0.017*sl 0.318 + 0.014*sl 0.328 + 0.013*sl ck to qn t r 0.104 0.051 + 0.027*sl 0.046 + 0.028*sl 0.040 + 0.029*sl t f 0.092 0.045 + 0.023*sl 0.043 + 0.024*sl 0.038 + 0.024*sl t plh 0.394 0.368 + 0.013*sl 0.371 + 0.012*sl 0.372 + 0.012*sl t phl 0.402 0.373 + 0.014*sl 0.379 + 0.013*sl 0.381 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.095 0.066 + 0.014*sl 0.070 + 0.013*sl 0.060 + 0.014*sl t f 0.085 0.060 + 0.013*sl 0.063 + 0.012*sl 0.063 + 0.012*sl t plh 0.348 0.329 + 0.009*sl 0.337 + 0.007*sl 0.350 + 0.006*sl t phl 0.341 0.320 + 0.010*sl 0.330 + 0.008*sl 0.347 + 0.007*sl ck to qn t r 0.079 0.053 + 0.013*sl 0.052 + 0.013*sl 0.040 + 0.014*sl t f 0.070 0.046 + 0.012*sl 0.048 + 0.012*sl 0.042 + 0.012*sl t plh 0.430 0.414 + 0.008*sl 0.420 + 0.007*sl 0.426 + 0.006*sl t phl 0.436 0.418 + 0.009*sl 0.425 + 0.007*sl 0.435 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-388 samsung asic fj2/fj2d2 jk flip-flop with reset, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count fj2 fj2d2 fj2 fj2d2 j k ck rn j k ck rn 0.6 0.6 0.7 1.8 0.6 0.6 0.7 1.8 7.33 7.67 j ck k q qn rn cl clb clb cl q qn j k ck cl clb rn rn rn cl clb cl clb rn truth table jckkrn q (n+1) qn (n+1) 01101 10110 0 0 1 q (n) qn (n) 1 1 1 qn (n) q (n) x x 1 q (n) qn (n) xxx001
samsung asic 3-389 STD111 fj2/fj2d2 jk flip-flop with reset, 1x/2x drive timing requirements (typical process, 25 c, 2.5v, unit = ns) switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fj2 fj2d2 parameter symbol value (ns) fj2 fj2d2 input setup time (j to ck) t su 0.287 0.288 input hold time (j to ck) t hd 0.023 0.022 input setup time (k to ck) t su 0.287 0.288 input hold time (k to ck) t hd 0.023 0.022 pulse width low (ck) t pwl 0.309 0.309 pulse width high (ck) t pwh 0.259 0.276 pulse width low (rn) t pwl 0.302 0.336 recovery time (rn to ck) t rc 0.000 0.000 removal time (rn to ck) t rm 0.234 0.234 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.120 0.065 + 0.027*sl 0.066 + 0.027*sl 0.060 + 0.028*sl t f 0.102 0.055 + 0.024*sl 0.058 + 0.023*sl 0.052 + 0.023*sl t plh 0.436 0.404 + 0.016*sl 0.413 + 0.013*sl 0.422 + 0.012*sl t phl 0.414 0.383 + 0.016*sl 0.392 + 0.013*sl 0.401 + 0.012*sl rn to q t f 0.117 0.071 + 0.023*sl 0.072 + 0.023*sl 0.069 + 0.023*sl t phl 0.210 0.175 + 0.017*sl 0.187 + 0.014*sl 0.200 + 0.013*sl ck to qn t r 0.110 0.056 + 0.027*sl 0.054 + 0.027*sl 0.045 + 0.028*sl t f 0.099 0.054 + 0.023*sl 0.052 + 0.023*sl 0.048 + 0.023*sl t plh 0.314 0.286 + 0.014*sl 0.292 + 0.013*sl 0.294 + 0.012*sl t phl 0.331 0.301 + 0.015*sl 0.309 + 0.013*sl 0.315 + 0.013*sl rn to qn t r 0.120 0.070 + 0.025*sl 0.064 + 0.027*sl 0.052 + 0.028*sl t plh 0.397 0.367 + 0.015*sl 0.375 + 0.013*sl 0.379 + 0.012*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.095 0.067 + 0.014*sl 0.068 + 0.014*sl 0.064 + 0.014*sl t f 0.082 0.057 + 0.013*sl 0.061 + 0.012*sl 0.058 + 0.012*sl t plh 0.468 0.449 + 0.010*sl 0.458 + 0.007*sl 0.473 + 0.006*sl t phl 0.445 0.426 + 0.010*sl 0.434 + 0.007*sl 0.451 + 0.006*sl rn to q t f 0.097 0.073 + 0.012*sl 0.074 + 0.012*sl 0.077 + 0.012*sl t phl 0.206 0.184 + 0.011*sl 0.195 + 0.008*sl 0.216 + 0.007*sl ck to qn t r 0.085 0.059 + 0.013*sl 0.057 + 0.013*sl 0.047 + 0.014*sl t f 0.079 0.053 + 0.013*sl 0.058 + 0.011*sl 0.053 + 0.012*sl t plh 0.320 0.303 + 0.009*sl 0.309 + 0.007*sl 0.317 + 0.006*sl t phl 0.335 0.316 + 0.010*sl 0.325 + 0.007*sl 0.338 + 0.006*sl rn to qn t r 0.099 0.074 + 0.012*sl 0.072 + 0.013*sl 0.059 + 0.014*sl t plh 0.432 0.414 + 0.009*sl 0.422 + 0.007*sl 0.433 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-390 samsung asic fj2s/fj2sd2 jk flip-flop with reset, scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count fj2s fj2sd2 fj2s fj2sd2 j k ck rn ti te j k ck rn ti te 0.7 0.5 0.7 1.3 0.6 1.4 0.7 0.5 0.7 1.3 0.7 1.4 9.00 9.33 parameter symbol value (ns) fj2s fj2sd2 input setup time (j to ck) t su 0.445 0.437 input hold time (j to ck) t hd 0.000 0.000 input setup time (k to ck) t su 0.445 0.437 input hold time (k to ck) t hd 0.000 0.000 pulse width low (ck) t pwl 0.322 0.321 pulse width high (ck) t pwh 0.265 0.283 pulse width low (rn) t pwl 0.278 0.317 recovery time (rn to ck) t rc 0.000 0.000 removal time (rn to ck) t rm 0.520 0.534 input setup time (ti to ck) t su 0.328 0.318 input hold time (ti to ck) t hd 0.051 0.052 input setup time (te to ck) t su 0.324 0.317 input hold time (te to ck) t hd 0.033 0.029 q qn j ti te ck k rn cl clb clb cl clb cl te teb q qn j k ti ck cl clb rn rn rn teb te te cl clb rn truth table j ck k ti te rn q (n+1) qn (n+1) 01x0101 10x0110 0 0 x 0 1 q (n) qn (n) 1 1 x 0 1 qn (n) q (n) x x x x 1 q (n) qn (n) xxxxx0 0 1 xx01101 xx11110
samsung asic 3-391 STD111 fj2s/fj2sd2 jk flip-flop with reset, scan, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fj2s fj2sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.128 0.074 + 0.027*sl 0.074 + 0.027*sl 0.067 + 0.028*sl t f 0.108 0.059 + 0.024*sl 0.064 + 0.023*sl 0.059 + 0.024*sl t plh 0.356 0.323 + 0.016*sl 0.333 + 0.014*sl 0.344 + 0.013*sl t phl 0.353 0.319 + 0.017*sl 0.330 + 0.014*sl 0.341 + 0.013*sl rn to q t f 0.113 0.064 + 0.025*sl 0.071 + 0.023*sl 0.063 + 0.024*sl t phl 0.203 0.168 + 0.017*sl 0.180 + 0.014*sl 0.191 + 0.013*sl ck to qn t r 0.102 0.048 + 0.027*sl 0.045 + 0.028*sl 0.039 + 0.029*sl t f 0.090 0.044 + 0.023*sl 0.044 + 0.023*sl 0.038 + 0.024*sl t plh 0.405 0.378 + 0.013*sl 0.382 + 0.012*sl 0.383 + 0.012*sl t phl 0.414 0.386 + 0.014*sl 0.392 + 0.013*sl 0.395 + 0.012*sl rn to qn t r 0.115 0.058 + 0.029*sl 0.060 + 0.028*sl 0.059 + 0.028*sl t plh 0.278 0.247 + 0.015*sl 0.253 + 0.014*sl 0.263 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.100 0.070 + 0.015*sl 0.075 + 0.014*sl 0.071 + 0.014*sl t f 0.086 0.060 + 0.013*sl 0.064 + 0.012*sl 0.065 + 0.012*sl t plh 0.362 0.342 + 0.010*sl 0.351 + 0.008*sl 0.367 + 0.006*sl t phl 0.353 0.333 + 0.010*sl 0.343 + 0.008*sl 0.361 + 0.007*sl rn to q t f 0.092 0.067 + 0.012*sl 0.070 + 0.012*sl 0.071 + 0.012*sl t phl 0.198 0.176 + 0.011*sl 0.187 + 0.008*sl 0.207 + 0.007*sl ck to qn t r 0.080 0.054 + 0.013*sl 0.053 + 0.013*sl 0.041 + 0.014*sl t f 0.073 0.049 + 0.012*sl 0.052 + 0.011*sl 0.044 + 0.012*sl t plh 0.445 0.429 + 0.008*sl 0.435 + 0.007*sl 0.440 + 0.006*sl t phl 0.454 0.436 + 0.009*sl 0.443 + 0.007*sl 0.454 + 0.006*sl rn to qn t r 0.090 0.061 + 0.014*sl 0.064 + 0.014*sl 0.060 + 0.014*sl t plh 0.315 0.297 + 0.009*sl 0.303 + 0.007*sl 0.316 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-392 samsung asic fj4/fj4d2 jk flip-flop with reset, set, 1x/2x drive logic symbol5 cell data schematic diagram input load (sl) gate count fj4 fj4d2 fj4 fj4d2 j k ck rn sn j k ck rn sn 0.6 0.6 0.7 1.7 1.4 0.6 0.6 0.7 1.7 1.4 8.00 8.33 j ck k q qn rn sn j cl clb k q qn cl clb clb cl clb cl rn sn cl ck clb truth table j ck k rn sn q (n+1) qn (n+1) 0 11101 1 01110 0 0 1 1 q (n) qn (n) 1 1 1 1 qn (n) q (n) x x 1 1 q (n) qn (n) xxx0101 xxx1010 xxx0000
samsung asic 3-393 STD111 fj4/fj4d2 jk flip-flop with reset, set, 1x/2x drive timing requirements (typical process, 25 c, 2.5v, unit = ns) switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fj4 parameter symbol value (ns) fj4 fj4d2 input setup time (j to ck) t su 0.294 0.294 input hold time (j to ck) t hd 0.042 0.041 input setup time (k to ck) t su 0.294 0.294 input hold time (k to ck) t hd 0.042 0.041 pulse width low (ck) t pwl 0.319 0.319 pulse width high (ck) t pwh 0.270 0.286 pulse width low (rn) t pwl 0.317 0.349 pulse width low (sn) t pwl 0.288 0.319 recovery time (rn to ck) t rc 0.000 0.000 removal time (rn to ck) t rm 0.268 0.319 recovery time (sn to ck) t rc 0.000 0.000 removal time (sn to ck) t rm 0.556 0.556 recovery time (sn to rn) t rc 0.133 0.131 removal time (sn to rn) t rm 0.087 0.089 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.121 0.066 + 0.028*sl 0.067 + 0.027*sl 0.060 + 0.028*sl t f 0.104 0.058 + 0.023*sl 0.060 + 0.023*sl 0.054 + 0.023*sl t plh 0.460 0.428 + 0.016*sl 0.437 + 0.013*sl 0.446 + 0.013*sl t phl 0.440 0.408 + 0.016*sl 0.418 + 0.013*sl 0.427 + 0.013*sl rn to q t r 0.132 0.074 + 0.029*sl 0.079 + 0.028*sl 0.079 + 0.028*sl t f 0.119 0.072 + 0.023*sl 0.075 + 0.023*sl 0.072 + 0.023*sl t plh 0.186 0.151 + 0.017*sl 0.162 + 0.015*sl 0.177 + 0.013*sl t phl 0.213 0.178 + 0.018*sl 0.190 + 0.014*sl 0.204 + 0.013*sl sn to q t r 0.134 0.076 + 0.029*sl 0.081 + 0.028*sl 0.082 + 0.028*sl t plh 0.306 0.271 + 0.017*sl 0.281 + 0.015*sl 0.297 + 0.013*sl ck to qn t r 0.117 0.062 + 0.027*sl 0.061 + 0.028*sl 0.056 + 0.028*sl t f 0.102 0.057 + 0.022*sl 0.055 + 0.023*sl 0.052 + 0.023*sl t plh 0.334 0.303 + 0.015*sl 0.311 + 0.013*sl 0.317 + 0.013*sl t phl 0.351 0.320 + 0.016*sl 0.329 + 0.013*sl 0.336 + 0.013*sl rn to qn t r 0.126 0.074 + 0.026*sl 0.070 + 0.027*sl 0.063 + 0.028*sl t plh 0.420 0.388 + 0.016*sl 0.397 + 0.013*sl 0.405 + 0.012*sl sn to qn t r 0.114 0.060 + 0.027*sl 0.058 + 0.027*sl 0.051 + 0.028*sl t f 0.102 0.056 + 0.023*sl 0.055 + 0.023*sl 0.052 + 0.023*sl t plh 0.150 0.120 + 0.015*sl 0.128 + 0.013*sl 0.133 + 0.012*sl t phl 0.173 0.142 + 0.016*sl 0.151 + 0.013*sl 0.157 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-394 samsung asic fj4/fj4d2 jk flip-flop with reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fj4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.095 0.067 + 0.014*sl 0.070 + 0.014*sl 0.064 + 0.014*sl t f 0.084 0.059 + 0.012*sl 0.063 + 0.011*sl 0.060 + 0.012*sl t plh 0.488 0.469 + 0.010*sl 0.478 + 0.007*sl 0.493 + 0.006*sl t phl 0.468 0.449 + 0.010*sl 0.458 + 0.007*sl 0.475 + 0.006*sl rn to q t r 0.103 0.074 + 0.014*sl 0.075 + 0.014*sl 0.081 + 0.014*sl t f 0.098 0.072 + 0.013*sl 0.077 + 0.011*sl 0.077 + 0.011*sl t plh 0.184 0.163 + 0.010*sl 0.172 + 0.008*sl 0.192 + 0.007*sl t phl 0.208 0.186 + 0.011*sl 0.197 + 0.008*sl 0.219 + 0.007*sl sn to q t r 0.107 0.078 + 0.015*sl 0.081 + 0.014*sl 0.084 + 0.014*sl t plh 0.330 0.309 + 0.011*sl 0.319 + 0.008*sl 0.340 + 0.007*sl ck to qn t r 0.092 0.063 + 0.014*sl 0.066 + 0.014*sl 0.060 + 0.014*sl t f 0.082 0.058 + 0.012*sl 0.061 + 0.011*sl 0.057 + 0.012*sl t plh 0.337 0.318 + 0.009*sl 0.326 + 0.007*sl 0.339 + 0.006*sl t phl 0.353 0.333 + 0.010*sl 0.342 + 0.007*sl 0.356 + 0.006*sl rn to qn t r 0.103 0.077 + 0.013*sl 0.076 + 0.013*sl 0.069 + 0.014*sl t plh 0.450 0.431 + 0.010*sl 0.440 + 0.007*sl 0.454 + 0.006*sl sn to qn t r 0.087 0.060 + 0.014*sl 0.060 + 0.014*sl 0.055 + 0.014*sl t f 0.080 0.054 + 0.013*sl 0.060 + 0.011*sl 0.056 + 0.012*sl t plh 0.153 0.135 + 0.009*sl 0.142 + 0.007*sl 0.155 + 0.006*sl t phl 0.172 0.152 + 0.010*sl 0.161 + 0.007*sl 0.175 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-395 STD111 fj4s/fj4sd2 jk flip-flop with reset, set, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count fj4s fj4sd2 fj4s fj4sd2 j k ck rn sn ti te j k ck rn sn ti te 0.7 0.5 0.7 1.4 1.7 0.7 1.4 0.6 0.5 0.7 1.4 1.7 0.7 1.4 10.00 10.33 q qn j ti te ck k rn sn cl clb clb cl clb cl q qn j k ti cl clb ck cl clb rn rn rn sn rn sn sn sn te te teb te teb truth table j ck k ti te rn sn q (n+1) qn (n+1) 01x01101 10x01110 0 0 x 0 1 1 q (n) qn (n) 1 1 x 0 1 1 qn (n) q (n) x x x x 1 1 q (n) qn (n) xxxxx01 0 1 xxxxx10 1 0 xxxxx00 0 0 x x0111 0 1 x x1111 1 0
STD111 3-396 samsung asic fj4s/fj4sd2 jk flip-flop with reset, set, scan, 1x/2x drive timing requirements (typical process, 25 c, 2.5v, unit = ns) switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fj4s parameter symbol value (ns) fj4s fj4sd2 input setup time (j to ck) t su 0.450 0.449 input hold time (j to ck) t hd 0.000 0.000 input setup time (k to ck) t su 0.450 0.449 input hold time (k to ck) t hd 0.000 0.000 pulse width low (ck) t pwl 0.354 0.354 pulse width high (ck) t pwh 0.279 0.298 pulse width low (rn) t pwl 0.291 0.327 pulse width low (sn) t pwl 0.318 0.347 recovery time (rn to ck) t rc 0.000 0.000 removal time (rn to ck) t rm 0.538 0.539 recovery time (sn to ck) t rc 0.000 0.000 removal time (sn to ck) t rm 0.271 0.271 input setup time (ti to ck) t su 0.330 0.330 input hold time (ti to ck) t hd 0.048 0.048 input setup time (te to ck) t su 0.336 0.336 input hold time (te to ck) t hd 0.029 0.029 recovery time (sn to rn) t rc 0.087 0.087 removal time (sn to rn) t rm 0.133 0.133 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.131 0.076 + 0.027*sl 0.078 + 0.027*sl 0.071 + 0.028*sl t f 0.114 0.065 + 0.024*sl 0.069 + 0.023*sl 0.067 + 0.024*sl t plh 0.368 0.335 + 0.016*sl 0.345 + 0.014*sl 0.356 + 0.013*sl t phl 0.380 0.346 + 0.017*sl 0.357 + 0.014*sl 0.369 + 0.013*sl rn to q t r 0.126 0.072 + 0.027*sl 0.071 + 0.027*sl 0.064 + 0.028*sl t f 0.115 0.066 + 0.024*sl 0.071 + 0.023*sl 0.067 + 0.024*sl t plh 0.181 0.149 + 0.016*sl 0.158 + 0.013*sl 0.167 + 0.013*sl t phl 0.206 0.171 + 0.017*sl 0.183 + 0.014*sl 0.195 + 0.013*sl sn to q t r 0.137 0.085 + 0.026*sl 0.083 + 0.027*sl 0.074 + 0.028*sl t plh 0.422 0.389 + 0.016*sl 0.400 + 0.014*sl 0.410 + 0.013*sl ck to qn t r 0.111 0.057 + 0.027*sl 0.054 + 0.028*sl 0.048 + 0.028*sl t f 0.097 0.050 + 0.023*sl 0.049 + 0.024*sl 0.043 + 0.024*sl t plh 0.450 0.421 + 0.015*sl 0.428 + 0.013*sl 0.432 + 0.012*sl t phl 0.445 0.414 + 0.015*sl 0.422 + 0.013*sl 0.427 + 0.013*sl rn to qn t r 0.125 0.066 + 0.029*sl 0.071 + 0.028*sl 0.073 + 0.028*sl t plh 0.301 0.268 + 0.017*sl 0.276 + 0.014*sl 0.290 + 0.013*sl sn to qn t r 0.121 0.062 + 0.030*sl 0.067 + 0.028*sl 0.068 + 0.028*sl t f 0.105 0.055 + 0.025*sl 0.059 + 0.024*sl 0.057 + 0.024*sl t plh 0.153 0.120 + 0.016*sl 0.128 + 0.014*sl 0.141 + 0.013*sl t phl 0.181 0.148 + 0.016*sl 0.156 + 0.014*sl 0.165 + 0.013*sl * group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-397 STD111 fj4s/fj4sd2 jk flip-flop with reset, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fj4sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.103 0.074 + 0.014*sl 0.077 + 0.014*sl 0.074 + 0.014*sl t f 0.091 0.066 + 0.013*sl 0.070 + 0.012*sl 0.069 + 0.012*sl t plh 0.367 0.347 + 0.010*sl 0.357 + 0.008*sl 0.374 + 0.006*sl t phl 0.377 0.356 + 0.011*sl 0.366 + 0.008*sl 0.385 + 0.007*sl rn to q t r 0.098 0.068 + 0.015*sl 0.074 + 0.013*sl 0.067 + 0.014*sl t f 0.093 0.067 + 0.013*sl 0.072 + 0.012*sl 0.072 + 0.012*sl t plh 0.180 0.160 + 0.010*sl 0.169 + 0.007*sl 0.186 + 0.006*sl t phl 0.200 0.178 + 0.011*sl 0.189 + 0.008*sl 0.209 + 0.007*sl sn to q t r 0.112 0.086 + 0.013*sl 0.086 + 0.013*sl 0.079 + 0.014*sl t plh 0.450 0.430 + 0.010*sl 0.440 + 0.008*sl 0.458 + 0.006*sl ck to qn t r 0.087 0.058 + 0.014*sl 0.062 + 0.013*sl 0.052 + 0.014*sl t f 0.078 0.053 + 0.012*sl 0.056 + 0.012*sl 0.050 + 0.012*sl t plh 0.483 0.465 + 0.009*sl 0.473 + 0.007*sl 0.484 + 0.006*sl t phl 0.478 0.459 + 0.009*sl 0.467 + 0.007*sl 0.480 + 0.006*sl rn to qn t r 0.099 0.071 + 0.014*sl 0.071 + 0.014*sl 0.075 + 0.014*sl t plh 0.331 0.311 + 0.010*sl 0.319 + 0.008*sl 0.337 + 0.007*sl sn to qn t r 0.093 0.064 + 0.014*sl 0.065 + 0.014*sl 0.069 + 0.014*sl t f 0.084 0.058 + 0.013*sl 0.063 + 0.012*sl 0.061 + 0.012*sl t plh 0.154 0.134 + 0.010*sl 0.142 + 0.008*sl 0.159 + 0.007*sl t phl 0.179 0.159 + 0.010*sl 0.168 + 0.008*sl 0.183 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-398 samsung asic ft2/ft2d2 toggle flip-flop with reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count ft2 ft2d2 ft2 ft2d2 ck rn ck rn 0.7 1.8 0.7 1.8 5.67 6.00 parameter symbol value (ns) ft2 ft2d2 pulse width low (ck) t pwl 0.210 0.230 pulse width high (ck) t pwh 0.262 0.256 pulse width low (rn) t pwl 0.316 0.353 recovery time (rn to ck) t rc 0.000 0.000 removal time (rn to ck) t rm 0.229 0.230 ck q qn rn clb cl clb cl q qn ck cl clb rn rn rn rn clb cl clb cl truth table ck rn q (n+1) qn (n+1) 1 qn (n) q (n) 1 q (n) qn (n) x001
samsung asic 3-399 STD111 ft2/ft2d2 toggle flip-flop with reset, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ft2 ft2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.113 0.060 + 0.027*sl 0.057 + 0.028*sl 0.051 + 0.028*sl t f 0.100 0.053 + 0.023*sl 0.053 + 0.023*sl 0.046 + 0.024*sl t plh 0.410 0.379 + 0.015*sl 0.387 + 0.013*sl 0.392 + 0.012*sl t phl 0.402 0.371 + 0.016*sl 0.379 + 0.013*sl 0.385 + 0.013*sl rn to q t f 0.101 0.053 + 0.024*sl 0.055 + 0.023*sl 0.048 + 0.024*sl t phl 0.174 0.142 + 0.016*sl 0.151 + 0.014*sl 0.158 + 0.013*sl ck to qn t r 0.112 0.060 + 0.026*sl 0.055 + 0.027*sl 0.046 + 0.028*sl t f 0.102 0.055 + 0.023*sl 0.055 + 0.023*sl 0.049 + 0.024*sl t plh 0.315 0.286 + 0.014*sl 0.293 + 0.013*sl 0.296 + 0.012*sl t phl 0.325 0.293 + 0.016*sl 0.302 + 0.014*sl 0.309 + 0.013*sl rn to qn t r 0.110 0.058 + 0.026*sl 0.053 + 0.027*sl 0.045 + 0.028*sl t plh 0.299 0.270 + 0.014*sl 0.277 + 0.013*sl 0.279 + 0.012*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t r 0.086 0.058 + 0.014*sl 0.059 + 0.014*sl 0.054 + 0.014*sl t f 0.077 0.053 + 0.012*sl 0.055 + 0.012*sl 0.051 + 0.012*sl t plh 0.438 0.420 + 0.009*sl 0.427 + 0.007*sl 0.440 + 0.006*sl t phl 0.431 0.412 + 0.010*sl 0.420 + 0.007*sl 0.434 + 0.006*sl rn to q t f 0.079 0.053 + 0.013*sl 0.059 + 0.011*sl 0.052 + 0.012*sl t phl 0.171 0.151 + 0.010*sl 0.160 + 0.007*sl 0.174 + 0.006*sl ck to qn t r 0.086 0.060 + 0.013*sl 0.058 + 0.014*sl 0.049 + 0.014*sl t f 0.079 0.054 + 0.012*sl 0.056 + 0.012*sl 0.053 + 0.012*sl t plh 0.321 0.303 + 0.009*sl 0.310 + 0.007*sl 0.319 + 0.006*sl t phl 0.326 0.307 + 0.010*sl 0.315 + 0.007*sl 0.328 + 0.007*sl rn to qn t r 0.085 0.058 + 0.013*sl 0.059 + 0.013*sl 0.047 + 0.014*sl t plh 0.308 0.291 + 0.009*sl 0.298 + 0.007*sl 0.307 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-400 samsung asic latches cell list cell name function description ld1 d latch with active high ld1d2 d latch with active high, 2x drive ld1a d latch with active high, tri-state output ld1d2a d latch with active high, tri-state output, 2x drive ld1q d latch with active high, q output only ld1qd2 d latch with active high, q output only, 2x drive ld2 d latch with active high, reset ld2d2 d latch with active high, reset, 2x drive ld2q d latch with active high, reset, q output only ld2qd2 d latch with active high, reset, q output only, 2x drive ld3 d latch with active high, set ld3d2 d latch with active high, set, 2x drive ld4 d latch with active high, reset, set ld4d2 d latch with active high, reset, set, 2x drive ld5 d latch with active low ld5d2 d latch with active low, 2x drive ld5q d latch with active low, q output only ld5qd2 d latch with active low, q output only, 2x drive ld6 d latch with active low, reset ld6d2 d latch with active low, reset, 2x drive ld6q d latch with active low, reset, q output only ld6qd2 d latch with active low, reset, q output only, 2x drive ld7 d latch with active low, set ld7d2 d latch with active low, set, 2x drive ld8 d latch with active low, reset, set ld8d2 d latch with active low, reset, set, 2x drive oak_ldi2 d latch with 2 input, 2 active high (for oak core only) oak_ldi2d2 d latch with 2 input, 2 active high, 2x drive (for oak core only) oak_ldi3 d latch with 3 input, 3 active high (for oak core only) oak_ldi3d2 d latch with 3 input, 3 active high, 2x drive (for oak core only)
samsung asic 3-401 STD111 latches cell list cell name function description ls0 sr latch ls0d2 sr latch with 2x drive ls1 sr latch with separate inputs ls1d2 sr latch with separate inputs, 2x drive
STD111 3-402 samsung asic ld1/ld1d2 d latch with active high, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count ld1 ld1d2 ld1 ld1d2 dgdg 0.8 0.7 0.8 0.7 4.00 4.00 parameter symbol value (ns) ld1 ld1d2 input setup time (d to g) t su 0.199 0.214 input hold time (d to g) t hd 0.077 0.057 pulse width high (g) t pwh 0.235 0.251 d g q qn gl g gb d gb gl gl gb qn q truth table d g q (n+1) qn (n+1) 0101 1110 x 0 q (n) qn (n)
samsung asic 3-403 STD111 ld1/ld1d2 d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ld1 ld1d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.101 0.047 + 0.027*sl 0.042 + 0.028*sl 0.037 + 0.029*sl t f 0.089 0.043 + 0.023*sl 0.040 + 0.024*sl 0.035 + 0.024*sl t plh 0.291 0.264 + 0.014*sl 0.268 + 0.012*sl 0.269 + 0.012*sl t phl 0.304 0.275 + 0.015*sl 0.280 + 0.013*sl 0.283 + 0.013*sl g to q t r 0.101 0.048 + 0.027*sl 0.042 + 0.028*sl 0.037 + 0.029*sl t f 0.089 0.042 + 0.023*sl 0.041 + 0.024*sl 0.035 + 0.024*sl t plh 0.335 0.308 + 0.014*sl 0.312 + 0.012*sl 0.313 + 0.012*sl t phl 0.346 0.317 + 0.015*sl 0.323 + 0.013*sl 0.325 + 0.013*sl d to qn t r 0.109 0.056 + 0.027*sl 0.053 + 0.028*sl 0.045 + 0.028*sl t f 0.097 0.050 + 0.023*sl 0.049 + 0.024*sl 0.043 + 0.024*sl t plh 0.247 0.219 + 0.014*sl 0.224 + 0.013*sl 0.228 + 0.012*sl t phl 0.240 0.209 + 0.016*sl 0.217 + 0.013*sl 0.223 + 0.013*sl g to qn t r 0.109 0.055 + 0.027*sl 0.051 + 0.028*sl 0.045 + 0.028*sl t f 0.096 0.050 + 0.023*sl 0.049 + 0.024*sl 0.043 + 0.024*sl t plh 0.290 0.261 + 0.014*sl 0.267 + 0.013*sl 0.270 + 0.012*sl t phl 0.284 0.253 + 0.015*sl 0.261 + 0.013*sl 0.267 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.078 0.051 + 0.013*sl 0.050 + 0.014*sl 0.039 + 0.014*sl t f 0.070 0.045 + 0.012*sl 0.048 + 0.012*sl 0.040 + 0.012*sl t plh 0.329 0.313 + 0.008*sl 0.318 + 0.007*sl 0.324 + 0.006*sl t phl 0.337 0.320 + 0.009*sl 0.327 + 0.007*sl 0.336 + 0.006*sl g to q t r 0.078 0.051 + 0.013*sl 0.050 + 0.013*sl 0.039 + 0.014*sl t f 0.070 0.045 + 0.012*sl 0.048 + 0.012*sl 0.041 + 0.012*sl t plh 0.370 0.354 + 0.008*sl 0.360 + 0.007*sl 0.365 + 0.006*sl t phl 0.381 0.363 + 0.009*sl 0.370 + 0.007*sl 0.379 + 0.006*sl d to qn t r 0.084 0.057 + 0.013*sl 0.057 + 0.013*sl 0.047 + 0.014*sl t f 0.074 0.049 + 0.013*sl 0.052 + 0.012*sl 0.048 + 0.012*sl t plh 0.253 0.236 + 0.009*sl 0.243 + 0.007*sl 0.251 + 0.006*sl t phl 0.242 0.223 + 0.009*sl 0.231 + 0.007*sl 0.244 + 0.006*sl g to qn t r 0.082 0.055 + 0.014*sl 0.056 + 0.013*sl 0.046 + 0.014*sl t f 0.075 0.052 + 0.012*sl 0.051 + 0.012*sl 0.048 + 0.012*sl t plh 0.297 0.280 + 0.009*sl 0.287 + 0.007*sl 0.294 + 0.006*sl t phl 0.284 0.265 + 0.009*sl 0.273 + 0.007*sl 0.285 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-404 samsung asic ld1a/ld1d2a d latch with active high, tri-state output, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) output load (sl) gate count ld1a ld1d2a ld1a ld1d2a ld1a ld1d2a dgedge q q 4.33 4.67 0.8 0.7 1.4 0.6 0.6 1.6 0.9 1.2 parameter symbol value (ns) ld1a ld1d2a input setup time (d to g) t su 0.195 0.197 input hold time (d to g) t hd 0.081 0.074 pulse width high (g) t pwh 0.230 0.233 d g q e d gb gl e q gl gb gl g gb truth table d g e q (n+1) x x 0 hi-z 0110 1111 x 0 1 q (n)
samsung asic 3-405 STD111 ld1a/ld1d2a d latch with active high, tri-state output 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ld1a ld1d2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.117 0.063 + 0.027*sl 0.060 + 0.028*sl 0.055 + 0.028*sl t f 0.114 0.049 + 0.033*sl 0.045 + 0.034*sl 0.042 + 0.034*sl t plh 0.295 0.268 + 0.014*sl 0.272 + 0.013*sl 0.275 + 0.012*sl t phl 0.302 0.269 + 0.017*sl 0.271 + 0.016*sl 0.272 + 0.016*sl g to q t r 0.117 0.063 + 0.027*sl 0.060 + 0.028*sl 0.055 + 0.028*sl t f 0.113 0.048 + 0.033*sl 0.045 + 0.034*sl 0.042 + 0.034*sl t plh 0.339 0.312 + 0.014*sl 0.316 + 0.013*sl 0.319 + 0.012*sl t phl 0.345 0.311 + 0.017*sl 0.313 + 0.016*sl 0.314 + 0.016*sl e to q t r 0.134 0.082 + 0.026*sl 0.071 + 0.029*sl 0.062 + 0.030*sl t f 0.158 0.096 + 0.031*sl 0.088 + 0.033*sl 0.069 + 0.035*sl t plh 0.117 0.089 + 0.014*sl 0.095 + 0.013*sl 0.098 + 0.012*sl t phl 0.070 0.026 + 0.022*sl 0.047 + 0.016*sl 0.048 + 0.016*sl t plz 0.099 0.099 + 0.000*sl 0.099 + 0.000*sl 0.099 + 0.000*sl t phz 0.143 0.143 + 0.000*sl 0.143 + 0.000*sl 0.143 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.087 0.059 + 0.014*sl 0.059 + 0.014*sl 0.053 + 0.014*sl t f 0.078 0.047 + 0.015*sl 0.043 + 0.017*sl 0.035 + 0.017*sl t plh 0.294 0.279 + 0.008*sl 0.283 + 0.007*sl 0.289 + 0.006*sl t phl 0.295 0.277 + 0.009*sl 0.279 + 0.008*sl 0.281 + 0.008*sl g to q t r 0.085 0.058 + 0.014*sl 0.057 + 0.014*sl 0.053 + 0.014*sl t f 0.078 0.047 + 0.016*sl 0.043 + 0.017*sl 0.035 + 0.017*sl t plh 0.336 0.320 + 0.008*sl 0.325 + 0.007*sl 0.331 + 0.006*sl t phl 0.338 0.321 + 0.009*sl 0.323 + 0.008*sl 0.325 + 0.008*sl e to q t r 0.109 0.090 + 0.009*sl 0.074 + 0.014*sl 0.060 + 0.015*sl t f 0.111 0.075 + 0.018*sl 0.085 + 0.016*sl 0.061 + 0.017*sl t plh 0.105 0.087 + 0.009*sl 0.095 + 0.007*sl 0.104 + 0.006*sl t phl 0.036 0.006 + 0.015*sl 0.028 + 0.009*sl 0.042 + 0.008*sl t plz 0.099 0.099 + 0.000*sl 0.099 + 0.000*sl 0.099 + 0.000*sl t phz 0.163 0.163 + 0.000*sl 0.163 + 0.000*sl 0.163 + 0.000*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-406 samsung asic ld1q/ld1qd2 d latch with active high, q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count ld1q ld1qd2 ld1q ld1qd2 dgdg 0.8 0.7 0.8 0.7 3.33 3.67 parameter symbol value (ns) ld1q ld1qd2 input setup time (d to g) t su 0.184 0.189 input hold time (d to g) t hd 0.088 0.082 pulse width high (g) t pwh 0.223 0.226 d g q gl g gb d gb gl gl gb q truth table d g q (n+1) 010 111 x 0 q (n)
samsung asic 3-407 STD111 ld1q/ld1qd2 d latch with active high, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ld1q ld1qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.099 0.046 + 0.027*sl 0.042 + 0.028*sl 0.037 + 0.028*sl t f 0.087 0.041 + 0.023*sl 0.040 + 0.023*sl 0.033 + 0.024*sl t plh 0.257 0.231 + 0.013*sl 0.234 + 0.012*sl 0.235 + 0.012*sl t phl 0.270 0.242 + 0.014*sl 0.247 + 0.013*sl 0.250 + 0.012*sl g to q t r 0.099 0.046 + 0.026*sl 0.041 + 0.028*sl 0.037 + 0.028*sl t f 0.086 0.040 + 0.023*sl 0.041 + 0.023*sl 0.034 + 0.024*sl t plh 0.307 0.280 + 0.013*sl 0.284 + 0.012*sl 0.285 + 0.012*sl t phl 0.315 0.287 + 0.014*sl 0.293 + 0.013*sl 0.295 + 0.012*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.073 0.046 + 0.013*sl 0.044 + 0.014*sl 0.036 + 0.014*sl t f 0.067 0.042 + 0.012*sl 0.045 + 0.011*sl 0.039 + 0.012*sl t plh 0.267 0.251 + 0.008*sl 0.256 + 0.007*sl 0.261 + 0.006*sl t phl 0.273 0.255 + 0.009*sl 0.263 + 0.007*sl 0.272 + 0.006*sl g to q t r 0.072 0.044 + 0.014*sl 0.045 + 0.014*sl 0.037 + 0.014*sl t f 0.067 0.044 + 0.012*sl 0.044 + 0.012*sl 0.039 + 0.012*sl t plh 0.309 0.293 + 0.008*sl 0.298 + 0.007*sl 0.303 + 0.006*sl t phl 0.317 0.299 + 0.009*sl 0.307 + 0.007*sl 0.316 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-408 samsung asic ld2/ld2d2 d latch with active high, reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count ld2 ld2d2 ld2 ld2d2 d g rn d g rn 0.7 0.7 1.0 0.7 0.7 1.0 4.33 4.67 parameter symbol value (ns) ld2 ld2d2 input setup time (d to g) t su 0.253 0.260 input hold time (d to g) t hd 0.011 0.003 pulse width high (g) t pwh 0.238 0.256 pulse width low (rn) t pwl 0.250 0.290 recovery time (rn to g) t rc 0.047 0.070 removal time (rn to g) t rm 0.173 0.150 d g q qn rn gl g gb d gb gl gb q qn rn gl truth table d g rn q (n+1) qn (n+1) 01101 11110 x 0 1 q (n) qn (n) xx001
samsung asic 3-409 STD111 ld2/ld2d2 d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ld2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.115 0.060 + 0.028*sl 0.060 + 0.028*sl 0.054 + 0.028*sl t f 0.098 0.051 + 0.023*sl 0.052 + 0.023*sl 0.046 + 0.024*sl t plh 0.308 0.278 + 0.015*sl 0.285 + 0.013*sl 0.292 + 0.013*sl t phl 0.307 0.276 + 0.015*sl 0.284 + 0.013*sl 0.291 + 0.013*sl g to q t r 0.115 0.059 + 0.028*sl 0.059 + 0.028*sl 0.054 + 0.028*sl t f 0.098 0.051 + 0.024*sl 0.053 + 0.023*sl 0.046 + 0.024*sl t plh 0.300 0.270 + 0.015*sl 0.277 + 0.013*sl 0.284 + 0.013*sl t phl 0.294 0.263 + 0.015*sl 0.271 + 0.013*sl 0.278 + 0.013*sl rn to q t r 0.115 0.060 + 0.028*sl 0.060 + 0.028*sl 0.053 + 0.028*sl t f 0.101 0.054 + 0.023*sl 0.056 + 0.023*sl 0.048 + 0.024*sl t plh 0.151 0.121 + 0.015*sl 0.128 + 0.013*sl 0.134 + 0.013*sl t phl 0.170 0.139 + 0.016*sl 0.147 + 0.013*sl 0.154 + 0.013*sl d to qn t r 0.102 0.048 + 0.027*sl 0.044 + 0.028*sl 0.039 + 0.028*sl t f 0.092 0.047 + 0.023*sl 0.044 + 0.023*sl 0.038 + 0.024*sl t plh 0.360 0.333 + 0.014*sl 0.337 + 0.012*sl 0.338 + 0.012*sl t phl 0.366 0.337 + 0.015*sl 0.344 + 0.013*sl 0.347 + 0.013*sl g to qn t r 0.102 0.048 + 0.027*sl 0.044 + 0.028*sl 0.039 + 0.028*sl t f 0.091 0.046 + 0.023*sl 0.043 + 0.023*sl 0.038 + 0.024*sl t plh 0.347 0.320 + 0.014*sl 0.324 + 0.012*sl 0.325 + 0.012*sl t phl 0.358 0.329 + 0.015*sl 0.336 + 0.013*sl 0.339 + 0.013*sl rn to qn t r 0.103 0.049 + 0.027*sl 0.045 + 0.028*sl 0.040 + 0.028*sl t f 0.091 0.046 + 0.022*sl 0.043 + 0.023*sl 0.038 + 0.024*sl t plh 0.222 0.195 + 0.013*sl 0.199 + 0.012*sl 0.199 + 0.012*sl t phl 0.209 0.180 + 0.015*sl 0.186 + 0.013*sl 0.189 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-410 samsung asic ld2/ld2d2 d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ld2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.088 0.061 + 0.014*sl 0.061 + 0.014*sl 0.056 + 0.014*sl t f 0.077 0.052 + 0.012*sl 0.054 + 0.012*sl 0.051 + 0.012*sl t plh 0.307 0.289 + 0.009*sl 0.297 + 0.007*sl 0.309 + 0.006*sl t phl 0.307 0.288 + 0.010*sl 0.296 + 0.007*sl 0.310 + 0.007*sl g to q t r 0.087 0.059 + 0.014*sl 0.061 + 0.014*sl 0.056 + 0.014*sl t f 0.076 0.051 + 0.013*sl 0.055 + 0.012*sl 0.052 + 0.012*sl t plh 0.305 0.287 + 0.009*sl 0.294 + 0.007*sl 0.306 + 0.006*sl t phl 0.300 0.280 + 0.010*sl 0.289 + 0.007*sl 0.302 + 0.007*sl rn to q t r 0.090 0.065 + 0.012*sl 0.060 + 0.014*sl 0.056 + 0.014*sl t f 0.079 0.053 + 0.013*sl 0.057 + 0.012*sl 0.054 + 0.012*sl t plh 0.150 0.132 + 0.009*sl 0.139 + 0.007*sl 0.152 + 0.006*sl t phl 0.170 0.151 + 0.010*sl 0.159 + 0.007*sl 0.173 + 0.007*sl d to qn t r 0.078 0.051 + 0.013*sl 0.051 + 0.013*sl 0.039 + 0.014*sl t f 0.072 0.047 + 0.013*sl 0.051 + 0.012*sl 0.043 + 0.012*sl t plh 0.395 0.379 + 0.008*sl 0.385 + 0.007*sl 0.390 + 0.006*sl t phl 0.399 0.380 + 0.009*sl 0.388 + 0.007*sl 0.398 + 0.006*sl g to qn t r 0.077 0.051 + 0.013*sl 0.051 + 0.013*sl 0.039 + 0.014*sl t f 0.073 0.049 + 0.012*sl 0.050 + 0.012*sl 0.043 + 0.012*sl t plh 0.388 0.371 + 0.008*sl 0.377 + 0.007*sl 0.383 + 0.006*sl t phl 0.396 0.378 + 0.009*sl 0.385 + 0.007*sl 0.395 + 0.006*sl rn to qn t r 0.078 0.052 + 0.013*sl 0.051 + 0.013*sl 0.039 + 0.014*sl t f 0.072 0.047 + 0.013*sl 0.051 + 0.012*sl 0.043 + 0.012*sl t plh 0.259 0.242 + 0.008*sl 0.248 + 0.007*sl 0.254 + 0.006*sl t phl 0.241 0.223 + 0.009*sl 0.231 + 0.007*sl 0.240 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-411 STD111 ld2q/ld2qd2 d latch with active high, reset, q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count ld2q ld2qd2 ld2q ld2qd2 d g rn d g rn 0.8 0.7 1.0 0.9 0.8 1.0 3.67 3.67 parameter symbol value (ns) ld2q ld2qd2 input setup time (d to g) t su 0.192 0.194 input hold time (d to g) t hd 0.081 0.080 pulse width high (g) t pwh 0.229 0.232 pulse width low (rn) t pwl 0.269 0.285 recovery time (rn to g) t rc 0.000 0.000 removal time (rn to g) t rm 0.337 0.321 d g q rn gl g gb d gb gl gb q rn gl truth table d g rn q (n+1) 0110 1111 x 0 1 q (n) xx00
STD111 3-412 samsung asic ld2q/ld2qd2 d latch with active high, reset, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ld2q ld2qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.107 0.053 + 0.027*sl 0.050 + 0.028*sl 0.044 + 0.028*sl t f 0.092 0.047 + 0.023*sl 0.043 + 0.024*sl 0.038 + 0.024*sl t plh 0.285 0.256 + 0.015*sl 0.263 + 0.013*sl 0.266 + 0.012*sl t phl 0.293 0.263 + 0.015*sl 0.270 + 0.013*sl 0.274 + 0.013*sl g to q t r 0.107 0.053 + 0.027*sl 0.050 + 0.028*sl 0.044 + 0.028*sl t f 0.092 0.047 + 0.023*sl 0.044 + 0.024*sl 0.038 + 0.024*sl t plh 0.327 0.297 + 0.015*sl 0.304 + 0.013*sl 0.308 + 0.012*sl t phl 0.338 0.308 + 0.015*sl 0.315 + 0.013*sl 0.319 + 0.013*sl rn to q t r 0.109 0.055 + 0.027*sl 0.053 + 0.028*sl 0.045 + 0.028*sl t f 0.097 0.053 + 0.022*sl 0.048 + 0.024*sl 0.042 + 0.024*sl t plh 0.135 0.105 + 0.015*sl 0.112 + 0.013*sl 0.116 + 0.012*sl t phl 0.159 0.129 + 0.015*sl 0.137 + 0.013*sl 0.141 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.081 0.053 + 0.014*sl 0.053 + 0.014*sl 0.048 + 0.014*sl t f 0.071 0.044 + 0.013*sl 0.050 + 0.012*sl 0.044 + 0.012*sl t plh 0.289 0.272 + 0.009*sl 0.279 + 0.007*sl 0.289 + 0.006*sl t phl 0.294 0.275 + 0.009*sl 0.283 + 0.007*sl 0.295 + 0.006*sl g to q t r 0.080 0.052 + 0.014*sl 0.053 + 0.014*sl 0.048 + 0.014*sl t f 0.070 0.044 + 0.013*sl 0.049 + 0.012*sl 0.044 + 0.012*sl t plh 0.331 0.314 + 0.009*sl 0.321 + 0.007*sl 0.331 + 0.006*sl t phl 0.339 0.320 + 0.009*sl 0.328 + 0.007*sl 0.340 + 0.006*sl rn to q t r 0.083 0.056 + 0.014*sl 0.056 + 0.014*sl 0.049 + 0.014*sl t f 0.076 0.051 + 0.012*sl 0.054 + 0.012*sl 0.048 + 0.012*sl t plh 0.142 0.124 + 0.009*sl 0.131 + 0.007*sl 0.142 + 0.006*sl t phl 0.161 0.142 + 0.009*sl 0.150 + 0.007*sl 0.162 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-413 STD111 ld3/ld3d2 d latch with active high, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count ld3 ld3d2 ld3 ld3d2 d g sn d g sn 0.8 0.7 1.0 0.8 0.7 1.0 4.00 4.33 parameter symbol value (ns) ld3 ld3d2 input setup time (d to g) t su 0.204 0.218 input hold time (d to g) t hd 0.065 0.047 pulse width high (g) t pwh 0.238 0.253 pulse width low (sn) t pwl 0.250 0.292 recovery time (sn to g) t rc 0.049 0.073 removal time (sn to g) t rm 0.170 0.146 d g q qn sn gl g gb d gb gl gb qn q sn gl truth table d g sn q (n+1) qn (n+1) 01101 11110 x 0 1 q (n) qn (n) xx010
STD111 3-414 samsung asic ld3/ld3d2 d latch with active high, set, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ld3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.102 0.048 + 0.027*sl 0.044 + 0.028*sl 0.039 + 0.028*sl t f 0.091 0.046 + 0.022*sl 0.043 + 0.023*sl 0.038 + 0.024*sl t plh 0.304 0.277 + 0.013*sl 0.281 + 0.012*sl 0.282 + 0.012*sl t phl 0.317 0.287 + 0.015*sl 0.294 + 0.013*sl 0.297 + 0.013*sl g to q t r 0.102 0.049 + 0.027*sl 0.044 + 0.028*sl 0.039 + 0.029*sl t f 0.091 0.047 + 0.022*sl 0.042 + 0.023*sl 0.038 + 0.024*sl t plh 0.345 0.318 + 0.014*sl 0.322 + 0.012*sl 0.323 + 0.012*sl t phl 0.357 0.328 + 0.015*sl 0.334 + 0.013*sl 0.338 + 0.013*sl sn to q t r 0.103 0.049 + 0.027*sl 0.045 + 0.028*sl 0.040 + 0.028*sl t f 0.091 0.047 + 0.022*sl 0.043 + 0.023*sl 0.038 + 0.024*sl t plh 0.222 0.195 + 0.013*sl 0.199 + 0.012*sl 0.199 + 0.012*sl t phl 0.209 0.180 + 0.015*sl 0.186 + 0.013*sl 0.189 + 0.013*sl d to qn t r 0.116 0.061 + 0.028*sl 0.060 + 0.028*sl 0.055 + 0.028*sl t f 0.097 0.049 + 0.024*sl 0.053 + 0.023*sl 0.045 + 0.024*sl t plh 0.258 0.228 + 0.015*sl 0.235 + 0.013*sl 0.242 + 0.013*sl t phl 0.251 0.220 + 0.015*sl 0.228 + 0.013*sl 0.235 + 0.013*sl g to qn t r 0.115 0.059 + 0.028*sl 0.059 + 0.028*sl 0.054 + 0.028*sl t f 0.097 0.051 + 0.023*sl 0.050 + 0.023*sl 0.046 + 0.024*sl t plh 0.299 0.269 + 0.015*sl 0.276 + 0.013*sl 0.283 + 0.013*sl t phl 0.292 0.262 + 0.015*sl 0.269 + 0.013*sl 0.276 + 0.013*sl sn to qn t r 0.115 0.060 + 0.028*sl 0.060 + 0.028*sl 0.053 + 0.028*sl t f 0.101 0.054 + 0.023*sl 0.056 + 0.023*sl 0.048 + 0.024*sl t plh 0.151 0.121 + 0.015*sl 0.128 + 0.013*sl 0.134 + 0.013*sl t phl 0.170 0.139 + 0.016*sl 0.147 + 0.013*sl 0.154 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-415 STD111 ld3/ld3d2 d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ld3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.078 0.052 + 0.013*sl 0.051 + 0.013*sl 0.040 + 0.014*sl t f 0.072 0.047 + 0.013*sl 0.051 + 0.011*sl 0.043 + 0.012*sl t plh 0.341 0.325 + 0.008*sl 0.331 + 0.006*sl 0.336 + 0.006*sl t phl 0.350 0.333 + 0.009*sl 0.340 + 0.007*sl 0.349 + 0.006*sl g to q t r 0.078 0.052 + 0.013*sl 0.050 + 0.013*sl 0.040 + 0.014*sl t f 0.072 0.047 + 0.012*sl 0.051 + 0.012*sl 0.043 + 0.012*sl t plh 0.384 0.368 + 0.008*sl 0.373 + 0.007*sl 0.379 + 0.006*sl t phl 0.392 0.374 + 0.009*sl 0.381 + 0.007*sl 0.391 + 0.006*sl sn to q t r 0.079 0.053 + 0.013*sl 0.052 + 0.013*sl 0.040 + 0.014*sl t f 0.072 0.047 + 0.013*sl 0.052 + 0.011*sl 0.043 + 0.012*sl t plh 0.260 0.244 + 0.008*sl 0.250 + 0.006*sl 0.255 + 0.006*sl t phl 0.240 0.223 + 0.009*sl 0.230 + 0.007*sl 0.239 + 0.006*sl d to qn t r 0.088 0.061 + 0.014*sl 0.061 + 0.014*sl 0.056 + 0.014*sl t f 0.076 0.050 + 0.013*sl 0.055 + 0.012*sl 0.051 + 0.012*sl t plh 0.260 0.242 + 0.009*sl 0.250 + 0.007*sl 0.262 + 0.006*sl t phl 0.254 0.235 + 0.010*sl 0.243 + 0.007*sl 0.257 + 0.007*sl g to qn t r 0.089 0.061 + 0.014*sl 0.062 + 0.014*sl 0.056 + 0.014*sl t f 0.077 0.052 + 0.013*sl 0.055 + 0.012*sl 0.052 + 0.012*sl t plh 0.302 0.283 + 0.009*sl 0.291 + 0.007*sl 0.303 + 0.006*sl t phl 0.297 0.277 + 0.010*sl 0.286 + 0.007*sl 0.299 + 0.007*sl sn to qn t r 0.090 0.066 + 0.012*sl 0.061 + 0.014*sl 0.056 + 0.014*sl t f 0.080 0.054 + 0.013*sl 0.058 + 0.012*sl 0.056 + 0.012*sl t plh 0.150 0.132 + 0.009*sl 0.140 + 0.007*sl 0.152 + 0.006*sl t phl 0.172 0.153 + 0.010*sl 0.161 + 0.007*sl 0.175 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-416 samsung asic ld4/ld4d2 d latch with active high, reset, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count ld4 ld4d2 ld4 ld4d2 d g sn rn d g sn rn 0.7 0.7 1.0 1.0 0.7 0.7 1.0 1.0 5.33 5.67 parameter symbol value (ns) ld4 ld4d2 input setup time (d to g) t su 0.262 0.282 input hold time (d to g) t hd 0.026 0.015 pulse width high (g) t pwh 0.256 0.276 pulse width low (sn) t pwl 0.658 0.705 recovery time (sn to g) t rc 0.000 0.000 removal time (sn to g) t rm 0.599 0.576 pulse width low (rn) t pwl 0.313 0.350 recovery time (rn to g) t rc 0.066 0.081 removal time (rn to g) t rm 0.163 0.149 recovery time (sn to rn) t rc 0.233 0.275 removal time (sn to rn) t rm 0.000 0.000 d g q qn sn rn gl g gb d gb gl gb qn q gl sn rn rn rn sn sn truth table d g rn sn q (n+1) qn (n+1) 011101 111110 x 0 1 1 q (n) qn (n) xx1010 xx0101 xx0010
samsung asic 3-417 STD111 ld4/ld4d2 d latch with active high, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ld4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.102 0.049 + 0.026*sl 0.045 + 0.028*sl 0.039 + 0.028*sl t f 0.090 0.044 + 0.023*sl 0.045 + 0.023*sl 0.037 + 0.024*sl t plh 0.422 0.395 + 0.013*sl 0.399 + 0.012*sl 0.401 + 0.012*sl t phl 0.431 0.402 + 0.015*sl 0.408 + 0.013*sl 0.412 + 0.012*sl g to q t r 0.102 0.050 + 0.026*sl 0.044 + 0.028*sl 0.039 + 0.028*sl t f 0.090 0.044 + 0.023*sl 0.044 + 0.023*sl 0.038 + 0.024*sl t plh 0.418 0.391 + 0.014*sl 0.395 + 0.012*sl 0.397 + 0.012*sl t phl 0.417 0.388 + 0.015*sl 0.395 + 0.013*sl 0.398 + 0.012*sl sn to q t r 0.102 0.049 + 0.026*sl 0.045 + 0.028*sl 0.039 + 0.028*sl t f 0.091 0.046 + 0.023*sl 0.045 + 0.023*sl 0.038 + 0.024*sl t plh 0.230 0.203 + 0.014*sl 0.208 + 0.012*sl 0.208 + 0.012*sl t phl 0.212 0.183 + 0.015*sl 0.190 + 0.013*sl 0.193 + 0.012*sl rn to q t r 0.102 0.050 + 0.026*sl 0.044 + 0.028*sl 0.038 + 0.028*sl t f 0.091 0.045 + 0.023*sl 0.045 + 0.023*sl 0.038 + 0.024*sl t plh 0.266 0.239 + 0.014*sl 0.243 + 0.012*sl 0.245 + 0.012*sl t phl 0.291 0.261 + 0.015*sl 0.268 + 0.013*sl 0.272 + 0.012*sl d to qn t r 0.112 0.057 + 0.027*sl 0.057 + 0.027*sl 0.052 + 0.028*sl t f 0.097 0.050 + 0.023*sl 0.052 + 0.023*sl 0.046 + 0.023*sl t plh 0.368 0.338 + 0.015*sl 0.345 + 0.013*sl 0.352 + 0.012*sl t phl 0.364 0.334 + 0.015*sl 0.342 + 0.013*sl 0.349 + 0.012*sl g to qn t r 0.112 0.057 + 0.027*sl 0.058 + 0.027*sl 0.052 + 0.028*sl t f 0.097 0.051 + 0.023*sl 0.051 + 0.023*sl 0.046 + 0.023*sl t plh 0.355 0.325 + 0.015*sl 0.332 + 0.013*sl 0.339 + 0.012*sl t phl 0.360 0.329 + 0.015*sl 0.337 + 0.013*sl 0.345 + 0.012*sl sn to qn t r 0.113 0.060 + 0.027*sl 0.059 + 0.027*sl 0.053 + 0.028*sl t f 0.100 0.055 + 0.023*sl 0.055 + 0.023*sl 0.049 + 0.023*sl t plh 0.150 0.120 + 0.015*sl 0.127 + 0.013*sl 0.133 + 0.012*sl t phl 0.172 0.141 + 0.016*sl 0.149 + 0.013*sl 0.157 + 0.012*sl rn to qn t r 0.112 0.058 + 0.027*sl 0.058 + 0.027*sl 0.052 + 0.028*sl t f 0.097 0.050 + 0.023*sl 0.052 + 0.023*sl 0.046 + 0.023*sl t plh 0.228 0.198 + 0.015*sl 0.205 + 0.013*sl 0.212 + 0.012*sl t phl 0.208 0.178 + 0.015*sl 0.186 + 0.013*sl 0.193 + 0.012*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-418 samsung asic ld4/ld4d2 d latch with active high, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ld4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.080 0.054 + 0.013*sl 0.053 + 0.013*sl 0.042 + 0.014*sl t f 0.073 0.048 + 0.012*sl 0.052 + 0.011*sl 0.046 + 0.012*sl t plh 0.464 0.448 + 0.008*sl 0.454 + 0.007*sl 0.460 + 0.006*sl t phl 0.466 0.448 + 0.009*sl 0.456 + 0.007*sl 0.466 + 0.006*sl g to q t r 0.080 0.054 + 0.013*sl 0.053 + 0.013*sl 0.042 + 0.014*sl t f 0.073 0.049 + 0.012*sl 0.052 + 0.011*sl 0.045 + 0.012*sl t plh 0.463 0.446 + 0.008*sl 0.452 + 0.007*sl 0.458 + 0.006*sl t phl 0.454 0.437 + 0.009*sl 0.444 + 0.007*sl 0.455 + 0.006*sl sn to q t r 0.080 0.054 + 0.013*sl 0.052 + 0.013*sl 0.042 + 0.014*sl t f 0.073 0.048 + 0.013*sl 0.053 + 0.011*sl 0.046 + 0.012*sl t plh 0.265 0.249 + 0.008*sl 0.255 + 0.007*sl 0.261 + 0.006*sl t phl 0.247 0.229 + 0.009*sl 0.236 + 0.007*sl 0.247 + 0.006*sl rn to q t r 0.080 0.054 + 0.013*sl 0.053 + 0.013*sl 0.042 + 0.014*sl t f 0.075 0.051 + 0.012*sl 0.052 + 0.011*sl 0.045 + 0.012*sl t plh 0.301 0.285 + 0.008*sl 0.291 + 0.007*sl 0.297 + 0.006*sl t phl 0.325 0.307 + 0.009*sl 0.315 + 0.007*sl 0.325 + 0.006*sl d to qn t r 0.086 0.059 + 0.014*sl 0.060 + 0.014*sl 0.055 + 0.014*sl t f 0.076 0.051 + 0.013*sl 0.055 + 0.012*sl 0.052 + 0.012*sl t plh 0.372 0.354 + 0.009*sl 0.361 + 0.007*sl 0.373 + 0.006*sl t phl 0.372 0.353 + 0.009*sl 0.361 + 0.007*sl 0.375 + 0.006*sl g to qn t r 0.087 0.058 + 0.014*sl 0.060 + 0.014*sl 0.056 + 0.014*sl t f 0.077 0.054 + 0.011*sl 0.053 + 0.012*sl 0.051 + 0.012*sl t plh 0.360 0.342 + 0.009*sl 0.350 + 0.007*sl 0.362 + 0.006*sl t phl 0.370 0.351 + 0.009*sl 0.359 + 0.007*sl 0.373 + 0.006*sl sn to qn t r 0.088 0.060 + 0.014*sl 0.061 + 0.014*sl 0.057 + 0.014*sl t f 0.080 0.055 + 0.012*sl 0.059 + 0.011*sl 0.055 + 0.012*sl t plh 0.152 0.134 + 0.009*sl 0.141 + 0.007*sl 0.153 + 0.006*sl t phl 0.173 0.154 + 0.010*sl 0.162 + 0.007*sl 0.176 + 0.006*sl rn to qn t r 0.087 0.058 + 0.014*sl 0.061 + 0.014*sl 0.056 + 0.014*sl t f 0.076 0.051 + 0.013*sl 0.055 + 0.012*sl 0.052 + 0.012*sl t plh 0.231 0.213 + 0.009*sl 0.221 + 0.007*sl 0.232 + 0.006*sl t phl 0.209 0.190 + 0.009*sl 0.198 + 0.007*sl 0.212 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-419 STD111 ld5/ld5d2 d latch with active low, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count ld5 ld5d2 ld5 ld5d2 dgndgn 0.9 0.7 0.9 0.7 4.00 4.00 parameter symbol value (ns) ld5 ld5d2 input setup time (d to gn) t su 0.189 0.201 input hold time (d to gn) t hd 0.058 0.039 pulse width low (gn) t pwl 0.217 0.234 d gn q qn qn q d gnb gln gln gnb gln gn gnb truth table d gn q (n+1) qn (n+1) 0001 1010 x 1 q (n) qn (n)
STD111 3-420 samsung asic ld5/ld5d2 d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ld5 ld5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.101 0.047 + 0.027*sl 0.042 + 0.028*sl 0.037 + 0.029*sl t f 0.089 0.043 + 0.023*sl 0.040 + 0.024*sl 0.035 + 0.024*sl t plh 0.291 0.264 + 0.014*sl 0.267 + 0.012*sl 0.268 + 0.012*sl t phl 0.303 0.274 + 0.015*sl 0.280 + 0.013*sl 0.283 + 0.013*sl gn to q t r 0.101 0.048 + 0.027*sl 0.042 + 0.028*sl 0.037 + 0.029*sl t f 0.089 0.042 + 0.023*sl 0.041 + 0.024*sl 0.035 + 0.024*sl t plh 0.321 0.294 + 0.014*sl 0.298 + 0.012*sl 0.299 + 0.012*sl t phl 0.358 0.329 + 0.015*sl 0.335 + 0.013*sl 0.338 + 0.013*sl d to qn t r 0.109 0.056 + 0.027*sl 0.053 + 0.028*sl 0.045 + 0.028*sl t f 0.097 0.050 + 0.023*sl 0.049 + 0.024*sl 0.043 + 0.024*sl t plh 0.247 0.219 + 0.014*sl 0.224 + 0.013*sl 0.227 + 0.012*sl t phl 0.240 0.209 + 0.015*sl 0.217 + 0.013*sl 0.223 + 0.013*sl gn to qn t r 0.109 0.056 + 0.027*sl 0.051 + 0.028*sl 0.045 + 0.028*sl t f 0.096 0.049 + 0.023*sl 0.048 + 0.024*sl 0.043 + 0.024*sl t plh 0.302 0.274 + 0.014*sl 0.279 + 0.013*sl 0.282 + 0.012*sl t phl 0.271 0.240 + 0.015*sl 0.248 + 0.013*sl 0.254 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.078 0.051 + 0.013*sl 0.050 + 0.014*sl 0.039 + 0.014*sl t f 0.070 0.045 + 0.012*sl 0.048 + 0.012*sl 0.040 + 0.012*sl t plh 0.329 0.313 + 0.008*sl 0.319 + 0.007*sl 0.324 + 0.006*sl t phl 0.338 0.320 + 0.009*sl 0.327 + 0.007*sl 0.336 + 0.006*sl gn to q t r 0.078 0.051 + 0.013*sl 0.050 + 0.014*sl 0.039 + 0.014*sl t f 0.070 0.045 + 0.013*sl 0.049 + 0.012*sl 0.040 + 0.012*sl t plh 0.364 0.348 + 0.008*sl 0.353 + 0.007*sl 0.359 + 0.006*sl t phl 0.393 0.375 + 0.009*sl 0.383 + 0.007*sl 0.392 + 0.006*sl d to qn t r 0.084 0.057 + 0.013*sl 0.057 + 0.013*sl 0.047 + 0.014*sl t f 0.075 0.050 + 0.012*sl 0.052 + 0.012*sl 0.049 + 0.012*sl t plh 0.254 0.237 + 0.009*sl 0.243 + 0.007*sl 0.251 + 0.006*sl t phl 0.243 0.224 + 0.009*sl 0.232 + 0.007*sl 0.244 + 0.006*sl gn to qn t r 0.083 0.057 + 0.013*sl 0.056 + 0.013*sl 0.046 + 0.014*sl t f 0.074 0.049 + 0.013*sl 0.053 + 0.012*sl 0.049 + 0.012*sl t plh 0.309 0.292 + 0.009*sl 0.299 + 0.007*sl 0.306 + 0.006*sl t phl 0.277 0.259 + 0.009*sl 0.267 + 0.007*sl 0.279 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-421 STD111 ld5q/ld5qd2 d latch with active low, q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count ld5q ld5qd2 ld5q ld5qd2 dgndgn 0.9 0.7 0.9 0.7 3.33 3.67 parameter symbol value (ns) ld5q ld5qd2 input setup time (d to gn) t su 0.179 0.184 input hold time (d to gn) t hd 0.074 0.066 pulse width low (gn) t pwl 0.208 0.212 d gn q q d gnb gln gln gnb gln gn gnb truth table d gn q (n+1) 000 101 x 1 q (n)
STD111 3-422 samsung asic ld5q/ld5qd2 d latch with active low, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ld5q ld5qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.099 0.045 + 0.027*sl 0.042 + 0.028*sl 0.037 + 0.028*sl t f 0.087 0.042 + 0.023*sl 0.040 + 0.023*sl 0.033 + 0.024*sl t plh 0.258 0.231 + 0.013*sl 0.235 + 0.012*sl 0.236 + 0.012*sl t phl 0.270 0.242 + 0.014*sl 0.248 + 0.013*sl 0.250 + 0.012*sl gn to q t r 0.099 0.045 + 0.027*sl 0.042 + 0.028*sl 0.037 + 0.028*sl t f 0.088 0.043 + 0.022*sl 0.039 + 0.023*sl 0.035 + 0.024*sl t plh 0.294 0.267 + 0.013*sl 0.270 + 0.012*sl 0.271 + 0.012*sl t phl 0.327 0.298 + 0.014*sl 0.304 + 0.013*sl 0.306 + 0.012*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.073 0.046 + 0.013*sl 0.044 + 0.014*sl 0.037 + 0.014*sl t f 0.067 0.043 + 0.012*sl 0.044 + 0.012*sl 0.039 + 0.012*sl t plh 0.272 0.256 + 0.008*sl 0.261 + 0.007*sl 0.266 + 0.006*sl t phl 0.276 0.258 + 0.009*sl 0.265 + 0.007*sl 0.274 + 0.006*sl gn to q t r 0.073 0.046 + 0.014*sl 0.046 + 0.014*sl 0.037 + 0.014*sl t f 0.067 0.044 + 0.012*sl 0.044 + 0.012*sl 0.039 + 0.012*sl t plh 0.307 0.291 + 0.008*sl 0.296 + 0.007*sl 0.301 + 0.006*sl t phl 0.332 0.314 + 0.009*sl 0.321 + 0.007*sl 0.330 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-423 STD111 ld6/ld6d2 d latch with active low, reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count ld6 ld6d2 ld6 ld6d2 d gn rn d gn rn 0.7 0.7 1.0 0.7 0.7 1.0 4.33 4.67 parameter symbol value (ns) ld6 ld6d2 input setup time (d to gn) t su 0.252 0.260 input hold time (d to gn) t hd 0.007 0.000 pulse width low (gn) t pwl 0.220 0.233 pulse width low (rn) t pwl 0.252 0.291 recovery time (rn to gn) t rc 0.025 0.046 removal time (rn to gn) t rm 0.195 0.174 d gn q qn rn gln gn gnb rn rn d gnb gln q rn gln gnb qn truth table d gn rn q (n+1) qn (n+1) 00101 10110 x 1 1 q (n) qn (n) xx001
STD111 3-424 samsung asic ld6/ld6d2 d latch with active low, reset, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ld6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.116 0.061 + 0.028*sl 0.060 + 0.028*sl 0.055 + 0.028*sl t f 0.097 0.049 + 0.024*sl 0.053 + 0.023*sl 0.046 + 0.024*sl t plh 0.309 0.279 + 0.015*sl 0.285 + 0.013*sl 0.292 + 0.013*sl t phl 0.307 0.277 + 0.015*sl 0.284 + 0.013*sl 0.291 + 0.013*sl gn to q t r 0.115 0.060 + 0.028*sl 0.060 + 0.028*sl 0.055 + 0.028*sl t f 0.097 0.051 + 0.023*sl 0.050 + 0.023*sl 0.046 + 0.024*sl t plh 0.313 0.283 + 0.015*sl 0.290 + 0.013*sl 0.297 + 0.013*sl t phl 0.283 0.253 + 0.015*sl 0.260 + 0.013*sl 0.267 + 0.013*sl rn to q t r 0.115 0.060 + 0.027*sl 0.060 + 0.028*sl 0.053 + 0.028*sl t f 0.101 0.054 + 0.023*sl 0.056 + 0.023*sl 0.049 + 0.024*sl t plh 0.150 0.120 + 0.015*sl 0.127 + 0.013*sl 0.133 + 0.013*sl t phl 0.170 0.139 + 0.015*sl 0.147 + 0.013*sl 0.154 + 0.013*sl d to qn t r 0.102 0.049 + 0.027*sl 0.045 + 0.028*sl 0.039 + 0.028*sl t f 0.092 0.047 + 0.022*sl 0.044 + 0.023*sl 0.038 + 0.024*sl t plh 0.360 0.333 + 0.014*sl 0.337 + 0.012*sl 0.338 + 0.012*sl t phl 0.367 0.338 + 0.015*sl 0.345 + 0.013*sl 0.348 + 0.013*sl gn to qn t r 0.102 0.049 + 0.027*sl 0.044 + 0.028*sl 0.039 + 0.028*sl t f 0.092 0.047 + 0.022*sl 0.043 + 0.023*sl 0.038 + 0.024*sl t plh 0.337 0.309 + 0.014*sl 0.314 + 0.012*sl 0.315 + 0.012*sl t phl 0.372 0.343 + 0.015*sl 0.350 + 0.013*sl 0.353 + 0.013*sl rn to qn t r 0.104 0.051 + 0.027*sl 0.046 + 0.028*sl 0.040 + 0.028*sl t f 0.092 0.047 + 0.023*sl 0.044 + 0.023*sl 0.038 + 0.024*sl t plh 0.222 0.195 + 0.013*sl 0.199 + 0.012*sl 0.200 + 0.012*sl t phl 0.209 0.180 + 0.015*sl 0.186 + 0.013*sl 0.189 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-425 STD111 ld6/ld6d2 d latch with active low, reset, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ld6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.089 0.061 + 0.014*sl 0.062 + 0.013*sl 0.056 + 0.014*sl t f 0.077 0.053 + 0.012*sl 0.054 + 0.012*sl 0.051 + 0.012*sl t plh 0.307 0.289 + 0.009*sl 0.297 + 0.007*sl 0.309 + 0.006*sl t phl 0.307 0.288 + 0.010*sl 0.296 + 0.007*sl 0.310 + 0.007*sl gn to q t r 0.089 0.062 + 0.014*sl 0.062 + 0.013*sl 0.056 + 0.014*sl t f 0.077 0.054 + 0.012*sl 0.053 + 0.012*sl 0.051 + 0.012*sl t plh 0.317 0.299 + 0.009*sl 0.306 + 0.007*sl 0.319 + 0.006*sl t phl 0.286 0.267 + 0.010*sl 0.275 + 0.007*sl 0.289 + 0.007*sl rn to q t r 0.090 0.065 + 0.012*sl 0.060 + 0.014*sl 0.056 + 0.014*sl t f 0.079 0.053 + 0.013*sl 0.057 + 0.012*sl 0.054 + 0.012*sl t plh 0.150 0.132 + 0.009*sl 0.140 + 0.007*sl 0.152 + 0.006*sl t phl 0.170 0.151 + 0.010*sl 0.160 + 0.007*sl 0.173 + 0.007*sl d to qn t r 0.078 0.052 + 0.013*sl 0.051 + 0.013*sl 0.039 + 0.014*sl t f 0.072 0.047 + 0.012*sl 0.051 + 0.012*sl 0.043 + 0.012*sl t plh 0.395 0.379 + 0.008*sl 0.385 + 0.007*sl 0.390 + 0.006*sl t phl 0.399 0.381 + 0.009*sl 0.388 + 0.007*sl 0.398 + 0.006*sl gn to qn t r 0.078 0.052 + 0.013*sl 0.051 + 0.013*sl 0.040 + 0.014*sl t f 0.072 0.047 + 0.012*sl 0.051 + 0.012*sl 0.043 + 0.012*sl t plh 0.374 0.358 + 0.008*sl 0.364 + 0.007*sl 0.370 + 0.006*sl t phl 0.408 0.390 + 0.009*sl 0.398 + 0.007*sl 0.407 + 0.006*sl rn to qn t r 0.078 0.052 + 0.013*sl 0.051 + 0.013*sl 0.039 + 0.014*sl t f 0.072 0.047 + 0.013*sl 0.052 + 0.012*sl 0.043 + 0.012*sl t plh 0.259 0.243 + 0.008*sl 0.248 + 0.007*sl 0.254 + 0.006*sl t phl 0.241 0.223 + 0.009*sl 0.231 + 0.007*sl 0.241 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-426 samsung asic ld6q/ld6qd2 d latch with active low, reset, q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c,2.5v, unit = ns) input load (sl) gate count ld6q ld6qd2 ld6q ld6qd2 d gn rn d gn rn 0.9 0.7 1.0 0.9 0.8 1.0 3.67 3.67 parameter symbol value (ns) ld6q ld6qd2 input setup time (d to gn) t su 0.182 0.184 input hold time (d to gn) t hd 0.062 0.060 pulse width low (gn) t pwl 0.212 0.213 pulse width low (rn) t pwl 0.269 0.286 recovery time (rn to gn) t rc 0.000 0.000 removal time (rn to gn) t rm 0.329 0.316 d gn q rn gln gn gnb rn rn d gnb gln q rn gln gnb truth table d gn rn q (n+1) 0010 1011 x 1 1 q (n) xx00
samsung asic 3-427 STD111 ld6q/ld6qd2 d latch with active low, reset, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ld6q ld6qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.107 0.053 + 0.027*sl 0.050 + 0.028*sl 0.044 + 0.028*sl t f 0.092 0.047 + 0.023*sl 0.043 + 0.024*sl 0.038 + 0.024*sl t plh 0.285 0.256 + 0.015*sl 0.263 + 0.013*sl 0.266 + 0.012*sl t phl 0.293 0.263 + 0.015*sl 0.270 + 0.013*sl 0.274 + 0.013*sl gn to q t r 0.107 0.052 + 0.027*sl 0.051 + 0.028*sl 0.044 + 0.028*sl t f 0.092 0.046 + 0.023*sl 0.045 + 0.024*sl 0.038 + 0.024*sl t plh 0.318 0.289 + 0.015*sl 0.296 + 0.013*sl 0.299 + 0.012*sl t phl 0.347 0.317 + 0.015*sl 0.325 + 0.013*sl 0.328 + 0.013*sl rn to q t r 0.109 0.055 + 0.027*sl 0.053 + 0.028*sl 0.045 + 0.028*sl t f 0.097 0.053 + 0.022*sl 0.048 + 0.024*sl 0.042 + 0.024*sl t plh 0.135 0.105 + 0.015*sl 0.112 + 0.013*sl 0.116 + 0.012*sl t phl 0.159 0.129 + 0.015*sl 0.137 + 0.013*sl 0.141 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.081 0.053 + 0.014*sl 0.053 + 0.014*sl 0.048 + 0.014*sl t f 0.070 0.044 + 0.013*sl 0.050 + 0.012*sl 0.044 + 0.012*sl t plh 0.289 0.272 + 0.009*sl 0.279 + 0.007*sl 0.289 + 0.006*sl t phl 0.294 0.275 + 0.009*sl 0.283 + 0.007*sl 0.295 + 0.006*sl gn to q t r 0.080 0.052 + 0.014*sl 0.053 + 0.014*sl 0.048 + 0.014*sl t f 0.070 0.043 + 0.013*sl 0.050 + 0.012*sl 0.044 + 0.012*sl t plh 0.323 0.305 + 0.009*sl 0.312 + 0.007*sl 0.323 + 0.006*sl t phl 0.347 0.329 + 0.009*sl 0.337 + 0.007*sl 0.348 + 0.006*sl rn to q t r 0.083 0.056 + 0.014*sl 0.057 + 0.014*sl 0.048 + 0.014*sl t f 0.075 0.051 + 0.012*sl 0.053 + 0.012*sl 0.048 + 0.012*sl t plh 0.141 0.124 + 0.009*sl 0.131 + 0.007*sl 0.141 + 0.006*sl t phl 0.160 0.142 + 0.009*sl 0.150 + 0.007*sl 0.162 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-428 samsung asic ld7/ld7d2 d latch with active low, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count ld7 ld7d2 ld7 ld7d2 d gn sn d gn sn 0.8 0.7 1.0 0.9 0.7 1.0 4.00 4.33 parameter symbol value (ns) ld7 ld7d2 input setup time (d to gn) t su 0.197 0.209 input hold time (d to gn) t hd 0.054 0.039 pulse width low (gn) t pwl 0.220 0.234 pulse width low (sn) t pwl 0.252 0.292 recovery time (sn to gn) t rc 0.028 0.052 removal time (sn to gn) t rm 0.192 0.168 d gn q qn sn gln gn gnb sn sn d gnb gln qn sn gln gnb q truth table d gn sn q (n+1) qn (n+1) 00101 10110 x 1 1 q (n) qn (n) xx010
samsung asic 3-429 STD111 ld7/ld7d2 d latch with active low, set, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ld7 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.102 0.048 + 0.027*sl 0.044 + 0.028*sl 0.039 + 0.028*sl t f 0.091 0.046 + 0.023*sl 0.043 + 0.023*sl 0.038 + 0.024*sl t plh 0.304 0.277 + 0.014*sl 0.281 + 0.012*sl 0.282 + 0.012*sl t phl 0.317 0.288 + 0.015*sl 0.295 + 0.013*sl 0.298 + 0.013*sl gn to q t r 0.102 0.049 + 0.026*sl 0.043 + 0.028*sl 0.038 + 0.029*sl t f 0.091 0.044 + 0.023*sl 0.045 + 0.023*sl 0.037 + 0.024*sl t plh 0.335 0.308 + 0.014*sl 0.312 + 0.012*sl 0.313 + 0.012*sl t phl 0.371 0.342 + 0.015*sl 0.348 + 0.013*sl 0.351 + 0.013*sl sn to q t r 0.103 0.050 + 0.027*sl 0.045 + 0.028*sl 0.039 + 0.028*sl t f 0.091 0.047 + 0.022*sl 0.043 + 0.023*sl 0.038 + 0.024*sl t plh 0.222 0.195 + 0.013*sl 0.199 + 0.012*sl 0.199 + 0.012*sl t phl 0.208 0.179 + 0.015*sl 0.186 + 0.013*sl 0.189 + 0.013*sl d to qn t r 0.116 0.061 + 0.027*sl 0.060 + 0.028*sl 0.055 + 0.028*sl t f 0.097 0.049 + 0.024*sl 0.053 + 0.023*sl 0.046 + 0.024*sl t plh 0.259 0.229 + 0.015*sl 0.236 + 0.013*sl 0.242 + 0.013*sl t phl 0.251 0.221 + 0.015*sl 0.228 + 0.013*sl 0.235 + 0.013*sl gn to qn t r 0.115 0.060 + 0.028*sl 0.060 + 0.028*sl 0.054 + 0.028*sl t f 0.097 0.051 + 0.023*sl 0.050 + 0.023*sl 0.046 + 0.024*sl t plh 0.312 0.282 + 0.015*sl 0.289 + 0.013*sl 0.296 + 0.013*sl t phl 0.282 0.252 + 0.015*sl 0.259 + 0.013*sl 0.266 + 0.013*sl sn to qn t r 0.115 0.060 + 0.027*sl 0.060 + 0.028*sl 0.054 + 0.028*sl t f 0.101 0.054 + 0.023*sl 0.056 + 0.023*sl 0.048 + 0.024*sl t plh 0.150 0.120 + 0.015*sl 0.127 + 0.013*sl 0.133 + 0.013*sl t phl 0.169 0.138 + 0.015*sl 0.147 + 0.013*sl 0.154 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-430 samsung asic ld7/ld7d2 d latch with active low, set, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ld7d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.078 0.052 + 0.013*sl 0.051 + 0.013*sl 0.040 + 0.014*sl t f 0.072 0.046 + 0.013*sl 0.051 + 0.011*sl 0.043 + 0.012*sl t plh 0.341 0.325 + 0.008*sl 0.331 + 0.006*sl 0.336 + 0.006*sl t phl 0.350 0.332 + 0.009*sl 0.340 + 0.007*sl 0.349 + 0.006*sl gn to q t r 0.078 0.052 + 0.013*sl 0.051 + 0.013*sl 0.040 + 0.014*sl t f 0.072 0.047 + 0.012*sl 0.051 + 0.012*sl 0.043 + 0.012*sl t plh 0.372 0.356 + 0.008*sl 0.362 + 0.006*sl 0.367 + 0.006*sl t phl 0.404 0.386 + 0.009*sl 0.394 + 0.007*sl 0.403 + 0.006*sl sn to q t r 0.079 0.053 + 0.013*sl 0.052 + 0.013*sl 0.040 + 0.014*sl t f 0.072 0.047 + 0.013*sl 0.051 + 0.011*sl 0.043 + 0.012*sl t plh 0.260 0.244 + 0.008*sl 0.249 + 0.006*sl 0.255 + 0.006*sl t phl 0.240 0.222 + 0.009*sl 0.229 + 0.007*sl 0.239 + 0.006*sl d to qn t r 0.088 0.061 + 0.014*sl 0.061 + 0.014*sl 0.056 + 0.014*sl t f 0.076 0.050 + 0.013*sl 0.055 + 0.012*sl 0.051 + 0.012*sl t plh 0.260 0.242 + 0.009*sl 0.250 + 0.007*sl 0.262 + 0.006*sl t phl 0.254 0.235 + 0.010*sl 0.243 + 0.007*sl 0.257 + 0.007*sl gn to qn t r 0.088 0.061 + 0.014*sl 0.061 + 0.014*sl 0.057 + 0.014*sl t f 0.077 0.051 + 0.013*sl 0.055 + 0.012*sl 0.052 + 0.012*sl t plh 0.314 0.296 + 0.009*sl 0.304 + 0.007*sl 0.316 + 0.006*sl t phl 0.285 0.266 + 0.010*sl 0.275 + 0.007*sl 0.288 + 0.007*sl sn to qn t r 0.090 0.066 + 0.012*sl 0.061 + 0.014*sl 0.056 + 0.014*sl t f 0.080 0.054 + 0.013*sl 0.058 + 0.012*sl 0.056 + 0.012*sl t plh 0.150 0.132 + 0.009*sl 0.140 + 0.007*sl 0.152 + 0.006*sl t phl 0.172 0.153 + 0.010*sl 0.161 + 0.007*sl 0.175 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-431 STD111 ld8/ld8d2 d latch with active low, reset, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c,2.5v, unit = ns) input load (sl) gate count ld8 ld8d2 ld8 ld8d2 d gn sn rn d gn sn rn 0.7 0.7 1.0 1.0 0.7 0.7 0.9 1.0 5.33 5.67 parameter symbol value (ns) ld8 ld8d2 input setup time (d to gn) t su 0.252 0.259 input hold time (d to gn) t hd 0.000 0.000 pulse width low (gn) t pwl 0.231 0.252 pulse width low (sn) t pwl 0.657 0.706 recovery time (sn to gn) t rc 0.000 0.000 removal time (sn to gn) t rm 0.523 0.522 pulse width low (rn) t pwl 0.313 0.350 recovery time (rn to gn) t rc 0.027 0.054 removal time (rn to gn) t rm 0.198 0.172 recovery time (sn to rn) t rc 0.233 0.275 removal time (sn to rn) t rm 0.000 0.000 d gn q qn rn sn gln gn gnb rn rn d gnb gln qn rn gln gnb q sn sn sn truth table dgnrnsn q (n+1) qn (n+1) 001101 101110 x 1 1 1 q (n) qn (n) xx1010 xx0101 xx0010
STD111 3-432 samsung asic ld8/ld8d2 d latch with active low, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ld8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.102 0.049 + 0.026*sl 0.045 + 0.028*sl 0.039 + 0.028*sl t f 0.090 0.043 + 0.023*sl 0.044 + 0.023*sl 0.038 + 0.024*sl t plh 0.422 0.395 + 0.013*sl 0.400 + 0.012*sl 0.401 + 0.012*sl t phl 0.431 0.402 + 0.015*sl 0.408 + 0.013*sl 0.412 + 0.012*sl gn to q t r 0.102 0.049 + 0.027*sl 0.045 + 0.028*sl 0.039 + 0.028*sl t f 0.090 0.044 + 0.023*sl 0.044 + 0.023*sl 0.038 + 0.024*sl t plh 0.430 0.403 + 0.013*sl 0.407 + 0.012*sl 0.409 + 0.012*sl t phl 0.406 0.377 + 0.015*sl 0.384 + 0.013*sl 0.387 + 0.012*sl sn to q t r 0.102 0.049 + 0.026*sl 0.045 + 0.028*sl 0.039 + 0.028*sl t f 0.091 0.046 + 0.023*sl 0.045 + 0.023*sl 0.038 + 0.024*sl t plh 0.230 0.203 + 0.014*sl 0.208 + 0.012*sl 0.208 + 0.012*sl t phl 0.212 0.183 + 0.015*sl 0.190 + 0.013*sl 0.193 + 0.012*sl rn to q t r 0.102 0.050 + 0.026*sl 0.044 + 0.028*sl 0.038 + 0.028*sl t f 0.091 0.045 + 0.023*sl 0.045 + 0.023*sl 0.038 + 0.024*sl t plh 0.266 0.239 + 0.014*sl 0.243 + 0.012*sl 0.245 + 0.012*sl t phl 0.291 0.261 + 0.015*sl 0.268 + 0.013*sl 0.272 + 0.012*sl d to qn t r 0.112 0.057 + 0.028*sl 0.058 + 0.027*sl 0.052 + 0.028*sl t f 0.097 0.050 + 0.023*sl 0.052 + 0.023*sl 0.046 + 0.023*sl t plh 0.368 0.338 + 0.015*sl 0.345 + 0.013*sl 0.352 + 0.012*sl t phl 0.365 0.334 + 0.015*sl 0.342 + 0.013*sl 0.349 + 0.012*sl gn to qn t r 0.112 0.057 + 0.027*sl 0.058 + 0.027*sl 0.052 + 0.028*sl t f 0.097 0.050 + 0.023*sl 0.052 + 0.023*sl 0.046 + 0.023*sl t plh 0.344 0.314 + 0.015*sl 0.321 + 0.013*sl 0.328 + 0.012*sl t phl 0.372 0.341 + 0.015*sl 0.350 + 0.013*sl 0.357 + 0.012*sl sn to qn t r 0.113 0.060 + 0.027*sl 0.059 + 0.027*sl 0.053 + 0.028*sl t f 0.100 0.054 + 0.023*sl 0.055 + 0.023*sl 0.049 + 0.023*sl t plh 0.150 0.120 + 0.015*sl 0.127 + 0.013*sl 0.133 + 0.012*sl t phl 0.172 0.141 + 0.016*sl 0.149 + 0.013*sl 0.157 + 0.012*sl rn to qn t r 0.112 0.058 + 0.027*sl 0.058 + 0.027*sl 0.052 + 0.028*sl t f 0.097 0.050 + 0.023*sl 0.052 + 0.023*sl 0.046 + 0.023*sl t plh 0.228 0.198 + 0.015*sl 0.205 + 0.013*sl 0.212 + 0.012*sl t phl 0.208 0.178 + 0.015*sl 0.186 + 0.013*sl 0.193 + 0.012*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-433 STD111 ld8/ld8d2 d latch with active low, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ld8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t r 0.080 0.054 + 0.013*sl 0.053 + 0.013*sl 0.042 + 0.014*sl t f 0.073 0.048 + 0.013*sl 0.052 + 0.011*sl 0.045 + 0.012*sl t plh 0.462 0.446 + 0.008*sl 0.451 + 0.007*sl 0.457 + 0.006*sl t phl 0.470 0.452 + 0.009*sl 0.459 + 0.007*sl 0.470 + 0.006*sl gn to q t r 0.080 0.054 + 0.013*sl 0.053 + 0.013*sl 0.042 + 0.014*sl t f 0.073 0.049 + 0.012*sl 0.052 + 0.011*sl 0.045 + 0.012*sl t plh 0.469 0.453 + 0.008*sl 0.459 + 0.007*sl 0.465 + 0.006*sl t phl 0.452 0.434 + 0.009*sl 0.442 + 0.007*sl 0.452 + 0.006*sl sn to q t r 0.080 0.054 + 0.013*sl 0.052 + 0.013*sl 0.042 + 0.014*sl t f 0.073 0.048 + 0.013*sl 0.053 + 0.011*sl 0.045 + 0.012*sl t plh 0.265 0.249 + 0.008*sl 0.255 + 0.007*sl 0.261 + 0.006*sl t phl 0.247 0.229 + 0.009*sl 0.236 + 0.007*sl 0.247 + 0.006*sl rn to q t r 0.080 0.054 + 0.013*sl 0.053 + 0.013*sl 0.042 + 0.014*sl t f 0.075 0.051 + 0.012*sl 0.053 + 0.011*sl 0.045 + 0.012*sl t plh 0.301 0.285 + 0.008*sl 0.291 + 0.007*sl 0.297 + 0.006*sl t phl 0.325 0.308 + 0.009*sl 0.315 + 0.007*sl 0.326 + 0.006*sl d to qn t r 0.086 0.059 + 0.014*sl 0.060 + 0.014*sl 0.056 + 0.014*sl t f 0.076 0.051 + 0.013*sl 0.055 + 0.012*sl 0.052 + 0.012*sl t plh 0.375 0.357 + 0.009*sl 0.364 + 0.007*sl 0.377 + 0.006*sl t phl 0.369 0.350 + 0.009*sl 0.358 + 0.007*sl 0.372 + 0.006*sl gn to qn t r 0.086 0.058 + 0.014*sl 0.060 + 0.014*sl 0.056 + 0.014*sl t f 0.077 0.054 + 0.011*sl 0.053 + 0.012*sl 0.052 + 0.012*sl t plh 0.358 0.340 + 0.009*sl 0.347 + 0.007*sl 0.359 + 0.006*sl t phl 0.377 0.358 + 0.009*sl 0.366 + 0.007*sl 0.380 + 0.006*sl sn to qn t r 0.088 0.060 + 0.014*sl 0.061 + 0.014*sl 0.057 + 0.014*sl t f 0.080 0.055 + 0.012*sl 0.059 + 0.012*sl 0.056 + 0.012*sl t plh 0.152 0.134 + 0.009*sl 0.141 + 0.007*sl 0.153 + 0.006*sl t phl 0.173 0.154 + 0.010*sl 0.162 + 0.007*sl 0.176 + 0.006*sl rn to qn t r 0.087 0.058 + 0.014*sl 0.061 + 0.014*sl 0.056 + 0.014*sl t f 0.076 0.051 + 0.013*sl 0.055 + 0.012*sl 0.052 + 0.012*sl t plh 0.231 0.213 + 0.009*sl 0.221 + 0.007*sl 0.232 + 0.006*sl t phl 0.209 0.190 + 0.009*sl 0.198 + 0.007*sl 0.212 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-434 samsung asic oak_ldi2/oak_ldi2d2 d latch with 2 input, 2 active high, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count oak_ldi2 oak_ldi2d2 oak_ldi2 oak_ldi2d2 d1 d2 g1 g2 d1 d2 g1 g2 0.8 0.8 1.6 1.5 0.8 0.8 1.6 1.5 5.00 5.33 parameter symbol value (ns) oak_ldi2 oak_ldi2d2 input setup time (d1 to g1) t su 0.325 0.343 input hold time (d1 to g1) t hd 0.000 0.000 input setup time (d2 to g2) t su 0.360 0.385 input hold time (d2 to g2) t hd 0.000 0.000 pulse width high (g1) t pwh 0.300 0.325 pulse width high (g2) t pwh 0.341 0.363 q qn d1 d2 g1 g2 g1 g2 d1 d2 qn q truth table d1 g1 d2 g2 q (n+1) qn (n+1) x0x0q (n)qn (n) 11xx10 01x001 xx1110 x00101 010101
samsung asic 3-435 STD111 oak_ldi2/oak_ldi2d2 d latch with 2 input, 2 active high, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) oak_ldi2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to q t r 0.101 0.048 + 0.027*sl 0.043 + 0.028*sl 0.038 + 0.029*sl t f 0.089 0.041 + 0.024*sl 0.043 + 0.024*sl 0.035 + 0.024*sl t plh 0.369 0.342 + 0.014*sl 0.346 + 0.012*sl 0.347 + 0.012*sl t phl 0.419 0.390 + 0.015*sl 0.396 + 0.013*sl 0.399 + 0.013*sl d2 to q t r 0.101 0.049 + 0.026*sl 0.042 + 0.028*sl 0.038 + 0.029*sl t f 0.091 0.044 + 0.023*sl 0.042 + 0.024*sl 0.035 + 0.024*sl t plh 0.413 0.386 + 0.014*sl 0.390 + 0.012*sl 0.391 + 0.012*sl t phl 0.443 0.413 + 0.015*sl 0.420 + 0.013*sl 0.422 + 0.013*sl g1 to q t r 0.101 0.048 + 0.027*sl 0.043 + 0.028*sl 0.037 + 0.029*sl t f 0.089 0.041 + 0.024*sl 0.043 + 0.024*sl 0.035 + 0.024*sl t plh 0.370 0.343 + 0.013*sl 0.347 + 0.013*sl 0.348 + 0.012*sl t phl 0.369 0.339 + 0.015*sl 0.346 + 0.013*sl 0.348 + 0.013*sl g2 to q t r 0.101 0.049 + 0.026*sl 0.042 + 0.028*sl 0.037 + 0.029*sl t f 0.089 0.041 + 0.024*sl 0.041 + 0.024*sl 0.035 + 0.024*sl t plh 0.414 0.387 + 0.014*sl 0.391 + 0.012*sl 0.392 + 0.012*sl t phl 0.386 0.357 + 0.015*sl 0.364 + 0.013*sl 0.364 + 0.013*sl d1 to qn t r 0.117 0.066 + 0.026*sl 0.060 + 0.027*sl 0.051 + 0.028*sl t f 0.101 0.055 + 0.023*sl 0.055 + 0.023*sl 0.048 + 0.024*sl t plh 0.361 0.332 + 0.015*sl 0.338 + 0.013*sl 0.342 + 0.012*sl t phl 0.318 0.287 + 0.016*sl 0.295 + 0.014*sl 0.302 + 0.013*sl d2 to qn t r 0.118 0.067 + 0.026*sl 0.061 + 0.027*sl 0.051 + 0.028*sl t f 0.101 0.055 + 0.023*sl 0.054 + 0.023*sl 0.048 + 0.024*sl t plh 0.384 0.355 + 0.015*sl 0.362 + 0.013*sl 0.366 + 0.012*sl t phl 0.362 0.330 + 0.016*sl 0.339 + 0.014*sl 0.346 + 0.013*sl g1 to qn t r 0.111 0.057 + 0.027*sl 0.054 + 0.028*sl 0.047 + 0.028*sl t f 0.099 0.050 + 0.024*sl 0.054 + 0.023*sl 0.046 + 0.024*sl t plh 0.311 0.282 + 0.014*sl 0.288 + 0.013*sl 0.292 + 0.012*sl t phl 0.319 0.288 + 0.016*sl 0.296 + 0.014*sl 0.303 + 0.013*sl g2 to qn t r 0.111 0.058 + 0.027*sl 0.054 + 0.028*sl 0.047 + 0.028*sl t f 0.100 0.053 + 0.023*sl 0.053 + 0.023*sl 0.047 + 0.024*sl t plh 0.329 0.300 + 0.014*sl 0.306 + 0.013*sl 0.308 + 0.012*sl t phl 0.362 0.331 + 0.016*sl 0.339 + 0.014*sl 0.346 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-436 samsung asic oak_ldi2/oak_ldi2d2 d latch with 2 input, 2 active high, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) oak_ldi2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to q t r 0.077 0.051 + 0.013*sl 0.050 + 0.013*sl 0.039 + 0.014*sl t f 0.069 0.043 + 0.013*sl 0.050 + 0.011*sl 0.040 + 0.012*sl t plh 0.412 0.396 + 0.008*sl 0.402 + 0.007*sl 0.407 + 0.006*sl t phl 0.455 0.438 + 0.009*sl 0.445 + 0.007*sl 0.454 + 0.006*sl d2 to q t r 0.078 0.052 + 0.013*sl 0.050 + 0.014*sl 0.039 + 0.014*sl t f 0.070 0.045 + 0.013*sl 0.049 + 0.011*sl 0.041 + 0.012*sl t plh 0.453 0.437 + 0.008*sl 0.443 + 0.007*sl 0.448 + 0.006*sl t phl 0.475 0.458 + 0.009*sl 0.465 + 0.007*sl 0.474 + 0.006*sl g1 to q t r 0.077 0.051 + 0.013*sl 0.050 + 0.014*sl 0.039 + 0.014*sl t f 0.070 0.044 + 0.013*sl 0.049 + 0.012*sl 0.040 + 0.012*sl t plh 0.413 0.397 + 0.008*sl 0.402 + 0.007*sl 0.408 + 0.006*sl t phl 0.403 0.385 + 0.009*sl 0.393 + 0.007*sl 0.402 + 0.006*sl g2 to q t r 0.078 0.051 + 0.013*sl 0.051 + 0.013*sl 0.039 + 0.014*sl t f 0.070 0.046 + 0.012*sl 0.049 + 0.012*sl 0.040 + 0.012*sl t plh 0.455 0.439 + 0.008*sl 0.445 + 0.007*sl 0.450 + 0.006*sl t phl 0.420 0.403 + 0.008*sl 0.408 + 0.007*sl 0.417 + 0.006*sl d1 to qn t r 0.093 0.066 + 0.013*sl 0.066 + 0.013*sl 0.053 + 0.014*sl t f 0.080 0.056 + 0.012*sl 0.058 + 0.012*sl 0.054 + 0.012*sl t plh 0.368 0.350 + 0.009*sl 0.358 + 0.007*sl 0.367 + 0.006*sl t phl 0.324 0.304 + 0.010*sl 0.313 + 0.007*sl 0.326 + 0.006*sl d2 to qn t r 0.093 0.066 + 0.013*sl 0.066 + 0.013*sl 0.053 + 0.014*sl t f 0.081 0.058 + 0.011*sl 0.057 + 0.012*sl 0.054 + 0.012*sl t plh 0.388 0.370 + 0.009*sl 0.378 + 0.007*sl 0.387 + 0.006*sl t phl 0.364 0.345 + 0.009*sl 0.353 + 0.007*sl 0.367 + 0.006*sl g1 to qn t r 0.086 0.061 + 0.013*sl 0.059 + 0.013*sl 0.048 + 0.014*sl t f 0.078 0.054 + 0.012*sl 0.056 + 0.012*sl 0.054 + 0.012*sl t plh 0.317 0.300 + 0.009*sl 0.307 + 0.007*sl 0.316 + 0.006*sl t phl 0.324 0.305 + 0.010*sl 0.313 + 0.007*sl 0.327 + 0.006*sl g2 to qn t r 0.086 0.060 + 0.013*sl 0.059 + 0.013*sl 0.048 + 0.014*sl t f 0.079 0.054 + 0.013*sl 0.057 + 0.012*sl 0.054 + 0.012*sl t plh 0.334 0.318 + 0.008*sl 0.322 + 0.007*sl 0.331 + 0.006*sl t phl 0.366 0.347 + 0.010*sl 0.355 + 0.007*sl 0.369 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-437 STD111 oak_ldi3/oak_ldi3d2 d latch with 3 input, 3 active high, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count oak_ldi3 oak_ldi3d2 oak_ldi3 oak_ldi3d2 d1 d2 d3 g1 g2 g3 d1 d2 d3 g1 g2 g3 0.8 0.8 0.8 1.5 1.5 1.6 0.8 0.8 0.8 1.5 1.5 1.6 6.00 6.33 parameter symbol value (ns) oak_ldi3 oak_ldi3d2 input setup time (d1 to g1) t su 0.340 0.351 input hold time (d1 to g1) t hd 0.000 0.000 input setup time (d2 to g2) t su 0.385 0.387 input hold time (d2 to g2) t hd 0.000 0.000 input setup time (d3 to g3) t su 0.442 0.456 input hold time (d3 to g3) t hd 0.000 0.000 pulse width high (g1) t pwh 0.310 0.329 pulse width high (g2) t pwh 0.353 0.369 pulse width high (g3) t pwh 0.399 0.416 q qn d1 d2 d3 g1 g2 g3 g1 g2 d1 d2 qn q g3 d3 truth table d1 g1 d2 g2 d3 g3 q (n+1) qn (n+1) x0x0x0q (n)qn (n) 11xxxx 1 0 01x0x0 0 1 xx11xx 1 0 x001x0 0 1 xxxx11 1 0 x0x001 0 1 0101x0 0 1 x00101 0 1 01x001 0 1 010101 0 1
STD111 3-438 samsung asic oak_ldi3/oak_ldi3d2 d latch with 3 input, 3 active high, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) oak_ldi3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to q t r 0.101 0.048 + 0.027*sl 0.044 + 0.028*sl 0.038 + 0.028*sl t f 0.090 0.046 + 0.022*sl 0.041 + 0.023*sl 0.036 + 0.024*sl t plh 0.375 0.348 + 0.013*sl 0.352 + 0.012*sl 0.353 + 0.012*sl t phl 0.400 0.372 + 0.014*sl 0.378 + 0.013*sl 0.380 + 0.012*sl d2 to q t r 0.102 0.049 + 0.026*sl 0.044 + 0.028*sl 0.038 + 0.028*sl t f 0.090 0.045 + 0.022*sl 0.042 + 0.023*sl 0.035 + 0.024*sl t plh 0.433 0.406 + 0.013*sl 0.410 + 0.012*sl 0.411 + 0.012*sl t phl 0.443 0.415 + 0.014*sl 0.421 + 0.013*sl 0.424 + 0.012*sl d3 to q t r 0.102 0.049 + 0.026*sl 0.044 + 0.028*sl 0.039 + 0.028*sl t f 0.090 0.044 + 0.023*sl 0.043 + 0.023*sl 0.036 + 0.024*sl t plh 0.481 0.454 + 0.013*sl 0.457 + 0.012*sl 0.459 + 0.012*sl t phl 0.477 0.449 + 0.014*sl 0.454 + 0.013*sl 0.457 + 0.012*sl g1 to q t r 0.102 0.049 + 0.026*sl 0.043 + 0.028*sl 0.038 + 0.028*sl t f 0.090 0.045 + 0.022*sl 0.043 + 0.023*sl 0.036 + 0.024*sl t plh 0.387 0.360 + 0.013*sl 0.364 + 0.012*sl 0.365 + 0.012*sl t phl 0.381 0.352 + 0.015*sl 0.359 + 0.013*sl 0.361 + 0.012*sl g2 to q t r 0.101 0.048 + 0.027*sl 0.044 + 0.028*sl 0.038 + 0.028*sl t f 0.089 0.042 + 0.023*sl 0.043 + 0.023*sl 0.035 + 0.024*sl t plh 0.431 0.404 + 0.013*sl 0.408 + 0.012*sl 0.409 + 0.012*sl t phl 0.400 0.371 + 0.014*sl 0.377 + 0.013*sl 0.380 + 0.012*sl g3 to q t r 0.101 0.048 + 0.027*sl 0.044 + 0.028*sl 0.038 + 0.028*sl t f 0.090 0.045 + 0.022*sl 0.041 + 0.023*sl 0.036 + 0.024*sl t plh 0.475 0.448 + 0.013*sl 0.452 + 0.012*sl 0.453 + 0.012*sl t phl 0.413 0.384 + 0.014*sl 0.390 + 0.013*sl 0.393 + 0.012*sl d1 to qn t r 0.116 0.065 + 0.025*sl 0.059 + 0.027*sl 0.050 + 0.028*sl t f 0.098 0.052 + 0.023*sl 0.055 + 0.023*sl 0.047 + 0.023*sl t plh 0.344 0.316 + 0.014*sl 0.322 + 0.013*sl 0.325 + 0.012*sl t phl 0.324 0.294 + 0.015*sl 0.301 + 0.013*sl 0.308 + 0.012*sl d2 to qn t r 0.118 0.068 + 0.025*sl 0.061 + 0.027*sl 0.052 + 0.028*sl t f 0.100 0.056 + 0.022*sl 0.053 + 0.023*sl 0.048 + 0.023*sl t plh 0.387 0.359 + 0.014*sl 0.365 + 0.013*sl 0.368 + 0.012*sl t phl 0.382 0.352 + 0.015*sl 0.359 + 0.013*sl 0.366 + 0.012*sl d3 to qn t r 0.119 0.069 + 0.025*sl 0.063 + 0.027*sl 0.053 + 0.028*sl t f 0.102 0.057 + 0.022*sl 0.056 + 0.023*sl 0.050 + 0.023*sl t plh 0.420 0.392 + 0.014*sl 0.398 + 0.013*sl 0.402 + 0.012*sl t phl 0.429 0.399 + 0.015*sl 0.407 + 0.013*sl 0.413 + 0.012*sl g1 to qn t r 0.111 0.059 + 0.026*sl 0.054 + 0.027*sl 0.047 + 0.028*sl t f 0.099 0.053 + 0.023*sl 0.054 + 0.023*sl 0.046 + 0.023*sl t plh 0.325 0.297 + 0.014*sl 0.303 + 0.013*sl 0.306 + 0.012*sl t phl 0.336 0.306 + 0.015*sl 0.313 + 0.013*sl 0.320 + 0.012*sl
samsung asic 3-439 STD111 oak_ldi3/oak_ldi3d2 d latch with 3 input, 3 active high, 1x/2x drive switching characteristics (cont.) (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) oak_ldi3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* g2 to qn t r 0.111 0.059 + 0.026*sl 0.054 + 0.027*sl 0.047 + 0.028*sl t f 0.098 0.051 + 0.024*sl 0.055 + 0.023*sl 0.047 + 0.023*sl t plh 0.344 0.316 + 0.014*sl 0.321 + 0.013*sl 0.325 + 0.012*sl t phl 0.380 0.349 + 0.015*sl 0.357 + 0.013*sl 0.364 + 0.012*sl g3 to qn t r 0.111 0.058 + 0.026*sl 0.054 + 0.027*sl 0.047 + 0.028*sl t f 0.102 0.057 + 0.023*sl 0.056 + 0.023*sl 0.049 + 0.023*sl t plh 0.357 0.329 + 0.014*sl 0.334 + 0.013*sl 0.338 + 0.012*sl t phl 0.424 0.393 + 0.015*sl 0.401 + 0.013*sl 0.408 + 0.012*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-440 samsung asic oak_ldi3/oak_ldi3d2 d latch with 3 input, 3 active high, 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) oak_ldi3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to q t r 0.077 0.051 + 0.013*sl 0.050 + 0.013*sl 0.041 + 0.014*sl t f 0.073 0.049 + 0.012*sl 0.050 + 0.011*sl 0.043 + 0.012*sl t plh 0.413 0.398 + 0.008*sl 0.403 + 0.006*sl 0.408 + 0.006*sl t phl 0.440 0.422 + 0.009*sl 0.429 + 0.007*sl 0.438 + 0.006*sl d2 to q t r 0.078 0.052 + 0.013*sl 0.050 + 0.013*sl 0.041 + 0.014*sl t f 0.073 0.050 + 0.011*sl 0.050 + 0.011*sl 0.043 + 0.012*sl t plh 0.472 0.456 + 0.008*sl 0.462 + 0.006*sl 0.467 + 0.006*sl t phl 0.484 0.467 + 0.009*sl 0.474 + 0.007*sl 0.483 + 0.006*sl d3 to q t r 0.079 0.053 + 0.013*sl 0.053 + 0.013*sl 0.041 + 0.014*sl t f 0.073 0.050 + 0.012*sl 0.050 + 0.011*sl 0.043 + 0.012*sl t plh 0.521 0.505 + 0.008*sl 0.511 + 0.006*sl 0.516 + 0.006*sl t phl 0.518 0.501 + 0.009*sl 0.508 + 0.007*sl 0.517 + 0.006*sl g1 to q t r 0.077 0.051 + 0.013*sl 0.050 + 0.013*sl 0.041 + 0.014*sl t f 0.071 0.045 + 0.013*sl 0.050 + 0.011*sl 0.043 + 0.012*sl t plh 0.425 0.410 + 0.008*sl 0.415 + 0.006*sl 0.420 + 0.006*sl t phl 0.419 0.401 + 0.009*sl 0.409 + 0.007*sl 0.418 + 0.006*sl g2 to q t r 0.077 0.052 + 0.013*sl 0.050 + 0.013*sl 0.041 + 0.014*sl t f 0.071 0.045 + 0.013*sl 0.051 + 0.011*sl 0.042 + 0.012*sl t plh 0.470 0.454 + 0.008*sl 0.459 + 0.006*sl 0.465 + 0.006*sl t phl 0.438 0.420 + 0.009*sl 0.427 + 0.007*sl 0.436 + 0.006*sl g3 to q t r 0.078 0.053 + 0.013*sl 0.050 + 0.013*sl 0.041 + 0.014*sl t f 0.071 0.045 + 0.013*sl 0.050 + 0.011*sl 0.042 + 0.012*sl t plh 0.515 0.499 + 0.008*sl 0.505 + 0.006*sl 0.510 + 0.006*sl t phl 0.451 0.433 + 0.009*sl 0.440 + 0.007*sl 0.449 + 0.006*sl d1 to qn t r 0.092 0.068 + 0.012*sl 0.065 + 0.013*sl 0.053 + 0.014*sl t f 0.080 0.056 + 0.012*sl 0.058 + 0.011*sl 0.054 + 0.012*sl t plh 0.353 0.335 + 0.009*sl 0.343 + 0.007*sl 0.351 + 0.006*sl t phl 0.327 0.309 + 0.009*sl 0.317 + 0.007*sl 0.330 + 0.006*sl d2 to qn t r 0.095 0.070 + 0.012*sl 0.068 + 0.013*sl 0.055 + 0.014*sl t f 0.082 0.059 + 0.011*sl 0.058 + 0.011*sl 0.054 + 0.012*sl t plh 0.396 0.379 + 0.009*sl 0.386 + 0.007*sl 0.395 + 0.006*sl t phl 0.386 0.367 + 0.009*sl 0.375 + 0.007*sl 0.388 + 0.006*sl d3 to qn t r 0.095 0.070 + 0.013*sl 0.069 + 0.013*sl 0.056 + 0.014*sl t f 0.084 0.061 + 0.011*sl 0.061 + 0.011*sl 0.056 + 0.012*sl t plh 0.430 0.412 + 0.009*sl 0.420 + 0.007*sl 0.429 + 0.006*sl t phl 0.434 0.415 + 0.009*sl 0.423 + 0.007*sl 0.437 + 0.006*sl g1 to qn t r 0.089 0.063 + 0.013*sl 0.062 + 0.013*sl 0.050 + 0.014*sl t f 0.078 0.054 + 0.012*sl 0.056 + 0.012*sl 0.053 + 0.012*sl t plh 0.332 0.315 + 0.009*sl 0.323 + 0.007*sl 0.331 + 0.006*sl t phl 0.339 0.321 + 0.009*sl 0.329 + 0.007*sl 0.342 + 0.006*sl
samsung asic 3-441 STD111 oak_ldi3/oak_ldi3d2 d latch with 3 input, 3 active high, 1x/2x drive switching characteristics (cont.) (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) oak_ldi3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* g2 to qn t r 0.087 0.060 + 0.013*sl 0.060 + 0.013*sl 0.050 + 0.014*sl t f 0.080 0.056 + 0.012*sl 0.058 + 0.011*sl 0.054 + 0.012*sl t plh 0.351 0.334 + 0.009*sl 0.341 + 0.007*sl 0.349 + 0.006*sl t phl 0.384 0.365 + 0.009*sl 0.373 + 0.007*sl 0.386 + 0.006*sl g3 to qn t r 0.088 0.062 + 0.013*sl 0.060 + 0.013*sl 0.050 + 0.014*sl t f 0.082 0.058 + 0.012*sl 0.061 + 0.011*sl 0.055 + 0.012*sl t plh 0.364 0.347 + 0.009*sl 0.354 + 0.007*sl 0.362 + 0.006*sl t phl 0.428 0.409 + 0.009*sl 0.418 + 0.007*sl 0.431 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-442 samsung asic ls0/ls0d2 sr latch with 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 2.5v, unit = ns) input load (sl) gate count ls0 ls0d2 ls0 ls0d2 rn sn rn sn 1.0 1.0 1.9 1.9 1.67 2.67 parameter symbol value (ns) ls0 ls0d2 pulse width low (sn) t pwl 0.238 0.207 removal time (sn to rn) t rm 0.044 0.074 recovery time (sn to rn) t rc 0.176 0.146 pulse width low (rn) t pwl 0.238 0.206 q qn rn sn sn qn q rn truth table * both q and qn outputs will remain high during rn and sn are low. however, if rn and sn go high simultaneously, the output states are unpredictable. rn sn q (n+1) qn (n+1) 00* * 1010 0101 1 1 q (n) qn (n)
samsung asic 3-443 STD111 ls0/ls0d2 sr latch with 1x/2x drive switching characteristics (typical process, 25 c, 2.5 v, t r /t f = 0.20ns, sl: standard load) ls0 ls0d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn to q t r 0.169 0.123 + 0.023*sl 0.125 + 0.022*sl 0.118 + 0.023*sl t f 0.175 0.117 + 0.029*sl 0.110 + 0.031*sl 0.093 + 0.033*sl t plh 0.109 0.076 + 0.016*sl 0.081 + 0.015*sl 0.081 + 0.015*sl t phl 0.103 0.069 + 0.017*sl 0.074 + 0.016*sl 0.073 + 0.016*sl rn to q t f 0.152 0.088 + 0.032*sl 0.085 + 0.033*sl 0.080 + 0.033*sl t phl 0.165 0.131 + 0.017*sl 0.134 + 0.016*sl 0.135 + 0.016*sl sn to qn t f 0.152 0.087 + 0.032*sl 0.085 + 0.033*sl 0.080 + 0.033*sl t phl 0.165 0.131 + 0.017*sl 0.134 + 0.016*sl 0.135 + 0.016*sl rn to qn t r 0.169 0.123 + 0.023*sl 0.125 + 0.022*sl 0.118 + 0.023*sl t f 0.175 0.117 + 0.029*sl 0.110 + 0.031*sl 0.093 + 0.033*sl t plh 0.109 0.076 + 0.016*sl 0.081 + 0.015*sl 0.081 + 0.015*sl t phl 0.103 0.069 + 0.017*sl 0.074 + 0.016*sl 0.073 + 0.016*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn to q t r 0.144 0.120 + 0.012*sl 0.122 + 0.011*sl 0.117 + 0.012*sl t f 0.146 0.117 + 0.014*sl 0.112 + 0.016*sl 0.095 + 0.017*sl t plh 0.090 0.072 + 0.009*sl 0.078 + 0.008*sl 0.079 + 0.008*sl t phl 0.086 0.066 + 0.010*sl 0.072 + 0.008*sl 0.073 + 0.008*sl rn to q t f 0.119 0.087 + 0.016*sl 0.084 + 0.017*sl 0.079 + 0.017*sl t phl 0.145 0.127 + 0.009*sl 0.130 + 0.008*sl 0.132 + 0.008*sl sn to qn t f 0.119 0.088 + 0.016*sl 0.084 + 0.017*sl 0.079 + 0.017*sl t phl 0.145 0.127 + 0.009*sl 0.130 + 0.008*sl 0.132 + 0.008*sl rn to qn t r 0.144 0.121 + 0.012*sl 0.122 + 0.011*sl 0.117 + 0.012*sl t f 0.146 0.118 + 0.014*sl 0.113 + 0.016*sl 0.095 + 0.017*sl t plh 0.090 0.072 + 0.009*sl 0.078 + 0.008*sl 0.079 + 0.008*sl t phl 0.086 0.066 + 0.010*sl 0.072 + 0.008*sl 0.073 + 0.008*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-444 samsung asic ls1/ls1d2 sr latch with separate inputs, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count ls1 ls1d2 ls1 ls1 d2 sn1 sn2 sn rn1 rn2 rn sn1 sn2 sn rn1 rn2 rn 2.67 4.67 1.0 1.1 0.9 1.0 1.1 0.9 1.0 1.1 0.9 1.0 1.1 0.9 q qn sn1 rn1 rn2 sn2 sn rn rn1 q qn rn rn2 sn1 sn sn2 truth table rn* = rn1 + rn2, sn* = sn1 + sn2 * both q and qn output will remain high during rn (rn*) and sn (sn*) are low, if rn (rn*) and sn (sn*) go high simultaneously, the output states are unpredictable rn sn rn* sn* q (n+1) qn (n+1) 00xx * * x00x* * xx00* * 0xx0* * 101x10 01x101 1x1010 x10101 1111q (n)qn (n)
samsung asic 3-445 STD111 ls1/ls1d2 sr latch with separate inputs, 1x/2x drive timing requirements (typical process, 25 c, 2.5v, unit = ns) parameter symbol value (ns) ls1 ls1d2 pulse width low (sn1) t pwl 0.356 0.302 removal time (sn1 to rn1) t rm 0.024 0.104 recovery time (sn1 to rn1) t rc 0.194 0.115 removal time (sn1 to rn2) t rm 0.046 0.123 recovery time (sn1 to rn2) t rc 0.173 0.097 removal time (sn1 to rn) t rm 0.033 0.110 recovery time (sn1 to rn) t rc 0.187 0.110 pulse width low (sn2) t pwl 0.360 0.304 removal time (sn2 to rn1) t rm 0.010 0.085 recovery time (sn2 to rn1) t rc 0.211 0.135 removal time (sn2 to rn2) t rm 0.028 0.105 recovery time (sn2 to rn2) t rc 0.191 0.115 removal time (sn2 to rn) t rm 0.016 0.091 recovery time (sn2 to rn) t rc 0.204 0.129 pulse width low (sn) t pwl 0.318 0.278 removal time (sn to rn1) t rm 0.022 0.100 recovery time (sn to rn1) t rc 0.200 0.122 removal time (sn to rn2) t rm 0.042 0.118 recovery time (sn to rn2) t rc 0.178 0.104 removal time (sn to rn) t rm 0.028 0.105 recovery time (sn to rn) t rc 0.192 0.117 pulse width low (rn1) t pwl 0.355 0.295 pulse width low (rn2) t pwl 0.360 0.297 pulse width low (rn) t pwl 0.318 0.275
STD111 3-446 samsung asic ls1/ls1d2 sr latch with separate inputs, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ls1 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn1 to q t r 0.269 0.198 + 0.035*sl 0.201 + 0.035*sl 0.201 + 0.035*sl t f 0.270 0.177 + 0.047*sl 0.169 + 0.049*sl 0.157 + 0.050*sl t plh 0.158 0.109 + 0.024*sl 0.109 + 0.024*sl 0.110 + 0.024*sl t phl 0.150 0.104 + 0.023*sl 0.104 + 0.023*sl 0.104 + 0.023*sl sn2 to q t r 0.274 0.197 + 0.039*sl 0.207 + 0.036*sl 0.217 + 0.035*sl t f 0.305 0.213 + 0.046*sl 0.205 + 0.048*sl 0.191 + 0.049*sl t plh 0.158 0.109 + 0.024*sl 0.109 + 0.024*sl 0.111 + 0.024*sl t phl 0.169 0.124 + 0.023*sl 0.123 + 0.023*sl 0.123 + 0.023*sl sn to q t r 0.232 0.178 + 0.027*sl 0.181 + 0.026*sl 0.180 + 0.027*sl t f 0.268 0.173 + 0.047*sl 0.167 + 0.049*sl 0.160 + 0.050*sl t plh 0.144 0.110 + 0.017*sl 0.110 + 0.017*sl 0.110 + 0.017*sl t phl 0.154 0.108 + 0.023*sl 0.108 + 0.023*sl 0.109 + 0.023*sl rn1 to q t f 0.266 0.170 + 0.048*sl 0.166 + 0.049*sl 0.162 + 0.050*sl t phl 0.264 0.216 + 0.024*sl 0.219 + 0.023*sl 0.222 + 0.023*sl rn2 to q t f 0.298 0.201 + 0.048*sl 0.199 + 0.049*sl 0.195 + 0.049*sl t phl 0.290 0.243 + 0.024*sl 0.245 + 0.023*sl 0.248 + 0.023*sl rn to q t f 0.262 0.165 + 0.049*sl 0.162 + 0.049*sl 0.158 + 0.050*sl t phl 0.262 0.215 + 0.024*sl 0.217 + 0.023*sl 0.218 + 0.023*sl sn1 to qn t f 0.263 0.167 + 0.048*sl 0.163 + 0.049*sl 0.159 + 0.050*sl t phl 0.265 0.216 + 0.024*sl 0.219 + 0.023*sl 0.223 + 0.023*sl sn2 to qn t f 0.296 0.199 + 0.048*sl 0.197 + 0.049*sl 0.193 + 0.049*sl t phl 0.291 0.243 + 0.024*sl 0.246 + 0.023*sl 0.249 + 0.023*sl sn to qn t f 0.259 0.162 + 0.048*sl 0.159 + 0.049*sl 0.155 + 0.050*sl t phl 0.262 0.214 + 0.024*sl 0.216 + 0.023*sl 0.218 + 0.023*sl rn1 to qn t r 0.267 0.196 + 0.035*sl 0.198 + 0.035*sl 0.199 + 0.035*sl t f 0.267 0.174 + 0.047*sl 0.167 + 0.048*sl 0.154 + 0.050*sl t plh 0.156 0.108 + 0.024*sl 0.108 + 0.024*sl 0.108 + 0.024*sl t phl 0.148 0.103 + 0.023*sl 0.102 + 0.023*sl 0.102 + 0.023*sl rn2 to qn t r 0.272 0.194 + 0.039*sl 0.204 + 0.036*sl 0.215 + 0.035*sl t f 0.303 0.212 + 0.045*sl 0.203 + 0.048*sl 0.189 + 0.049*sl t plh 0.157 0.108 + 0.024*sl 0.109 + 0.024*sl 0.110 + 0.024*sl t phl 0.168 0.123 + 0.023*sl 0.122 + 0.023*sl 0.122 + 0.023*sl rn to qn t r 0.231 0.176 + 0.027*sl 0.179 + 0.027*sl 0.179 + 0.027*sl t f 0.265 0.170 + 0.047*sl 0.164 + 0.049*sl 0.157 + 0.050*sl t plh 0.143 0.109 + 0.017*sl 0.109 + 0.017*sl 0.109 + 0.017*sl t phl 0.153 0.107 + 0.023*sl 0.107 + 0.023*sl 0.107 + 0.023*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-447 STD111 ls1/ls1d2 sr latch with separate inputs, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ls1d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn1 to q t r 0.081 0.054 + 0.013*sl 0.054 + 0.013*sl 0.042 + 0.014*sl t f 0.074 0.051 + 0.011*sl 0.052 + 0.011*sl 0.045 + 0.012*sl t plh 0.279 0.262 + 0.008*sl 0.268 + 0.007*sl 0.274 + 0.006*sl t phl 0.265 0.248 + 0.009*sl 0.255 + 0.007*sl 0.266 + 0.006*sl sn2 to q t r 0.081 0.054 + 0.013*sl 0.054 + 0.013*sl 0.042 + 0.014*sl t f 0.075 0.053 + 0.011*sl 0.052 + 0.011*sl 0.046 + 0.012*sl t plh 0.279 0.263 + 0.008*sl 0.269 + 0.007*sl 0.275 + 0.006*sl t phl 0.290 0.272 + 0.009*sl 0.280 + 0.007*sl 0.290 + 0.006*sl sn to q t r 0.078 0.052 + 0.013*sl 0.050 + 0.014*sl 0.040 + 0.014*sl t f 0.073 0.048 + 0.012*sl 0.053 + 0.011*sl 0.044 + 0.012*sl t plh 0.261 0.245 + 0.008*sl 0.251 + 0.007*sl 0.256 + 0.006*sl t phl 0.270 0.252 + 0.009*sl 0.260 + 0.007*sl 0.270 + 0.006*sl rn1 to q t f 0.074 0.050 + 0.012*sl 0.053 + 0.011*sl 0.045 + 0.012*sl t phl 0.395 0.377 + 0.009*sl 0.385 + 0.007*sl 0.395 + 0.006*sl rn2 to q t f 0.074 0.050 + 0.012*sl 0.054 + 0.011*sl 0.045 + 0.012*sl t phl 0.424 0.406 + 0.009*sl 0.414 + 0.007*sl 0.425 + 0.006*sl rn to q t f 0.074 0.050 + 0.012*sl 0.052 + 0.011*sl 0.044 + 0.012*sl t phl 0.386 0.369 + 0.009*sl 0.376 + 0.007*sl 0.387 + 0.006*sl sn1 to qn t f 0.077 0.052 + 0.012*sl 0.055 + 0.011*sl 0.047 + 0.012*sl t phl 0.406 0.387 + 0.009*sl 0.395 + 0.007*sl 0.406 + 0.006*sl sn2 to qn t f 0.078 0.054 + 0.012*sl 0.055 + 0.012*sl 0.048 + 0.012*sl t phl 0.438 0.419 + 0.009*sl 0.427 + 0.007*sl 0.438 + 0.006*sl sn to qn t f 0.075 0.050 + 0.013*sl 0.055 + 0.012*sl 0.047 + 0.012*sl t phl 0.394 0.375 + 0.009*sl 0.383 + 0.007*sl 0.395 + 0.006*sl rn1 to qn t r 0.081 0.054 + 0.013*sl 0.054 + 0.013*sl 0.043 + 0.014*sl t f 0.076 0.053 + 0.012*sl 0.054 + 0.012*sl 0.046 + 0.012*sl t plh 0.268 0.252 + 0.008*sl 0.258 + 0.007*sl 0.264 + 0.006*sl t phl 0.265 0.247 + 0.009*sl 0.254 + 0.007*sl 0.265 + 0.006*sl rn2 to qn t r 0.081 0.055 + 0.013*sl 0.054 + 0.013*sl 0.043 + 0.014*sl t f 0.077 0.054 + 0.012*sl 0.055 + 0.011*sl 0.047 + 0.012*sl t plh 0.268 0.252 + 0.008*sl 0.258 + 0.007*sl 0.264 + 0.006*sl t phl 0.290 0.271 + 0.009*sl 0.279 + 0.007*sl 0.290 + 0.006*sl rn to qn t r 0.079 0.052 + 0.013*sl 0.051 + 0.013*sl 0.041 + 0.014*sl t f 0.076 0.051 + 0.012*sl 0.054 + 0.012*sl 0.047 + 0.012*sl t plh 0.255 0.239 + 0.008*sl 0.245 + 0.007*sl 0.250 + 0.006*sl t phl 0.270 0.252 + 0.009*sl 0.260 + 0.007*sl 0.270 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-448 samsung asic busholder cell list logic symbol cell name function description busholder bus holder y cell data input load (sl) gate count y 1.33 8.1
samsung asic 3-449 STD111 internal clock drivers cell list logic symbol cell data cell name function description ck2 internal clock driver cmos 2ma ck4 internal clock driver cmos 4ma ck6 internal clock driver cmos 6ma ck8 internal clock driver cmos 8ma standard load (sl) i/o slot ck2 ck4 ck6 ck8 ck2 ck4 ck6 ck8 aaaa 17.524 17.551 25.277 25.271 1.0 1.0 1.0 1.0 a y truth table ay 00 11
STD111 3-450 samsung asic ck2/ck4/ck6/ck8 internal clock driver cmos 2/4/6/8ma switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) ck2 ck4 ck6 ck8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.059 0.053 + 0.003*sl 0.052 + 0.003*sl 0.052 + 0.003*sl t f 0.055 0.047 + 0.004*sl 0.046 + 0.004*sl 0.045 + 0.004*sl t plh 0.119 0.116 + 0.001*sl 0.116 + 0.001*sl 0.116 + 0.001*sl t phl 0.158 0.154 + 0.002*sl 0.155 + 0.002*sl 0.155 + 0.002*sl *group1 : sl < 482, *group2 : 482 sl < < = = 722, *group3 : 722 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.059 0.056 + 0.002*sl 0.054 + 0.002*sl 0.054 + 0.002*sl t f 0.056 0.052 + 0.002*sl 0.049 + 0.002*sl 0.048 + 0.002*sl t plh 0.145 0.143 + 0.001*sl 0.144 + 0.001*sl 0.144 + 0.001*sl t phl 0.191 0.189 + 0.001*sl 0.190 + 0.001*sl 0.190 + 0.001*sl *group1 : sl < 962, *group2 : 962 sl < < = = 1443, *group3 : 1443 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.060 0.057 + 0.001*sl 0.055 + 0.001*sl 0.054 + 0.001*sl t f 0.055 0.052 + 0.001*sl 0.049 + 0.001*sl 0.048 + 0.001*sl t plh 0.154 0.153 + 0.000*sl 0.153 + 0.000*sl 0.153 + 0.000*sl t phl 0.189 0.188 + 0.001*sl 0.189 + 0.001*sl 0.189 + 0.001*sl *group1 : sl < 1443, *group2 : 1443 sl < < = = 2165, *group3 : 2165 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t r 0.062 0.061 + 0.001*sl 0.057 + 0.001*sl 0.056 + 0.001*sl t f 0.058 0.056 + 0.001*sl 0.051 + 0.001*sl 0.050 + 0.001*sl t plh 0.173 0.172 + 0.000*sl 0.173 + 0.000*sl 0.173 + 0.000*sl t phl 0.212 0.211 + 0.000*sl 0.212 + 0.000*sl 0.212 + 0.000*sl *group1 : sl < 1923, *group2 : 1923 sl < < = = 2887, *group3 : 2887 < sl
samsung asic 3-451 STD111 decoders cell list cell name function description dc4 2 > 4 non-inverting decoder dc4i 2 > 4 inverting decoder dc8i 3 > 8 inverting decoder
STD111 3-452 samsung asic dc4 2 > 4 non-inverting decoder logic symbol schematic diagram s0 s1 y0 y1 y2 y3 y0 y1 y2 y3 s0 s1 truth table cell data s1 s0 y0 y1 y2 y3 001000 010100 100010 110001 input load (sl) gate count s0 s1 6.00 2.5 2.4
samsung asic 3-453 STD111 dc4 2 > 4 non-inverting decoder switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) dc4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s0 to y0 t r 0.113 0.065 + 0.024*sl 0.052 + 0.028*sl 0.045 + 0.028*sl t f 0.096 0.050 + 0.023*sl 0.047 + 0.024*sl 0.041 + 0.024*sl t plh 0.202 0.171 + 0.015*sl 0.180 + 0.013*sl 0.184 + 0.012*sl t phl 0.205 0.175 + 0.015*sl 0.183 + 0.013*sl 0.187 + 0.013*sl s1 to y0 t r 0.111 0.058 + 0.026*sl 0.053 + 0.028*sl 0.047 + 0.028*sl t f 0.099 0.052 + 0.023*sl 0.052 + 0.023*sl 0.044 + 0.024*sl t plh 0.204 0.174 + 0.015*sl 0.182 + 0.013*sl 0.186 + 0.012*sl t phl 0.222 0.191 + 0.015*sl 0.199 + 0.013*sl 0.204 + 0.013*sl s0 to y1 t r 0.110 0.056 + 0.027*sl 0.054 + 0.028*sl 0.047 + 0.028*sl t f 0.097 0.051 + 0.023*sl 0.047 + 0.024*sl 0.043 + 0.024*sl t plh 0.142 0.113 + 0.014*sl 0.119 + 0.013*sl 0.123 + 0.012*sl t phl 0.158 0.128 + 0.015*sl 0.135 + 0.013*sl 0.140 + 0.013*sl s1 to y1 t r 0.108 0.054 + 0.027*sl 0.051 + 0.028*sl 0.046 + 0.028*sl t f 0.099 0.053 + 0.023*sl 0.052 + 0.023*sl 0.044 + 0.024*sl t plh 0.203 0.174 + 0.014*sl 0.181 + 0.013*sl 0.184 + 0.012*sl t phl 0.220 0.190 + 0.015*sl 0.197 + 0.013*sl 0.202 + 0.013*sl s0 to y2 t r 0.109 0.056 + 0.027*sl 0.052 + 0.028*sl 0.046 + 0.028*sl t f 0.096 0.048 + 0.024*sl 0.049 + 0.024*sl 0.042 + 0.024*sl t plh 0.203 0.174 + 0.015*sl 0.181 + 0.013*sl 0.185 + 0.012*sl t phl 0.206 0.175 + 0.015*sl 0.183 + 0.013*sl 0.188 + 0.013*sl s1 to y2 t r 0.110 0.056 + 0.027*sl 0.054 + 0.027*sl 0.046 + 0.028*sl t f 0.099 0.053 + 0.023*sl 0.051 + 0.023*sl 0.044 + 0.024*sl t plh 0.137 0.107 + 0.015*sl 0.115 + 0.013*sl 0.118 + 0.012*sl t phl 0.173 0.142 + 0.015*sl 0.150 + 0.013*sl 0.154 + 0.013*sl s0 to y3 t r 0.111 0.056 + 0.027*sl 0.054 + 0.028*sl 0.048 + 0.028*sl t f 0.095 0.050 + 0.022*sl 0.048 + 0.023*sl 0.044 + 0.024*sl t plh 0.143 0.114 + 0.014*sl 0.120 + 0.013*sl 0.124 + 0.012*sl t phl 0.157 0.127 + 0.015*sl 0.134 + 0.013*sl 0.139 + 0.012*sl s1 to y3 t r 0.110 0.056 + 0.027*sl 0.054 + 0.028*sl 0.047 + 0.028*sl t f 0.097 0.051 + 0.023*sl 0.052 + 0.023*sl 0.044 + 0.024*sl t plh 0.135 0.106 + 0.015*sl 0.113 + 0.013*sl 0.116 + 0.012*sl t phl 0.168 0.138 + 0.015*sl 0.145 + 0.013*sl 0.150 + 0.012*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-454 samsung asic dc4i 2 > 4 inverting decoder logic symbol schematic diagram s0 s1 yn0 yn1 yn2 yn3 yn0 yn1 yn2 yn3 s0 s1 truth table cell data s1 s0 yn0 yn1 yn2 yn3 000111 011011 101101 111110 input load (sl) gate count s0 s1 4.00 2.9 3.1
samsung asic 3-455 STD111 dc4i 2 > 4 inverting decoder switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) dc4i path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s0 to yn0 t r 0.123 0.057 + 0.033*sl 0.053 + 0.034*sl 0.047 + 0.035*sl t f 0.127 0.062 + 0.032*sl 0.059 + 0.033*sl 0.053 + 0.034*sl t plh 0.155 0.122 + 0.016*sl 0.127 + 0.015*sl 0.128 + 0.015*sl t phl 0.162 0.126 + 0.018*sl 0.132 + 0.016*sl 0.134 + 0.016*sl s1 to yn0 t r 0.141 0.077 + 0.032*sl 0.069 + 0.034*sl 0.063 + 0.035*sl t f 0.124 0.061 + 0.032*sl 0.054 + 0.034*sl 0.051 + 0.034*sl t plh 0.168 0.136 + 0.016*sl 0.138 + 0.015*sl 0.139 + 0.015*sl t phl 0.163 0.127 + 0.018*sl 0.131 + 0.017*sl 0.134 + 0.016*sl s0 to yn1 t r 0.146 0.086 + 0.030*sl 0.077 + 0.032*sl 0.059 + 0.034*sl t f 0.145 0.087 + 0.029*sl 0.077 + 0.032*sl 0.060 + 0.033*sl t plh 0.090 0.055 + 0.018*sl 0.065 + 0.015*sl 0.065 + 0.015*sl t phl 0.085 0.047 + 0.019*sl 0.059 + 0.016*sl 0.057 + 0.016*sl s1 to yn1 t r 0.144 0.084 + 0.030*sl 0.069 + 0.034*sl 0.063 + 0.035*sl t f 0.124 0.060 + 0.032*sl 0.054 + 0.033*sl 0.049 + 0.034*sl t plh 0.168 0.137 + 0.016*sl 0.139 + 0.015*sl 0.140 + 0.015*sl t phl 0.163 0.128 + 0.018*sl 0.132 + 0.016*sl 0.134 + 0.016*sl s0 to yn2 t r 0.125 0.060 + 0.032*sl 0.054 + 0.034*sl 0.048 + 0.035*sl t f 0.128 0.063 + 0.032*sl 0.059 + 0.033*sl 0.053 + 0.034*sl t plh 0.156 0.123 + 0.016*sl 0.127 + 0.015*sl 0.129 + 0.015*sl t phl 0.163 0.127 + 0.018*sl 0.133 + 0.016*sl 0.135 + 0.016*sl s1 to yn2 t r 0.161 0.102 + 0.029*sl 0.090 + 0.032*sl 0.074 + 0.034*sl t f 0.137 0.080 + 0.029*sl 0.067 + 0.032*sl 0.052 + 0.034*sl t plh 0.102 0.068 + 0.017*sl 0.075 + 0.015*sl 0.074 + 0.015*sl t phl 0.080 0.044 + 0.018*sl 0.054 + 0.016*sl 0.049 + 0.016*sl s0 to yn3 t r 0.146 0.086 + 0.030*sl 0.077 + 0.032*sl 0.059 + 0.034*sl t f 0.146 0.088 + 0.029*sl 0.078 + 0.032*sl 0.060 + 0.033*sl t plh 0.093 0.057 + 0.018*sl 0.067 + 0.015*sl 0.067 + 0.015*sl t phl 0.088 0.050 + 0.019*sl 0.061 + 0.016*sl 0.060 + 0.016*sl s1 to yn3 t r 0.161 0.102 + 0.029*sl 0.090 + 0.033*sl 0.075 + 0.034*sl t f 0.138 0.080 + 0.029*sl 0.068 + 0.032*sl 0.055 + 0.034*sl t plh 0.102 0.069 + 0.016*sl 0.075 + 0.015*sl 0.074 + 0.015*sl t phl 0.080 0.044 + 0.018*sl 0.051 + 0.016*sl 0.051 + 0.016*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-456 samsung asic dc8i 3 > 8 inverting decoder logic symbol schematic diagram s0 s2 yn0 yn2 yn4 yn6 s1 yn1 yn3 yn5 yn7 yn0 yn1 yn2 yn3 s2 s0 yn4 yn5 yn6 yn7 s1 truth table cell data s2 s1 s0 yn0 yn1 yn2 yn3 yn4 yn5 yn6 yn7 00001111111 00110111111 01011011111 01111101111 10011110111 10111111011 11011111101 11111111110 input load (sl) gate count s0 s1 s2 10.33 5.0 5.0 5.1
samsung asic 3-457 STD111 dc8i 3 > 8 inverting decoder switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) dc8i path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s0 to yn0 t r 0.169 0.080 + 0.044*sl 0.076 + 0.045*sl 0.069 + 0.046*sl t f 0.186 0.095 + 0.045*sl 0.090 + 0.047*sl 0.082 + 0.048*sl t plh 0.188 0.146 + 0.021*sl 0.150 + 0.020*sl 0.151 + 0.020*sl t phl 0.196 0.150 + 0.023*sl 0.154 + 0.022*sl 0.153 + 0.022*sl s1 to yn0 t r 0.191 0.103 + 0.044*sl 0.099 + 0.045*sl 0.091 + 0.046*sl t f 0.187 0.095 + 0.046*sl 0.091 + 0.047*sl 0.085 + 0.047*sl t plh 0.215 0.173 + 0.021*sl 0.176 + 0.020*sl 0.177 + 0.020*sl t phl 0.207 0.160 + 0.023*sl 0.165 + 0.022*sl 0.166 + 0.022*sl s2 to yn0 t r 0.213 0.127 + 0.043*sl 0.120 + 0.045*sl 0.112 + 0.046*sl t f 0.183 0.091 + 0.046*sl 0.087 + 0.047*sl 0.083 + 0.048*sl t plh 0.225 0.184 + 0.021*sl 0.186 + 0.020*sl 0.188 + 0.020*sl t phl 0.207 0.162 + 0.023*sl 0.165 + 0.022*sl 0.166 + 0.022*sl s0 to yn1 t r 0.182 0.100 + 0.041*sl 0.089 + 0.044*sl 0.074 + 0.045*sl t f 0.201 0.117 + 0.042*sl 0.104 + 0.045*sl 0.087 + 0.047*sl t plh 0.114 0.073 + 0.021*sl 0.077 + 0.020*sl 0.076 + 0.020*sl t phl 0.108 0.063 + 0.023*sl 0.067 + 0.022*sl 0.065 + 0.022*sl s1 to yn1 t r 0.190 0.104 + 0.043*sl 0.099 + 0.044*sl 0.093 + 0.045*sl t f 0.188 0.097 + 0.046*sl 0.093 + 0.047*sl 0.086 + 0.047*sl t plh 0.214 0.173 + 0.020*sl 0.176 + 0.020*sl 0.177 + 0.020*sl t phl 0.208 0.162 + 0.023*sl 0.166 + 0.022*sl 0.167 + 0.022*sl s2 to yn1 t r 0.215 0.128 + 0.044*sl 0.122 + 0.045*sl 0.114 + 0.046*sl t f 0.184 0.092 + 0.046*sl 0.089 + 0.047*sl 0.084 + 0.047*sl t plh 0.226 0.185 + 0.021*sl 0.188 + 0.020*sl 0.188 + 0.020*sl t phl 0.209 0.163 + 0.023*sl 0.166 + 0.022*sl 0.167 + 0.022*sl s0 to yn2 t r 0.170 0.082 + 0.044*sl 0.078 + 0.045*sl 0.071 + 0.046*sl t f 0.189 0.099 + 0.045*sl 0.093 + 0.047*sl 0.086 + 0.047*sl t plh 0.189 0.147 + 0.021*sl 0.151 + 0.020*sl 0.152 + 0.020*sl t phl 0.197 0.151 + 0.023*sl 0.155 + 0.022*sl 0.156 + 0.022*sl s1 to yn2 t r 0.205 0.123 + 0.041*sl 0.110 + 0.044*sl 0.095 + 0.046*sl t f 0.198 0.113 + 0.042*sl 0.100 + 0.046*sl 0.087 + 0.047*sl t plh 0.130 0.090 + 0.020*sl 0.092 + 0.020*sl 0.091 + 0.020*sl t phl 0.112 0.066 + 0.023*sl 0.072 + 0.021*sl 0.068 + 0.022*sl s2 to yn2 t r 0.216 0.129 + 0.043*sl 0.123 + 0.045*sl 0.114 + 0.046*sl t f 0.185 0.093 + 0.046*sl 0.089 + 0.047*sl 0.085 + 0.048*sl t plh 0.227 0.185 + 0.021*sl 0.188 + 0.020*sl 0.189 + 0.020*sl t phl 0.209 0.163 + 0.023*sl 0.166 + 0.022*sl 0.167 + 0.022*sl s0 to yn3 t r 0.181 0.098 + 0.041*sl 0.088 + 0.044*sl 0.072 + 0.046*sl t f 0.201 0.116 + 0.042*sl 0.104 + 0.045*sl 0.087 + 0.047*sl t plh 0.114 0.072 + 0.021*sl 0.077 + 0.020*sl 0.076 + 0.020*sl t phl 0.108 0.062 + 0.023*sl 0.066 + 0.022*sl 0.065 + 0.022*sl
STD111 3-458 samsung asic dc8i 3 > 8 inverting decoder switching characteristics (cont.) (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) dc8i path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s1 to yn3 t r 0.203 0.121 + 0.041*sl 0.108 + 0.044*sl 0.093 + 0.046*sl t f 0.194 0.108 + 0.043*sl 0.097 + 0.046*sl 0.086 + 0.047*sl t plh 0.129 0.089 + 0.020*sl 0.090 + 0.020*sl 0.089 + 0.020*sl t phl 0.110 0.064 + 0.023*sl 0.068 + 0.022*sl 0.068 + 0.022*sl s2 to yn3 t r 0.214 0.127 + 0.043*sl 0.121 + 0.045*sl 0.112 + 0.046*sl t f 0.183 0.091 + 0.046*sl 0.088 + 0.047*sl 0.083 + 0.048*sl t plh 0.227 0.186 + 0.021*sl 0.188 + 0.020*sl 0.189 + 0.020*sl t phl 0.209 0.163 + 0.023*sl 0.166 + 0.022*sl 0.167 + 0.022*sl s0 to yn4 t r 0.169 0.081 + 0.044*sl 0.077 + 0.045*sl 0.070 + 0.046*sl t f 0.187 0.097 + 0.045*sl 0.090 + 0.047*sl 0.083 + 0.047*sl t plh 0.188 0.146 + 0.021*sl 0.150 + 0.020*sl 0.151 + 0.020*sl t phl 0.196 0.150 + 0.023*sl 0.154 + 0.022*sl 0.153 + 0.022*sl s1 to yn4 t r 0.191 0.104 + 0.043*sl 0.099 + 0.045*sl 0.092 + 0.046*sl t f 0.187 0.096 + 0.046*sl 0.092 + 0.047*sl 0.086 + 0.047*sl t plh 0.214 0.173 + 0.021*sl 0.176 + 0.020*sl 0.177 + 0.020*sl t phl 0.207 0.161 + 0.023*sl 0.165 + 0.022*sl 0.167 + 0.022*sl s2 to yn4 t r 0.227 0.145 + 0.041*sl 0.132 + 0.044*sl 0.115 + 0.046*sl t f 0.190 0.103 + 0.043*sl 0.091 + 0.046*sl 0.081 + 0.047*sl t plh 0.140 0.100 + 0.020*sl 0.101 + 0.020*sl 0.100 + 0.020*sl t phl 0.109 0.063 + 0.023*sl 0.069 + 0.021*sl 0.064 + 0.022*sl s0 to yn5 t r 0.181 0.099 + 0.041*sl 0.088 + 0.044*sl 0.072 + 0.046*sl t f 0.200 0.116 + 0.042*sl 0.103 + 0.046*sl 0.086 + 0.047*sl t plh 0.115 0.073 + 0.021*sl 0.077 + 0.020*sl 0.077 + 0.020*sl t phl 0.108 0.063 + 0.023*sl 0.067 + 0.022*sl 0.065 + 0.022*sl s1 to yn5 t r 0.190 0.104 + 0.043*sl 0.098 + 0.044*sl 0.092 + 0.045*sl t f 0.187 0.096 + 0.046*sl 0.092 + 0.047*sl 0.085 + 0.047*sl t plh 0.213 0.172 + 0.020*sl 0.175 + 0.020*sl 0.176 + 0.020*sl t phl 0.207 0.160 + 0.023*sl 0.165 + 0.022*sl 0.166 + 0.022*sl s2 to yn5 t r 0.225 0.145 + 0.040*sl 0.132 + 0.044*sl 0.115 + 0.045*sl t f 0.190 0.102 + 0.044*sl 0.092 + 0.047*sl 0.084 + 0.047*sl t plh 0.139 0.099 + 0.020*sl 0.100 + 0.020*sl 0.099 + 0.020*sl t phl 0.108 0.062 + 0.023*sl 0.066 + 0.022*sl 0.065 + 0.022*sl s0 to yn6 t r 0.170 0.081 + 0.045*sl 0.077 + 0.046*sl 0.070 + 0.046*sl t f 0.188 0.097 + 0.045*sl 0.091 + 0.047*sl 0.084 + 0.047*sl t plh 0.189 0.147 + 0.021*sl 0.151 + 0.020*sl 0.151 + 0.020*sl t phl 0.196 0.150 + 0.023*sl 0.154 + 0.022*sl 0.154 + 0.022*sl s1 to yn6 t r 0.203 0.122 + 0.041*sl 0.109 + 0.044*sl 0.094 + 0.046*sl t f 0.196 0.111 + 0.043*sl 0.098 + 0.046*sl 0.085 + 0.047*sl t plh 0.130 0.089 + 0.020*sl 0.091 + 0.020*sl 0.090 + 0.020*sl t phl 0.111 0.065 + 0.023*sl 0.071 + 0.021*sl 0.067 + 0.022*sl
samsung asic 3-459 STD111 dc8i 3 > 8 inverting decoder switching characteristics (cont.) (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) dc8i path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s2 to yn6 t r 0.225 0.143 + 0.041*sl 0.131 + 0.044*sl 0.115 + 0.046*sl t f 0.189 0.102 + 0.044*sl 0.091 + 0.046*sl 0.081 + 0.047*sl t plh 0.139 0.099 + 0.020*sl 0.100 + 0.020*sl 0.100 + 0.020*sl t phl 0.108 0.062 + 0.023*sl 0.068 + 0.021*sl 0.064 + 0.022*sl s0 to yn7 t r 0.180 0.099 + 0.041*sl 0.089 + 0.043*sl 0.072 + 0.045*sl t f 0.202 0.117 + 0.042*sl 0.105 + 0.045*sl 0.088 + 0.047*sl t plh 0.113 0.072 + 0.021*sl 0.077 + 0.019*sl 0.076 + 0.019*sl t phl 0.109 0.063 + 0.023*sl 0.067 + 0.022*sl 0.066 + 0.022*sl s1 to yn7 t r 0.201 0.120 + 0.040*sl 0.107 + 0.044*sl 0.092 + 0.045*sl t f 0.194 0.107 + 0.044*sl 0.097 + 0.046*sl 0.086 + 0.047*sl t plh 0.128 0.089 + 0.020*sl 0.089 + 0.020*sl 0.088 + 0.020*sl t phl 0.110 0.064 + 0.023*sl 0.068 + 0.022*sl 0.067 + 0.022*sl s2 to yn7 t r 0.226 0.144 + 0.041*sl 0.132 + 0.044*sl 0.116 + 0.046*sl t f 0.190 0.101 + 0.044*sl 0.092 + 0.047*sl 0.085 + 0.047*sl t plh 0.140 0.100 + 0.020*sl 0.100 + 0.020*sl 0.100 + 0.020*sl t phl 0.108 0.063 + 0.023*sl 0.066 + 0.022*sl 0.066 + 0.022*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-460 samsung asic adders cell list cell name function description fadh full adder with 0.5x drive fa full adder with 1x drive fad2 full adder with 2x drive hadh half adder with 0.5x drive ha half adder with 1x drive had2 half adder with 2x drive scg23 full adder with one inverted input, 1x drive scg23d2 full adder with one inverted input, 2x drive
samsung asic 3-461 STD111 fadh/fa/fad2 full adder with 0.5x/1x/2x drive logic symbol cell data switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fadh input load (sl) gate count fadh fa fad2 fadh fa fad2 ci a b ci a b ci a b 0.4 0.6 0.5 0.8 1.0 1.0 0.8 1.0 1.0 5.00 6.00 6.00 ci a b s co path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t r 0.195 0.083 + 0.056*sl 0.077 + 0.058*sl 0.064 + 0.059*sl t f 0.177 0.081 + 0.048*sl 0.084 + 0.047*sl 0.074 + 0.048*sl t plh 0.415 0.356 + 0.029*sl 0.368 + 0.026*sl 0.372 + 0.026*sl t phl 0.434 0.371 + 0.032*sl 0.388 + 0.027*sl 0.401 + 0.026*sl b to s t r 0.194 0.084 + 0.055*sl 0.075 + 0.058*sl 0.060 + 0.059*sl t f 0.177 0.082 + 0.048*sl 0.084 + 0.047*sl 0.072 + 0.048*sl t plh 0.466 0.408 + 0.029*sl 0.419 + 0.026*sl 0.423 + 0.026*sl t phl 0.492 0.428 + 0.032*sl 0.446 + 0.027*sl 0.459 + 0.026*sl ci to s t r 0.193 0.081 + 0.056*sl 0.075 + 0.058*sl 0.060 + 0.059*sl t f 0.188 0.093 + 0.047*sl 0.096 + 0.046*sl 0.081 + 0.048*sl t plh 0.382 0.322 + 0.030*sl 0.335 + 0.026*sl 0.340 + 0.026*sl t phl 0.370 0.305 + 0.032*sl 0.325 + 0.027*sl 0.339 + 0.026*sl a to co t r 0.201 0.088 + 0.056*sl 0.080 + 0.058*sl 0.068 + 0.060*sl t f 0.183 0.085 + 0.049*sl 0.091 + 0.047*sl 0.081 + 0.048*sl t plh 0.414 0.355 + 0.030*sl 0.367 + 0.027*sl 0.371 + 0.026*sl t phl 0.433 0.370 + 0.032*sl 0.387 + 0.027*sl 0.400 + 0.026*sl b to co t r 0.239 0.137 + 0.051*sl 0.120 + 0.055*sl 0.086 + 0.059*sl t f 0.207 0.120 + 0.043*sl 0.112 + 0.046*sl 0.091 + 0.048*sl t plh 0.465 0.406 + 0.030*sl 0.418 + 0.026*sl 0.422 + 0.026*sl t phl 0.498 0.434 + 0.032*sl 0.452 + 0.027*sl 0.465 + 0.026*sl ci to co t r 0.200 0.086 + 0.057*sl 0.081 + 0.058*sl 0.068 + 0.060*sl t f 0.193 0.095 + 0.049*sl 0.103 + 0.047*sl 0.092 + 0.048*sl t plh 0.272 0.211 + 0.030*sl 0.225 + 0.027*sl 0.231 + 0.026*sl t phl 0.292 0.224 + 0.034*sl 0.247 + 0.028*sl 0.266 + 0.026*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl truth table ci a b s co 00000 10010 00110 10101 01010 11001 01101 11111
STD111 3-462 samsung asic fadh/fa/fad2 full adder with 0.5x/1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fa path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t r 0.124 0.073 + 0.026*sl 0.069 + 0.027*sl 0.062 + 0.028*sl t f 0.115 0.068 + 0.024*sl 0.072 + 0.023*sl 0.070 + 0.023*sl t plh 0.336 0.305 + 0.015*sl 0.313 + 0.013*sl 0.321 + 0.012*sl t phl 0.344 0.310 + 0.017*sl 0.320 + 0.014*sl 0.333 + 0.013*sl b to s t r 0.125 0.073 + 0.026*sl 0.071 + 0.027*sl 0.062 + 0.028*sl t f 0.116 0.067 + 0.024*sl 0.072 + 0.023*sl 0.070 + 0.023*sl t plh 0.382 0.351 + 0.015*sl 0.359 + 0.013*sl 0.367 + 0.012*sl t phl 0.402 0.368 + 0.017*sl 0.379 + 0.014*sl 0.392 + 0.013*sl ci to s t r 0.126 0.072 + 0.027*sl 0.073 + 0.027*sl 0.064 + 0.028*sl t f 0.124 0.076 + 0.024*sl 0.083 + 0.022*sl 0.079 + 0.023*sl t plh 0.304 0.273 + 0.016*sl 0.282 + 0.013*sl 0.289 + 0.012*sl t phl 0.299 0.264 + 0.017*sl 0.277 + 0.014*sl 0.290 + 0.013*sl a to co t r 0.122 0.069 + 0.027*sl 0.067 + 0.027*sl 0.061 + 0.028*sl t f 0.114 0.065 + 0.025*sl 0.071 + 0.023*sl 0.070 + 0.023*sl t plh 0.329 0.299 + 0.015*sl 0.306 + 0.013*sl 0.313 + 0.012*sl t phl 0.338 0.304 + 0.017*sl 0.315 + 0.014*sl 0.327 + 0.013*sl b to co t r 0.168 0.123 + 0.022*sl 0.117 + 0.024*sl 0.090 + 0.027*sl t f 0.163 0.122 + 0.021*sl 0.123 + 0.020*sl 0.107 + 0.022*sl t plh 0.376 0.345 + 0.015*sl 0.353 + 0.013*sl 0.360 + 0.012*sl t phl 0.403 0.369 + 0.017*sl 0.380 + 0.014*sl 0.392 + 0.013*sl ci to co t r 0.127 0.072 + 0.027*sl 0.074 + 0.027*sl 0.066 + 0.028*sl t f 0.126 0.077 + 0.024*sl 0.085 + 0.023*sl 0.082 + 0.023*sl t plh 0.220 0.189 + 0.016*sl 0.198 + 0.013*sl 0.207 + 0.012*sl t phl 0.225 0.189 + 0.018*sl 0.202 + 0.015*sl 0.218 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-463 STD111 fadh/fa/fad2 full adder with 0.5x/1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) fad2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t r 0.106 0.079 + 0.013*sl 0.079 + 0.013*sl 0.074 + 0.014*sl t f 0.112 0.086 + 0.013*sl 0.089 + 0.012*sl 0.094 + 0.012*sl t plh 0.346 0.326 + 0.010*sl 0.335 + 0.007*sl 0.351 + 0.006*sl t phl 0.355 0.333 + 0.011*sl 0.344 + 0.008*sl 0.365 + 0.007*sl b to s t r 0.107 0.079 + 0.014*sl 0.080 + 0.013*sl 0.074 + 0.014*sl t f 0.110 0.084 + 0.013*sl 0.089 + 0.012*sl 0.091 + 0.012*sl t plh 0.393 0.373 + 0.010*sl 0.383 + 0.007*sl 0.399 + 0.006*sl t phl 0.408 0.385 + 0.011*sl 0.397 + 0.008*sl 0.420 + 0.007*sl ci to s t r 0.106 0.079 + 0.014*sl 0.080 + 0.013*sl 0.074 + 0.014*sl t f 0.111 0.085 + 0.013*sl 0.089 + 0.012*sl 0.094 + 0.012*sl t plh 0.333 0.313 + 0.010*sl 0.323 + 0.007*sl 0.340 + 0.006*sl t phl 0.326 0.303 + 0.012*sl 0.315 + 0.008*sl 0.339 + 0.007*sl a to co t r 0.103 0.076 + 0.013*sl 0.076 + 0.014*sl 0.071 + 0.014*sl t f 0.105 0.079 + 0.013*sl 0.082 + 0.012*sl 0.086 + 0.012*sl t plh 0.338 0.319 + 0.009*sl 0.327 + 0.007*sl 0.342 + 0.006*sl t phl 0.347 0.325 + 0.011*sl 0.335 + 0.008*sl 0.356 + 0.007*sl b to co t r 0.152 0.133 + 0.010*sl 0.124 + 0.012*sl 0.102 + 0.013*sl t f 0.164 0.145 + 0.010*sl 0.144 + 0.010*sl 0.126 + 0.011*sl t plh 0.381 0.361 + 0.010*sl 0.370 + 0.007*sl 0.385 + 0.006*sl t phl 0.404 0.383 + 0.011*sl 0.393 + 0.008*sl 0.414 + 0.007*sl ci to co t r 0.106 0.079 + 0.013*sl 0.078 + 0.014*sl 0.075 + 0.014*sl t f 0.112 0.085 + 0.014*sl 0.090 + 0.012*sl 0.096 + 0.012*sl t plh 0.226 0.205 + 0.010*sl 0.215 + 0.007*sl 0.232 + 0.006*sl t phl 0.230 0.206 + 0.012*sl 0.219 + 0.009*sl 0.245 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-464 samsung asic hadh/ha/had2 half adder with 0.5x/1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count hadh ha had2 hadh ha had2 ababab 0.8 1.1 1.4 2.0 1.5 2.3 3.00 3.67 4.00 a b s co a s co b truth table absco 0000 0110 1010 1101
samsung asic 3-465 STD111 hadh/ha/had2 half adder with 0.5x/1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) hadh ha path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t r 0.193 0.081 + 0.056*sl 0.075 + 0.058*sl 0.061 + 0.059*sl t f 0.185 0.090 + 0.048*sl 0.094 + 0.047*sl 0.079 + 0.048*sl t plh 0.311 0.252 + 0.029*sl 0.264 + 0.026*sl 0.268 + 0.026*sl t phl 0.312 0.247 + 0.032*sl 0.267 + 0.027*sl 0.279 + 0.026*sl b to s t r 0.187 0.074 + 0.057*sl 0.069 + 0.058*sl 0.058 + 0.059*sl t f 0.175 0.079 + 0.048*sl 0.081 + 0.047*sl 0.069 + 0.048*sl t plh 0.238 0.178 + 0.030*sl 0.191 + 0.026*sl 0.196 + 0.026*sl t phl 0.250 0.186 + 0.032*sl 0.205 + 0.027*sl 0.218 + 0.026*sl a to co t r 0.181 0.065 + 0.058*sl 0.058 + 0.060*sl 0.048 + 0.061*sl t f 0.154 0.060 + 0.047*sl 0.056 + 0.048*sl 0.044 + 0.049*sl t plh 0.182 0.126 + 0.028*sl 0.133 + 0.026*sl 0.134 + 0.026*sl t phl 0.213 0.156 + 0.028*sl 0.166 + 0.026*sl 0.169 + 0.026*sl b to co t r 0.180 0.064 + 0.058*sl 0.057 + 0.060*sl 0.048 + 0.061*sl t f 0.151 0.057 + 0.047*sl 0.051 + 0.048*sl 0.042 + 0.049*sl t plh 0.187 0.131 + 0.028*sl 0.137 + 0.026*sl 0.139 + 0.026*sl t phl 0.198 0.142 + 0.028*sl 0.151 + 0.026*sl 0.153 + 0.026*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t r 0.125 0.071 + 0.027*sl 0.070 + 0.027*sl 0.062 + 0.028*sl t f 0.125 0.077 + 0.024*sl 0.082 + 0.023*sl 0.076 + 0.023*sl t plh 0.244 0.213 + 0.016*sl 0.222 + 0.013*sl 0.229 + 0.012*sl t phl 0.244 0.209 + 0.018*sl 0.221 + 0.014*sl 0.234 + 0.013*sl b to s t r 0.118 0.064 + 0.027*sl 0.064 + 0.027*sl 0.057 + 0.028*sl t f 0.113 0.063 + 0.025*sl 0.069 + 0.023*sl 0.066 + 0.024*sl t plh 0.185 0.154 + 0.016*sl 0.163 + 0.013*sl 0.170 + 0.012*sl t phl 0.195 0.160 + 0.017*sl 0.172 + 0.014*sl 0.185 + 0.013*sl a to co t r 0.111 0.057 + 0.027*sl 0.054 + 0.028*sl 0.047 + 0.028*sl t f 0.099 0.054 + 0.023*sl 0.051 + 0.023*sl 0.044 + 0.024*sl t plh 0.134 0.105 + 0.014*sl 0.112 + 0.013*sl 0.115 + 0.012*sl t phl 0.168 0.137 + 0.015*sl 0.145 + 0.013*sl 0.149 + 0.013*sl b to co t r 0.110 0.055 + 0.027*sl 0.054 + 0.028*sl 0.047 + 0.028*sl t f 0.098 0.047 + 0.025*sl 0.057 + 0.023*sl 0.042 + 0.024*sl t plh 0.139 0.110 + 0.014*sl 0.116 + 0.013*sl 0.120 + 0.012*sl t phl 0.153 0.123 + 0.015*sl 0.130 + 0.013*sl 0.134 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-466 samsung asic hadh/ha/had2 half adder with 0.5x/1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) had2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t r 0.109 0.082 + 0.014*sl 0.084 + 0.013*sl 0.078 + 0.014*sl t f 0.111 0.086 + 0.013*sl 0.090 + 0.012*sl 0.094 + 0.011*sl t plh 0.246 0.227 + 0.010*sl 0.236 + 0.007*sl 0.252 + 0.006*sl t phl 0.250 0.227 + 0.011*sl 0.239 + 0.008*sl 0.262 + 0.007*sl b to s t r 0.101 0.074 + 0.014*sl 0.074 + 0.014*sl 0.072 + 0.014*sl t f 0.101 0.076 + 0.013*sl 0.079 + 0.012*sl 0.085 + 0.012*sl t plh 0.192 0.172 + 0.010*sl 0.181 + 0.007*sl 0.198 + 0.006*sl t phl 0.200 0.178 + 0.011*sl 0.189 + 0.008*sl 0.212 + 0.007*sl a to co t r 0.087 0.061 + 0.013*sl 0.058 + 0.014*sl 0.052 + 0.014*sl t f 0.075 0.052 + 0.012*sl 0.053 + 0.011*sl 0.048 + 0.012*sl t plh 0.146 0.128 + 0.009*sl 0.136 + 0.007*sl 0.147 + 0.006*sl t phl 0.161 0.143 + 0.009*sl 0.151 + 0.007*sl 0.163 + 0.006*sl b to co t r 0.085 0.057 + 0.014*sl 0.059 + 0.014*sl 0.052 + 0.014*sl t f 0.073 0.049 + 0.012*sl 0.051 + 0.011*sl 0.045 + 0.012*sl t plh 0.157 0.139 + 0.009*sl 0.146 + 0.007*sl 0.157 + 0.006*sl t phl 0.153 0.135 + 0.009*sl 0.143 + 0.007*sl 0.154 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-467 STD111 scg23/scg23d2 full adder with one inverted input, 1x/2x drive logic symbol cell data input load (sl) gate count scg23 scg23d2 scg23 scg23d2 ci an b ci an b 0.8 0.7 1.0 0.8 0.6 1.0 6.33 6.33 an b ci s co truth table an b ci s co 00010 00101 01001 01111 10000 10110 11010 11101
STD111 3-468 samsung asic scg23/scg23d2 full adder with one inverted input, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg23 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* an to s t r 0.124 0.071 + 0.027*sl 0.069 + 0.027*sl 0.062 + 0.028*sl t f 0.116 0.067 + 0.024*sl 0.072 + 0.023*sl 0.071 + 0.023*sl t plh 0.398 0.367 + 0.015*sl 0.376 + 0.013*sl 0.383 + 0.013*sl t phl 0.395 0.361 + 0.017*sl 0.372 + 0.014*sl 0.385 + 0.013*sl b to s t r 0.126 0.073 + 0.026*sl 0.071 + 0.027*sl 0.062 + 0.028*sl t f 0.116 0.067 + 0.024*sl 0.072 + 0.023*sl 0.070 + 0.023*sl t plh 0.382 0.351 + 0.016*sl 0.360 + 0.013*sl 0.367 + 0.013*sl t phl 0.402 0.368 + 0.017*sl 0.379 + 0.014*sl 0.392 + 0.013*sl ci to s t r 0.127 0.073 + 0.027*sl 0.072 + 0.027*sl 0.064 + 0.028*sl t f 0.124 0.076 + 0.024*sl 0.083 + 0.022*sl 0.079 + 0.023*sl t plh 0.304 0.273 + 0.016*sl 0.282 + 0.013*sl 0.289 + 0.012*sl t phl 0.300 0.266 + 0.017*sl 0.278 + 0.014*sl 0.292 + 0.013*sl an to co t r 0.123 0.070 + 0.026*sl 0.067 + 0.027*sl 0.062 + 0.028*sl t f 0.117 0.067 + 0.025*sl 0.070 + 0.024*sl 0.072 + 0.024*sl t plh 0.392 0.362 + 0.015*sl 0.369 + 0.013*sl 0.376 + 0.012*sl t phl 0.393 0.359 + 0.017*sl 0.369 + 0.014*sl 0.381 + 0.013*sl b to co t r 0.169 0.124 + 0.022*sl 0.118 + 0.024*sl 0.091 + 0.027*sl t f 0.165 0.122 + 0.021*sl 0.124 + 0.021*sl 0.106 + 0.023*sl t plh 0.377 0.346 + 0.015*sl 0.354 + 0.013*sl 0.361 + 0.012*sl t phl 0.405 0.371 + 0.017*sl 0.381 + 0.014*sl 0.394 + 0.013*sl ci to co t r 0.127 0.073 + 0.027*sl 0.075 + 0.027*sl 0.067 + 0.028*sl t f 0.128 0.078 + 0.025*sl 0.084 + 0.023*sl 0.084 + 0.023*sl t plh 0.221 0.189 + 0.016*sl 0.199 + 0.013*sl 0.208 + 0.012*sl t phl 0.228 0.191 + 0.018*sl 0.205 + 0.015*sl 0.221 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-469 STD111 scg23/scg23d2 full adder with one inverted input, 1x/2x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) scg23d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* an to s t r 0.106 0.079 + 0.014*sl 0.080 + 0.013*sl 0.073 + 0.014*sl t f 0.112 0.087 + 0.013*sl 0.089 + 0.012*sl 0.095 + 0.012*sl t plh 0.420 0.401 + 0.010*sl 0.410 + 0.007*sl 0.426 + 0.006*sl t phl 0.422 0.400 + 0.011*sl 0.411 + 0.008*sl 0.433 + 0.007*sl b to s t r 0.107 0.080 + 0.014*sl 0.081 + 0.013*sl 0.075 + 0.014*sl t f 0.111 0.086 + 0.013*sl 0.089 + 0.012*sl 0.091 + 0.012*sl t plh 0.396 0.376 + 0.010*sl 0.386 + 0.007*sl 0.403 + 0.006*sl t phl 0.411 0.388 + 0.011*sl 0.400 + 0.008*sl 0.423 + 0.007*sl ci to s t r 0.107 0.079 + 0.014*sl 0.081 + 0.013*sl 0.074 + 0.014*sl t f 0.111 0.085 + 0.013*sl 0.089 + 0.012*sl 0.094 + 0.012*sl t plh 0.335 0.315 + 0.010*sl 0.325 + 0.007*sl 0.342 + 0.006*sl t phl 0.328 0.305 + 0.012*sl 0.317 + 0.008*sl 0.341 + 0.007*sl an to co t r 0.104 0.077 + 0.013*sl 0.076 + 0.014*sl 0.072 + 0.014*sl t f 0.105 0.079 + 0.013*sl 0.082 + 0.012*sl 0.087 + 0.012*sl t plh 0.414 0.395 + 0.009*sl 0.403 + 0.007*sl 0.417 + 0.006*sl t phl 0.412 0.391 + 0.011*sl 0.401 + 0.008*sl 0.421 + 0.007*sl b to co t r 0.152 0.133 + 0.010*sl 0.124 + 0.012*sl 0.103 + 0.013*sl t f 0.166 0.146 + 0.010*sl 0.146 + 0.010*sl 0.129 + 0.011*sl t plh 0.384 0.364 + 0.010*sl 0.373 + 0.007*sl 0.388 + 0.006*sl t phl 0.406 0.384 + 0.011*sl 0.394 + 0.008*sl 0.416 + 0.007*sl ci to co t r 0.107 0.080 + 0.013*sl 0.079 + 0.014*sl 0.076 + 0.014*sl t f 0.112 0.085 + 0.013*sl 0.091 + 0.012*sl 0.097 + 0.012*sl t plh 0.227 0.206 + 0.010*sl 0.216 + 0.007*sl 0.233 + 0.006*sl t phl 0.230 0.207 + 0.012*sl 0.219 + 0.008*sl 0.245 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-470 samsung asic multiplexers cell list cell name function description mx2dh 2 > 1 non-inverting mux with 0.5x drive mx2 2 > 1 non-inverting mux mx2d2 2 > 1 non-inverting mux with 2x drive mx2d4 2 > 1 non-inverting mux with 4x drive mx2x4 4-bit 2 > 1 non-inverting mux mx2idh 2 > 1 inverting mux with 0.5x drive mx2i 2 > 1 inverting mux mx2id2 2 > 1 inverting mux with 2x drive mx2id4 2 > 1 inverting mux with 4x drive mx2idha 2 > 1 inverting mux with separate s and sn inputs, 0.5x drive mx2ia 2 > 1 inverting mux with separate s and sn inputs mx2id2a 2 > 1 inverting mux with separate s and sn inputs, 2x drive mx2id4a 2 > 1 inverting mux with separate s and sn inputs, 4x drive mx2ix4 4-bit 2 > 1 inverting mux mx3i 3 > 1 inverting mux mx3id2 3 > 1 inverting mux with 2x drive mx3id4 3 > 1 inverting mux with 4x drive mx4 4 > 1 non-inverting mux mx4d2 4 > 1 non-inverting mux with 2x drive mx4d4 4 > 1 non-inverting mux with 4x drive mx8 8 > 1 non-inverting mux mx8d2 8 > 1 non-inverting mux with 2x drive mx8d4 8 > 1 non-inverting mux with 4x drive
samsung asic 3-471 STD111 mx2dh/mx2/mx2d2/mx2d4 2 > 1 non-inverting mux with 0.5x/1x/2x/4x drive logic symbol cell data schematic diagram input load (sl) mx2dh mx2 mx2d2 mx2d4 d0d1sd0d1sd0d1sd0d1s 0.4 0.4 0.7 0.8 0.8 1.2 0.8 0.8 1.2 0.8 0.8 1.2 gate count mx2dh mx2 mx2d2 mx2d4 2.67 2.33 2.67 3.33 d0 d1 y s s sb y sb s s d0 d1 truth table d0 d1 s y 0x00 1x01 x010 x111
STD111 3-472 samsung asic mx2dh/mx2/mx2d2/mx2d4 2 > 1 non-inverting mux with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx2dh mx2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t r 0.187 0.075 + 0.056*sl 0.066 + 0.058*sl 0.054 + 0.059*sl t f 0.174 0.079 + 0.047*sl 0.079 + 0.047*sl 0.067 + 0.049*sl t plh 0.225 0.167 + 0.029*sl 0.178 + 0.026*sl 0.180 + 0.026*sl t phl 0.239 0.176 + 0.032*sl 0.194 + 0.027*sl 0.205 + 0.026*sl d1 to y t r 0.187 0.075 + 0.056*sl 0.067 + 0.058*sl 0.054 + 0.059*sl t f 0.174 0.080 + 0.047*sl 0.080 + 0.047*sl 0.067 + 0.049*sl t plh 0.229 0.171 + 0.029*sl 0.182 + 0.026*sl 0.185 + 0.026*sl t phl 0.243 0.180 + 0.032*sl 0.198 + 0.027*sl 0.209 + 0.026*sl s to y t r 0.186 0.073 + 0.056*sl 0.067 + 0.058*sl 0.055 + 0.059*sl t f 0.171 0.075 + 0.048*sl 0.078 + 0.047*sl 0.066 + 0.049*sl t plh 0.236 0.178 + 0.029*sl 0.188 + 0.026*sl 0.191 + 0.026*sl t phl 0.243 0.180 + 0.032*sl 0.198 + 0.027*sl 0.209 + 0.026*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t r 0.116 0.062 + 0.027*sl 0.061 + 0.027*sl 0.054 + 0.028*sl t f 0.114 0.065 + 0.024*sl 0.069 + 0.023*sl 0.065 + 0.024*sl t plh 0.176 0.146 + 0.015*sl 0.154 + 0.013*sl 0.160 + 0.012*sl t phl 0.186 0.152 + 0.017*sl 0.163 + 0.014*sl 0.175 + 0.013*sl d1 to y t r 0.117 0.064 + 0.027*sl 0.061 + 0.027*sl 0.054 + 0.028*sl t f 0.114 0.065 + 0.024*sl 0.070 + 0.023*sl 0.066 + 0.024*sl t plh 0.179 0.149 + 0.015*sl 0.157 + 0.013*sl 0.163 + 0.012*sl t phl 0.187 0.153 + 0.017*sl 0.164 + 0.014*sl 0.176 + 0.013*sl s to y t r 0.116 0.061 + 0.027*sl 0.062 + 0.027*sl 0.053 + 0.028*sl t f 0.111 0.061 + 0.025*sl 0.066 + 0.023*sl 0.063 + 0.024*sl t plh 0.180 0.150 + 0.015*sl 0.158 + 0.013*sl 0.164 + 0.012*sl t phl 0.190 0.156 + 0.017*sl 0.167 + 0.014*sl 0.179 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-473 STD111 mx2dh/mx2/mx2d2/mx2d4 2 > 1 non-inverting mux with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx2d2 mx2d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t r 0.099 0.072 + 0.014*sl 0.073 + 0.013*sl 0.067 + 0.014*sl t f 0.101 0.074 + 0.013*sl 0.080 + 0.012*sl 0.083 + 0.012*sl t plh 0.186 0.167 + 0.010*sl 0.176 + 0.007*sl 0.190 + 0.006*sl t phl 0.195 0.173 + 0.011*sl 0.184 + 0.008*sl 0.206 + 0.007*sl d1 to y t r 0.099 0.072 + 0.014*sl 0.072 + 0.014*sl 0.067 + 0.014*sl t f 0.102 0.075 + 0.013*sl 0.080 + 0.012*sl 0.082 + 0.012*sl t plh 0.189 0.170 + 0.010*sl 0.178 + 0.007*sl 0.193 + 0.006*sl t phl 0.196 0.174 + 0.011*sl 0.185 + 0.008*sl 0.207 + 0.007*sl s to y t r 0.099 0.073 + 0.013*sl 0.071 + 0.014*sl 0.065 + 0.014*sl t f 0.098 0.070 + 0.014*sl 0.077 + 0.012*sl 0.081 + 0.012*sl t plh 0.186 0.167 + 0.010*sl 0.176 + 0.007*sl 0.191 + 0.006*sl t phl 0.196 0.174 + 0.011*sl 0.185 + 0.008*sl 0.208 + 0.007*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t r 0.116 0.102 + 0.007*sl 0.103 + 0.007*sl 0.101 + 0.007*sl t f 0.123 0.107 + 0.008*sl 0.113 + 0.006*sl 0.124 + 0.006*sl t plh 0.228 0.215 + 0.006*sl 0.223 + 0.004*sl 0.249 + 0.003*sl t phl 0.242 0.228 + 0.007*sl 0.237 + 0.005*sl 0.269 + 0.004*sl d1 to y t r 0.117 0.103 + 0.007*sl 0.103 + 0.007*sl 0.102 + 0.007*sl t f 0.123 0.107 + 0.008*sl 0.114 + 0.006*sl 0.124 + 0.006*sl t plh 0.231 0.219 + 0.006*sl 0.227 + 0.004*sl 0.252 + 0.003*sl t phl 0.243 0.228 + 0.007*sl 0.237 + 0.005*sl 0.270 + 0.004*sl s to y t r 0.116 0.102 + 0.007*sl 0.103 + 0.007*sl 0.101 + 0.007*sl t f 0.122 0.105 + 0.008*sl 0.113 + 0.006*sl 0.123 + 0.006*sl t plh 0.223 0.211 + 0.006*sl 0.219 + 0.004*sl 0.244 + 0.003*sl t phl 0.239 0.224 + 0.007*sl 0.233 + 0.005*sl 0.266 + 0.004*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-474 samsung asic mx2x4 4-bit 2 > 1 non-inverting mux logic symbol cell data input load (sl) gate count d00 d10 d01 d11 d02 d12 d03 d13 s 8.00 0.8 0.8 0.9 0.8 0.8 0.8 0.8 0.8 3.4 y0 y1 y2 y3 d00 d10 d01 d11 d02 d12 d03 d13 s truth table s y0y1y2y3 0 d00 d01 d02 d03 1 d10 d11 d12 d13
samsung asic 3-475 STD111 mx2x4 4-bit 2 > 1 non-inverting mux switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx2x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d00 to y0 t r 0.119 0.066 + 0.027*sl 0.063 + 0.027*sl 0.057 + 0.028*sl t f 0.115 0.066 + 0.024*sl 0.071 + 0.023*sl 0.067 + 0.024*sl t plh 0.181 0.150 + 0.015*sl 0.158 + 0.013*sl 0.164 + 0.012*sl t phl 0.187 0.153 + 0.017*sl 0.164 + 0.014*sl 0.176 + 0.013*sl d10 to y0 t r 0.119 0.065 + 0.027*sl 0.064 + 0.027*sl 0.056 + 0.028*sl t f 0.116 0.066 + 0.025*sl 0.073 + 0.023*sl 0.068 + 0.024*sl t plh 0.181 0.150 + 0.015*sl 0.159 + 0.013*sl 0.164 + 0.012*sl t phl 0.191 0.156 + 0.017*sl 0.168 + 0.014*sl 0.180 + 0.013*sl s to y0 t r 0.122 0.069 + 0.027*sl 0.066 + 0.027*sl 0.058 + 0.028*sl t f 0.115 0.065 + 0.025*sl 0.071 + 0.023*sl 0.066 + 0.024*sl t plh 0.201 0.171 + 0.015*sl 0.179 + 0.013*sl 0.185 + 0.012*sl t phl 0.213 0.178 + 0.017*sl 0.189 + 0.014*sl 0.201 + 0.013*sl d01 to y1 t r 0.118 0.064 + 0.027*sl 0.062 + 0.027*sl 0.055 + 0.028*sl t f 0.114 0.065 + 0.024*sl 0.069 + 0.023*sl 0.065 + 0.024*sl t plh 0.179 0.148 + 0.015*sl 0.157 + 0.013*sl 0.162 + 0.012*sl t phl 0.186 0.151 + 0.017*sl 0.163 + 0.014*sl 0.174 + 0.013*sl d11 to y1 t r 0.116 0.062 + 0.027*sl 0.061 + 0.027*sl 0.054 + 0.028*sl t f 0.114 0.065 + 0.024*sl 0.069 + 0.023*sl 0.064 + 0.024*sl t plh 0.178 0.147 + 0.015*sl 0.156 + 0.013*sl 0.161 + 0.012*sl t phl 0.185 0.151 + 0.017*sl 0.162 + 0.014*sl 0.174 + 0.013*sl s to y1 t r 0.121 0.067 + 0.027*sl 0.065 + 0.027*sl 0.057 + 0.028*sl t f 0.112 0.063 + 0.025*sl 0.069 + 0.023*sl 0.064 + 0.024*sl t plh 0.201 0.170 + 0.015*sl 0.179 + 0.013*sl 0.185 + 0.012*sl t phl 0.209 0.175 + 0.017*sl 0.186 + 0.014*sl 0.198 + 0.013*sl d02 to y2 t r 0.117 0.065 + 0.026*sl 0.062 + 0.027*sl 0.056 + 0.028*sl t f 0.115 0.065 + 0.025*sl 0.071 + 0.023*sl 0.066 + 0.024*sl t plh 0.182 0.151 + 0.015*sl 0.160 + 0.013*sl 0.166 + 0.012*sl t phl 0.188 0.154 + 0.017*sl 0.165 + 0.014*sl 0.177 + 0.013*sl d12 to y2 t r 0.117 0.064 + 0.026*sl 0.062 + 0.027*sl 0.056 + 0.028*sl t f 0.115 0.066 + 0.024*sl 0.070 + 0.023*sl 0.066 + 0.024*sl t plh 0.179 0.149 + 0.015*sl 0.157 + 0.013*sl 0.163 + 0.012*sl t phl 0.187 0.153 + 0.017*sl 0.164 + 0.014*sl 0.176 + 0.013*sl s to y2 t r 0.120 0.068 + 0.026*sl 0.066 + 0.027*sl 0.057 + 0.028*sl t f 0.114 0.064 + 0.025*sl 0.070 + 0.023*sl 0.065 + 0.024*sl t plh 0.200 0.170 + 0.015*sl 0.179 + 0.013*sl 0.185 + 0.012*sl t phl 0.211 0.177 + 0.017*sl 0.188 + 0.014*sl 0.200 + 0.013*sl d03 to y3 t r 0.121 0.068 + 0.027*sl 0.065 + 0.027*sl 0.058 + 0.028*sl t f 0.115 0.067 + 0.024*sl 0.073 + 0.023*sl 0.068 + 0.023*sl t plh 0.180 0.150 + 0.015*sl 0.158 + 0.013*sl 0.164 + 0.012*sl t phl 0.189 0.156 + 0.017*sl 0.167 + 0.014*sl 0.178 + 0.013*sl
STD111 3-476 samsung asic mx2x4 4-bit 2 > 1 non-inverting mux switching characteristics (cont.) (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx2x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d13 to y3 t r 0.121 0.067 + 0.027*sl 0.064 + 0.027*sl 0.058 + 0.028*sl t f 0.115 0.068 + 0.024*sl 0.072 + 0.023*sl 0.067 + 0.023*sl t plh 0.180 0.150 + 0.015*sl 0.158 + 0.013*sl 0.164 + 0.012*sl t phl 0.188 0.154 + 0.017*sl 0.165 + 0.014*sl 0.176 + 0.013*sl s to y3 t r 0.124 0.071 + 0.026*sl 0.068 + 0.027*sl 0.060 + 0.028*sl t f 0.114 0.066 + 0.024*sl 0.071 + 0.023*sl 0.067 + 0.023*sl t plh 0.203 0.172 + 0.015*sl 0.181 + 0.013*sl 0.186 + 0.012*sl t phl 0.212 0.178 + 0.017*sl 0.189 + 0.014*sl 0.200 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-477 STD111 mx2idh/mx2i/mx2id2/mx2id4 2 > 1 inverting mux with 0.5x/1x/2x/4x drive logic symbol cell data schematic diagram input load (sl) mx2idh mx2i mx2id2 mx2id4 d0 d1 s d0 d1 s d0 d1 s d0 d1 s 0.5 0.6 0.8 1.0 1.1 1.7 1.1 1.2 1.7 1.1 1.2 1.7 gate count mx2idh mx2i mx2id2 mx2id4 2.00 2.00 3.00 3.33 d0 d1 yn s yn d0 s d1 truth table d0 d1 s yn 0x01 1x00 x011 x110
STD111 3-478 samsung asic mx2idh/mx2i/mx2id2/mx2id4 2 > 1 inverting mux with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx2idh mx2i path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t r 0.385 0.156 + 0.114*sl 0.141 + 0.118*sl 0.137 + 0.119*sl t f 0.253 0.115 + 0.069*sl 0.098 + 0.074*sl 0.082 + 0.075*sl t plh 0.195 0.094 + 0.051*sl 0.093 + 0.051*sl 0.093 + 0.051*sl t phl 0.145 0.073 + 0.036*sl 0.074 + 0.036*sl 0.075 + 0.036*sl d1 to yn t r 0.386 0.155 + 0.116*sl 0.145 + 0.118*sl 0.140 + 0.119*sl t f 0.311 0.174 + 0.069*sl 0.156 + 0.073*sl 0.139 + 0.075*sl t plh 0.225 0.122 + 0.052*sl 0.124 + 0.051*sl 0.126 + 0.051*sl t phl 0.184 0.110 + 0.037*sl 0.113 + 0.036*sl 0.114 + 0.036*sl s to yn t r 0.379 0.144 + 0.118*sl 0.140 + 0.119*sl 0.140 + 0.119*sl t f 0.276 0.134 + 0.071*sl 0.120 + 0.075*sl 0.111 + 0.076*sl t plh 0.256 0.154 + 0.051*sl 0.155 + 0.051*sl 0.155 + 0.051*sl t phl 0.220 0.147 + 0.037*sl 0.150 + 0.036*sl 0.150 + 0.036*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t r 0.255 0.151 + 0.052*sl 0.144 + 0.054*sl 0.129 + 0.055*sl t f 0.179 0.117 + 0.031*sl 0.106 + 0.034*sl 0.091 + 0.036*sl t plh 0.137 0.090 + 0.023*sl 0.089 + 0.024*sl 0.088 + 0.024*sl t phl 0.105 0.067 + 0.019*sl 0.073 + 0.017*sl 0.073 + 0.017*sl d1 to yn t r 0.253 0.147 + 0.053*sl 0.141 + 0.055*sl 0.133 + 0.055*sl t f 0.233 0.170 + 0.031*sl 0.161 + 0.034*sl 0.144 + 0.035*sl t plh 0.161 0.111 + 0.025*sl 0.114 + 0.024*sl 0.115 + 0.024*sl t phl 0.141 0.106 + 0.018*sl 0.107 + 0.017*sl 0.108 + 0.017*sl s to yn t r 0.248 0.142 + 0.053*sl 0.136 + 0.055*sl 0.130 + 0.055*sl t f 0.198 0.133 + 0.032*sl 0.124 + 0.035*sl 0.110 + 0.036*sl t plh 0.187 0.139 + 0.024*sl 0.140 + 0.024*sl 0.140 + 0.024*sl t phl 0.164 0.128 + 0.018*sl 0.131 + 0.017*sl 0.132 + 0.017*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
samsung asic 3-479 STD111 mx2idh/mx2i/mx2id2/mx2id4 2 > 1 inverting mux with 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx2id2 mx2id4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t r 0.079 0.053 + 0.013*sl 0.051 + 0.014*sl 0.042 + 0.014*sl t f 0.071 0.046 + 0.013*sl 0.051 + 0.011*sl 0.042 + 0.012*sl t plh 0.245 0.229 + 0.008*sl 0.234 + 0.007*sl 0.240 + 0.006*sl t phl 0.211 0.193 + 0.009*sl 0.200 + 0.007*sl 0.210 + 0.006*sl d1 to yn t r 0.079 0.053 + 0.013*sl 0.051 + 0.014*sl 0.042 + 0.014*sl t f 0.072 0.049 + 0.012*sl 0.051 + 0.011*sl 0.044 + 0.012*sl t plh 0.267 0.251 + 0.008*sl 0.257 + 0.007*sl 0.263 + 0.006*sl t phl 0.251 0.234 + 0.009*sl 0.241 + 0.007*sl 0.251 + 0.006*sl s to yn t r 0.080 0.054 + 0.013*sl 0.053 + 0.013*sl 0.041 + 0.014*sl t f 0.072 0.048 + 0.012*sl 0.050 + 0.011*sl 0.043 + 0.012*sl t plh 0.296 0.280 + 0.008*sl 0.286 + 0.007*sl 0.291 + 0.006*sl t phl 0.264 0.247 + 0.009*sl 0.254 + 0.007*sl 0.263 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t r 0.073 0.061 + 0.006*sl 0.059 + 0.007*sl 0.049 + 0.007*sl t f 0.066 0.053 + 0.006*sl 0.055 + 0.006*sl 0.051 + 0.006*sl t plh 0.263 0.254 + 0.005*sl 0.258 + 0.004*sl 0.269 + 0.003*sl t phl 0.223 0.213 + 0.005*sl 0.218 + 0.004*sl 0.233 + 0.003*sl d1 to yn t r 0.073 0.060 + 0.007*sl 0.060 + 0.007*sl 0.049 + 0.007*sl t f 0.067 0.056 + 0.006*sl 0.055 + 0.006*sl 0.052 + 0.006*sl t plh 0.285 0.275 + 0.005*sl 0.280 + 0.003*sl 0.290 + 0.003*sl t phl 0.261 0.251 + 0.005*sl 0.256 + 0.004*sl 0.272 + 0.003*sl s to yn t r 0.074 0.061 + 0.007*sl 0.060 + 0.007*sl 0.049 + 0.007*sl t f 0.066 0.052 + 0.007*sl 0.056 + 0.006*sl 0.051 + 0.006*sl t plh 0.315 0.305 + 0.005*sl 0.310 + 0.003*sl 0.321 + 0.003*sl t phl 0.278 0.268 + 0.005*sl 0.273 + 0.004*sl 0.289 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-480 samsung asic mx2idha/mx2ia/mx2id2a/mx2id4a 2 > 1 inverting mux with separate s and sn inputs, 0.5x/1x/2x/4x drive logic symbol cell data schematic diagram input load (sl) mx2idha mx2ia mx2id2a mx2id4a d0 d1 s sn d0 d1 s sn d0 d1 s sn d0 d1 s sn 0.5 0.5 0.5 0.5 1.0 1.0 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 gate count mx2idha mx2ia mx2id2a mx2id4a 1.67 1.67 2.67 3.00 yn d0 d1 s sn yn d0 sn d1 s truth table d0 d1 s sn yn 0 x 011 1 x 010 x 0 101 x 1 100
samsung asic 3-481 STD111 mx2idha/mx2ia/mx2id2a/mx2id4a 2 > 1 inverting mux with separate s and sn inputs, 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx2idha mx2ia path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t r 0.394 0.164 + 0.115*sl 0.149 + 0.119*sl 0.144 + 0.119*sl t f 0.254 0.116 + 0.069*sl 0.099 + 0.074*sl 0.083 + 0.075*sl t plh 0.195 0.094 + 0.051*sl 0.093 + 0.051*sl 0.092 + 0.051*sl t phl 0.147 0.075 + 0.036*sl 0.076 + 0.036*sl 0.076 + 0.036*sl d1 to yn t r 0.393 0.161 + 0.116*sl 0.151 + 0.119*sl 0.146 + 0.119*sl t f 0.301 0.161 + 0.070*sl 0.147 + 0.074*sl 0.133 + 0.075*sl t plh 0.230 0.126 + 0.052*sl 0.128 + 0.051*sl 0.130 + 0.051*sl t phl 0.189 0.115 + 0.037*sl 0.118 + 0.036*sl 0.120 + 0.036*sl s to yn t r 0.417 0.184 + 0.116*sl 0.175 + 0.119*sl 0.171 + 0.119*sl t f 0.297 0.154 + 0.071*sl 0.143 + 0.074*sl 0.134 + 0.075*sl t plh 0.245 0.142 + 0.051*sl 0.143 + 0.051*sl 0.144 + 0.051*sl t phl 0.183 0.109 + 0.037*sl 0.112 + 0.036*sl 0.114 + 0.036*sl sn to yn t r 0.418 0.188 + 0.115*sl 0.173 + 0.119*sl 0.169 + 0.119*sl t f 0.248 0.106 + 0.071*sl 0.094 + 0.074*sl 0.083 + 0.075*sl t plh 0.210 0.109 + 0.050*sl 0.107 + 0.051*sl 0.106 + 0.051*sl t phl 0.141 0.068 + 0.037*sl 0.070 + 0.036*sl 0.071 + 0.036*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t r 0.260 0.154 + 0.053*sl 0.147 + 0.055*sl 0.133 + 0.056*sl t f 0.179 0.117 + 0.031*sl 0.105 + 0.034*sl 0.090 + 0.036*sl t plh 0.137 0.090 + 0.024*sl 0.089 + 0.024*sl 0.088 + 0.024*sl t phl 0.105 0.067 + 0.019*sl 0.073 + 0.017*sl 0.073 + 0.017*sl d1 to yn t r 0.256 0.149 + 0.053*sl 0.143 + 0.055*sl 0.134 + 0.056*sl t f 0.218 0.153 + 0.032*sl 0.147 + 0.034*sl 0.133 + 0.036*sl t plh 0.164 0.114 + 0.025*sl 0.116 + 0.024*sl 0.117 + 0.024*sl t phl 0.144 0.109 + 0.018*sl 0.110 + 0.017*sl 0.111 + 0.017*sl s to yn t r 0.278 0.170 + 0.054*sl 0.165 + 0.055*sl 0.158 + 0.056*sl t f 0.212 0.145 + 0.034*sl 0.140 + 0.035*sl 0.131 + 0.036*sl t plh 0.178 0.129 + 0.024*sl 0.130 + 0.024*sl 0.131 + 0.024*sl t phl 0.138 0.101 + 0.018*sl 0.103 + 0.018*sl 0.105 + 0.017*sl sn to yn t r 0.283 0.179 + 0.052*sl 0.170 + 0.055*sl 0.156 + 0.056*sl t f 0.172 0.108 + 0.032*sl 0.097 + 0.035*sl 0.086 + 0.036*sl t plh 0.152 0.105 + 0.023*sl 0.103 + 0.024*sl 0.102 + 0.024*sl t phl 0.098 0.061 + 0.019*sl 0.066 + 0.017*sl 0.067 + 0.017*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-482 samsung asic mx2idha/mx2ia/mx2id2a/mx2id4a 2 > 1 inverting mux with separate s and sn inputs, 0.5x/1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx2id2a mx2id4a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t r 0.080 0.054 + 0.013*sl 0.053 + 0.013*sl 0.042 + 0.014*sl t f 0.070 0.045 + 0.013*sl 0.050 + 0.011*sl 0.042 + 0.012*sl t plh 0.248 0.232 + 0.008*sl 0.238 + 0.007*sl 0.244 + 0.006*sl t phl 0.213 0.195 + 0.009*sl 0.203 + 0.007*sl 0.212 + 0.006*sl d1 to yn t r 0.080 0.054 + 0.013*sl 0.052 + 0.013*sl 0.042 + 0.014*sl t f 0.072 0.049 + 0.011*sl 0.049 + 0.011*sl 0.043 + 0.012*sl t plh 0.268 0.252 + 0.008*sl 0.257 + 0.007*sl 0.263 + 0.006*sl t phl 0.251 0.234 + 0.009*sl 0.241 + 0.007*sl 0.251 + 0.006*sl s to yn t r 0.081 0.055 + 0.013*sl 0.054 + 0.013*sl 0.042 + 0.014*sl t f 0.071 0.046 + 0.012*sl 0.050 + 0.011*sl 0.043 + 0.012*sl t plh 0.288 0.272 + 0.008*sl 0.278 + 0.007*sl 0.283 + 0.006*sl t phl 0.245 0.227 + 0.009*sl 0.235 + 0.007*sl 0.244 + 0.006*sl sn to yn t r 0.079 0.053 + 0.013*sl 0.052 + 0.014*sl 0.042 + 0.014*sl t f 0.071 0.047 + 0.012*sl 0.050 + 0.011*sl 0.043 + 0.012*sl t plh 0.268 0.252 + 0.008*sl 0.258 + 0.007*sl 0.264 + 0.006*sl t phl 0.207 0.190 + 0.009*sl 0.197 + 0.007*sl 0.207 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t r 0.073 0.060 + 0.007*sl 0.060 + 0.007*sl 0.049 + 0.007*sl t f 0.067 0.055 + 0.006*sl 0.055 + 0.006*sl 0.051 + 0.006*sl t plh 0.269 0.259 + 0.005*sl 0.264 + 0.003*sl 0.275 + 0.003*sl t phl 0.229 0.218 + 0.005*sl 0.224 + 0.004*sl 0.239 + 0.003*sl d1 to yn t r 0.074 0.061 + 0.006*sl 0.061 + 0.007*sl 0.049 + 0.007*sl t f 0.066 0.052 + 0.007*sl 0.056 + 0.006*sl 0.052 + 0.006*sl t plh 0.287 0.277 + 0.005*sl 0.282 + 0.003*sl 0.293 + 0.003*sl t phl 0.266 0.255 + 0.005*sl 0.261 + 0.004*sl 0.276 + 0.003*sl s to yn t r 0.074 0.061 + 0.007*sl 0.062 + 0.007*sl 0.050 + 0.007*sl t f 0.066 0.054 + 0.006*sl 0.055 + 0.006*sl 0.052 + 0.006*sl t plh 0.307 0.297 + 0.005*sl 0.302 + 0.003*sl 0.313 + 0.003*sl t phl 0.259 0.249 + 0.005*sl 0.254 + 0.004*sl 0.269 + 0.003*sl sn to yn t r 0.075 0.062 + 0.006*sl 0.061 + 0.007*sl 0.050 + 0.007*sl t f 0.066 0.053 + 0.007*sl 0.056 + 0.006*sl 0.051 + 0.006*sl t plh 0.289 0.279 + 0.005*sl 0.284 + 0.003*sl 0.295 + 0.003*sl t phl 0.223 0.212 + 0.005*sl 0.218 + 0.004*sl 0.233 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
samsung asic 3-483 STD111 mx2ix4 4-bit 2 > 1 inverting mux logic symbol cell data input load (sl) gate count d00 d10 d01 d11 d02 d12 d03 d13 s 6.33 1.0 1.1 1.0 1.1 1.1 1.1 1.0 1.1 5.5 yn0 yn1 yn2 yn3 d00 d10 d01 d11 d02 d12 d03 d13 s truth table s yn0 yn1 yn2 yn3 0 d00 d01 d02 d03 1 d10 d11 d12 d13
STD111 3-484 samsung asic mx2ix4 4-bit 2 > 1 inverting mux switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx2ix4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d00 to yn0 t r 0.250 0.145 + 0.052*sl 0.138 + 0.054*sl 0.124 + 0.056*sl t f 0.177 0.116 + 0.031*sl 0.103 + 0.034*sl 0.088 + 0.036*sl t plh 0.135 0.088 + 0.024*sl 0.088 + 0.024*sl 0.087 + 0.024*sl t phl 0.102 0.064 + 0.019*sl 0.071 + 0.017*sl 0.071 + 0.017*sl d10 to yn0 t r 0.247 0.140 + 0.053*sl 0.135 + 0.055*sl 0.126 + 0.056*sl t f 0.232 0.169 + 0.031*sl 0.159 + 0.034*sl 0.142 + 0.036*sl t plh 0.157 0.108 + 0.025*sl 0.110 + 0.024*sl 0.112 + 0.024*sl t phl 0.140 0.104 + 0.018*sl 0.105 + 0.018*sl 0.106 + 0.017*sl s to yn0 t r 0.242 0.136 + 0.053*sl 0.129 + 0.055*sl 0.122 + 0.056*sl t f 0.194 0.127 + 0.034*sl 0.122 + 0.035*sl 0.108 + 0.036*sl t plh 0.226 0.179 + 0.024*sl 0.179 + 0.024*sl 0.177 + 0.024*sl t phl 0.178 0.141 + 0.019*sl 0.145 + 0.018*sl 0.148 + 0.017*sl d01 to yn1 t r 0.252 0.147 + 0.053*sl 0.141 + 0.054*sl 0.126 + 0.056*sl t f 0.178 0.117 + 0.031*sl 0.104 + 0.034*sl 0.089 + 0.036*sl t plh 0.136 0.089 + 0.024*sl 0.088 + 0.024*sl 0.087 + 0.024*sl t phl 0.102 0.064 + 0.019*sl 0.071 + 0.017*sl 0.071 + 0.017*sl d11 to yn1 t r 0.248 0.142 + 0.053*sl 0.136 + 0.055*sl 0.128 + 0.056*sl t f 0.234 0.172 + 0.031*sl 0.162 + 0.034*sl 0.144 + 0.035*sl t plh 0.160 0.110 + 0.025*sl 0.113 + 0.024*sl 0.114 + 0.024*sl t phl 0.140 0.105 + 0.018*sl 0.106 + 0.017*sl 0.107 + 0.017*sl s to yn1 t r 0.245 0.138 + 0.054*sl 0.132 + 0.055*sl 0.125 + 0.056*sl t f 0.195 0.128 + 0.033*sl 0.124 + 0.035*sl 0.110 + 0.036*sl t plh 0.226 0.178 + 0.024*sl 0.178 + 0.024*sl 0.177 + 0.024*sl t phl 0.178 0.141 + 0.019*sl 0.146 + 0.018*sl 0.148 + 0.017*sl d02 to yn2 t r 0.258 0.153 + 0.053*sl 0.146 + 0.054*sl 0.131 + 0.056*sl t f 0.182 0.119 + 0.031*sl 0.109 + 0.034*sl 0.093 + 0.036*sl t plh 0.138 0.091 + 0.024*sl 0.090 + 0.024*sl 0.090 + 0.024*sl t phl 0.103 0.065 + 0.019*sl 0.072 + 0.017*sl 0.072 + 0.017*sl d12 to yn2 t r 0.251 0.145 + 0.053*sl 0.139 + 0.055*sl 0.131 + 0.055*sl t f 0.236 0.174 + 0.031*sl 0.164 + 0.034*sl 0.148 + 0.035*sl t plh 0.161 0.112 + 0.025*sl 0.114 + 0.024*sl 0.116 + 0.024*sl t phl 0.142 0.106 + 0.018*sl 0.107 + 0.017*sl 0.109 + 0.017*sl s to yn2 t r 0.251 0.143 + 0.054*sl 0.138 + 0.055*sl 0.130 + 0.056*sl t f 0.197 0.131 + 0.033*sl 0.126 + 0.035*sl 0.113 + 0.036*sl t plh 0.226 0.179 + 0.024*sl 0.179 + 0.024*sl 0.177 + 0.024*sl t phl 0.179 0.142 + 0.019*sl 0.147 + 0.018*sl 0.149 + 0.017*sl d03 to yn3 t r 0.259 0.155 + 0.052*sl 0.148 + 0.054*sl 0.133 + 0.055*sl t f 0.181 0.118 + 0.031*sl 0.109 + 0.034*sl 0.094 + 0.036*sl t plh 0.139 0.092 + 0.023*sl 0.091 + 0.024*sl 0.090 + 0.024*sl t phl 0.106 0.069 + 0.019*sl 0.075 + 0.017*sl 0.075 + 0.017*sl
samsung asic 3-485 STD111 mx2ix4 4-bit 2 > 1 inverting mux switching characteristics (cont.) (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx2ix4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d13 to yn3 t r 0.257 0.151 + 0.053*sl 0.144 + 0.055*sl 0.137 + 0.056*sl t f 0.234 0.171 + 0.031*sl 0.161 + 0.034*sl 0.145 + 0.035*sl t plh 0.161 0.112 + 0.025*sl 0.114 + 0.024*sl 0.115 + 0.024*sl t phl 0.142 0.107 + 0.018*sl 0.108 + 0.017*sl 0.109 + 0.017*sl s to yn3 t r 0.251 0.144 + 0.053*sl 0.137 + 0.055*sl 0.131 + 0.056*sl t f 0.196 0.129 + 0.033*sl 0.124 + 0.035*sl 0.112 + 0.036*sl t plh 0.230 0.183 + 0.024*sl 0.183 + 0.024*sl 0.181 + 0.024*sl t phl 0.183 0.145 + 0.019*sl 0.150 + 0.018*sl 0.152 + 0.017*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-486 samsung asic mx3i/mx3id2/mx3id4 3 > 1 inverting mux with 1x/2x/4x drive logic symbol cell data schematic diagram input load (sl) mx3i mx3id2 mx3id4 d0 d1 d2 s0 s1 d0 d1 d2 s0 s1 d0 d1 d2 s0 s1 0.8 0.9 0.8 1.2 1.2 0.8 0.9 0.8 1.2 1.2 0.8 0.9 0.8 1.2 1.2 gate count mx3i mx3id2 mx3id4 4.67 4.67 5.33 d0 d1 d2 yn s0 s1 d0 d1 s0 s1 d2 yn truth table s0 s1 yn 00 d0 10 d1 x1 d2
samsung asic 3-487 STD111 mx3i/mx3id2/mx3id4 3 > 1 inverting mux with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx3i path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t r 0.110 0.059 + 0.025*sl 0.053 + 0.027*sl 0.043 + 0.028*sl t f 0.095 0.050 + 0.023*sl 0.048 + 0.023*sl 0.039 + 0.024*sl t plh 0.317 0.289 + 0.014*sl 0.295 + 0.012*sl 0.296 + 0.012*sl t phl 0.307 0.277 + 0.015*sl 0.284 + 0.013*sl 0.287 + 0.013*sl d1 to yn t r 0.110 0.059 + 0.026*sl 0.053 + 0.027*sl 0.043 + 0.028*sl t f 0.095 0.050 + 0.023*sl 0.048 + 0.023*sl 0.039 + 0.024*sl t plh 0.319 0.291 + 0.014*sl 0.297 + 0.012*sl 0.298 + 0.012*sl t phl 0.306 0.276 + 0.015*sl 0.283 + 0.013*sl 0.286 + 0.013*sl d2 to yn t r 0.103 0.050 + 0.026*sl 0.046 + 0.027*sl 0.039 + 0.028*sl t f 0.091 0.043 + 0.024*sl 0.045 + 0.023*sl 0.036 + 0.024*sl t plh 0.233 0.206 + 0.014*sl 0.210 + 0.012*sl 0.211 + 0.012*sl t phl 0.224 0.195 + 0.015*sl 0.201 + 0.013*sl 0.204 + 0.013*sl s0 to yn t r 0.110 0.059 + 0.025*sl 0.053 + 0.027*sl 0.043 + 0.028*sl t f 0.095 0.049 + 0.023*sl 0.048 + 0.023*sl 0.039 + 0.024*sl t plh 0.317 0.289 + 0.014*sl 0.294 + 0.012*sl 0.296 + 0.012*sl t phl 0.307 0.278 + 0.015*sl 0.285 + 0.013*sl 0.288 + 0.013*sl s1 to yn t r 0.107 0.056 + 0.026*sl 0.049 + 0.027*sl 0.042 + 0.028*sl t f 0.094 0.049 + 0.022*sl 0.044 + 0.024*sl 0.039 + 0.024*sl t plh 0.238 0.210 + 0.014*sl 0.215 + 0.012*sl 0.217 + 0.012*sl t phl 0.249 0.220 + 0.015*sl 0.227 + 0.013*sl 0.230 + 0.013*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-488 samsung asic mx3i/mx3id2/mx3id4 3 > 1 inverting mux with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx3id2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t r 0.089 0.064 + 0.013*sl 0.063 + 0.013*sl 0.049 + 0.014*sl t f 0.077 0.052 + 0.012*sl 0.056 + 0.011*sl 0.048 + 0.012*sl t plh 0.333 0.317 + 0.008*sl 0.323 + 0.007*sl 0.330 + 0.006*sl t phl 0.322 0.304 + 0.009*sl 0.311 + 0.007*sl 0.322 + 0.006*sl d1 to yn t r 0.090 0.064 + 0.013*sl 0.063 + 0.013*sl 0.049 + 0.014*sl t f 0.076 0.051 + 0.013*sl 0.056 + 0.011*sl 0.048 + 0.012*sl t plh 0.335 0.319 + 0.008*sl 0.325 + 0.007*sl 0.332 + 0.006*sl t phl 0.320 0.302 + 0.009*sl 0.310 + 0.007*sl 0.320 + 0.006*sl d2 to yn t r 0.081 0.055 + 0.013*sl 0.054 + 0.013*sl 0.043 + 0.014*sl t f 0.072 0.047 + 0.013*sl 0.052 + 0.011*sl 0.044 + 0.012*sl t plh 0.245 0.229 + 0.008*sl 0.234 + 0.007*sl 0.240 + 0.006*sl t phl 0.235 0.217 + 0.009*sl 0.224 + 0.007*sl 0.234 + 0.006*sl s0 to yn t r 0.089 0.063 + 0.013*sl 0.064 + 0.013*sl 0.049 + 0.014*sl t f 0.077 0.052 + 0.013*sl 0.056 + 0.011*sl 0.048 + 0.012*sl t plh 0.333 0.317 + 0.008*sl 0.323 + 0.007*sl 0.330 + 0.006*sl t phl 0.322 0.304 + 0.009*sl 0.312 + 0.007*sl 0.322 + 0.006*sl s1 to yn t r 0.086 0.060 + 0.013*sl 0.059 + 0.013*sl 0.047 + 0.014*sl t f 0.076 0.051 + 0.012*sl 0.055 + 0.011*sl 0.047 + 0.012*sl t plh 0.254 0.238 + 0.008*sl 0.244 + 0.007*sl 0.250 + 0.006*sl t phl 0.263 0.245 + 0.009*sl 0.253 + 0.007*sl 0.263 + 0.006*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-489 STD111 mx3i/mx3id2/mx3id4 3 > 1 inverting mux with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx3id4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t r 0.086 0.073 + 0.007*sl 0.073 + 0.006*sl 0.059 + 0.007*sl t f 0.074 0.062 + 0.006*sl 0.063 + 0.006*sl 0.059 + 0.006*sl t plh 0.365 0.355 + 0.005*sl 0.360 + 0.004*sl 0.373 + 0.003*sl t phl 0.346 0.336 + 0.005*sl 0.341 + 0.004*sl 0.357 + 0.003*sl d1 to yn t r 0.086 0.073 + 0.007*sl 0.074 + 0.006*sl 0.059 + 0.007*sl t f 0.074 0.062 + 0.006*sl 0.063 + 0.006*sl 0.059 + 0.006*sl t plh 0.367 0.357 + 0.005*sl 0.362 + 0.004*sl 0.375 + 0.003*sl t phl 0.345 0.334 + 0.005*sl 0.339 + 0.004*sl 0.356 + 0.003*sl d2 to yn t r 0.076 0.062 + 0.007*sl 0.063 + 0.007*sl 0.051 + 0.007*sl t f 0.067 0.053 + 0.007*sl 0.058 + 0.006*sl 0.052 + 0.006*sl t plh 0.269 0.259 + 0.005*sl 0.264 + 0.003*sl 0.275 + 0.003*sl t phl 0.253 0.242 + 0.005*sl 0.248 + 0.004*sl 0.263 + 0.003*sl s0 to yn t r 0.087 0.075 + 0.006*sl 0.073 + 0.006*sl 0.059 + 0.007*sl t f 0.073 0.060 + 0.007*sl 0.063 + 0.006*sl 0.057 + 0.006*sl t plh 0.364 0.354 + 0.005*sl 0.360 + 0.004*sl 0.372 + 0.003*sl t phl 0.346 0.335 + 0.005*sl 0.341 + 0.004*sl 0.357 + 0.003*sl s1 to yn t r 0.084 0.072 + 0.006*sl 0.071 + 0.006*sl 0.058 + 0.007*sl t f 0.073 0.061 + 0.006*sl 0.061 + 0.006*sl 0.058 + 0.006*sl t plh 0.286 0.276 + 0.005*sl 0.281 + 0.004*sl 0.293 + 0.003*sl t phl 0.287 0.277 + 0.005*sl 0.283 + 0.004*sl 0.298 + 0.003*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-490 samsung asic mx4/mx4d2/mx4d4 4 > 1 non-inverting mux with 1x/2x/4x drive logic symbol cell data schematic diagram input load (sl) mx4 mx4d2 mx4d4 d0 d1 d2 d3 s0 s1 d0 d1 d2 d3 s0 s1 d0 d1 d2 d3 s0 s1 0.8 0.9 0.8 0.8 1.9 1.2 0.8 0.8 0.8 0.8 1.9 1.2 0.8 0.8 0.8 0.8 1.9 1.2 gate count mx4 mx4 d2 mx4 d4 5.33 5.33 6.00 y d0 d1 d2 d3 s0 s1 s0b s0 s0 s1b s1 s1 d0 d1 d2 d3 y s0 s0 s0b s0 s0b s1 s1b s1b s1 truth table s0 s1 y 00d0 10d1 01d2 11d3
samsung asic 3-491 STD111 mx4/mx4d2/mx4d4 4 > 1 non-inverting mux with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t r 0.146 0.091 + 0.027*sl 0.093 + 0.027*sl 0.088 + 0.028*sl t f 0.154 0.102 + 0.026*sl 0.110 + 0.024*sl 0.116 + 0.023*sl t plh 0.263 0.228 + 0.018*sl 0.240 + 0.014*sl 0.255 + 0.013*sl t phl 0.270 0.228 + 0.021*sl 0.246 + 0.016*sl 0.269 + 0.014*sl d1 to y t r 0.146 0.091 + 0.027*sl 0.092 + 0.027*sl 0.087 + 0.028*sl t f 0.154 0.102 + 0.026*sl 0.111 + 0.024*sl 0.116 + 0.023*sl t plh 0.264 0.229 + 0.018*sl 0.241 + 0.014*sl 0.256 + 0.013*sl t phl 0.273 0.230 + 0.021*sl 0.248 + 0.016*sl 0.271 + 0.014*sl d2 to y t r 0.145 0.090 + 0.028*sl 0.092 + 0.027*sl 0.086 + 0.028*sl t f 0.153 0.102 + 0.026*sl 0.108 + 0.024*sl 0.114 + 0.023*sl t plh 0.260 0.225 + 0.018*sl 0.238 + 0.014*sl 0.252 + 0.013*sl t phl 0.269 0.227 + 0.021*sl 0.244 + 0.016*sl 0.267 + 0.014*sl d3 to y t r 0.144 0.089 + 0.028*sl 0.092 + 0.027*sl 0.086 + 0.028*sl t f 0.154 0.102 + 0.026*sl 0.109 + 0.024*sl 0.115 + 0.023*sl t plh 0.258 0.222 + 0.018*sl 0.235 + 0.014*sl 0.250 + 0.013*sl t phl 0.270 0.228 + 0.021*sl 0.246 + 0.016*sl 0.268 + 0.014*sl s0 to y t r 0.146 0.090 + 0.028*sl 0.093 + 0.027*sl 0.089 + 0.028*sl t f 0.154 0.103 + 0.026*sl 0.110 + 0.024*sl 0.115 + 0.023*sl t plh 0.273 0.237 + 0.018*sl 0.250 + 0.014*sl 0.265 + 0.013*sl t phl 0.285 0.242 + 0.021*sl 0.260 + 0.016*sl 0.283 + 0.014*sl s1 to y t r 0.135 0.076 + 0.029*sl 0.083 + 0.027*sl 0.080 + 0.028*sl t f 0.137 0.083 + 0.027*sl 0.093 + 0.025*sl 0.102 + 0.024*sl t plh 0.199 0.164 + 0.018*sl 0.176 + 0.014*sl 0.191 + 0.013*sl t phl 0.213 0.171 + 0.021*sl 0.188 + 0.016*sl 0.210 + 0.014*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-492 samsung asic mx4/mx4d2/mx4d4 4 > 1 non-inverting mux with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t r 0.135 0.108 + 0.013*sl 0.107 + 0.014*sl 0.109 + 0.014*sl t f 0.151 0.121 + 0.015*sl 0.130 + 0.012*sl 0.141 + 0.012*sl t plh 0.281 0.257 + 0.012*sl 0.271 + 0.008*sl 0.295 + 0.007*sl t phl 0.290 0.262 + 0.014*sl 0.277 + 0.010*sl 0.311 + 0.008*sl d1 to y t r 0.134 0.108 + 0.013*sl 0.107 + 0.014*sl 0.109 + 0.014*sl t f 0.150 0.120 + 0.015*sl 0.130 + 0.013*sl 0.142 + 0.012*sl t plh 0.280 0.257 + 0.012*sl 0.270 + 0.008*sl 0.294 + 0.007*sl t phl 0.291 0.263 + 0.014*sl 0.278 + 0.010*sl 0.312 + 0.008*sl d2 to y t r 0.133 0.107 + 0.013*sl 0.105 + 0.014*sl 0.107 + 0.014*sl t f 0.150 0.121 + 0.015*sl 0.129 + 0.013*sl 0.141 + 0.012*sl t plh 0.276 0.253 + 0.012*sl 0.266 + 0.008*sl 0.290 + 0.007*sl t phl 0.287 0.260 + 0.014*sl 0.275 + 0.010*sl 0.308 + 0.008*sl d3 to y t r 0.134 0.107 + 0.013*sl 0.105 + 0.014*sl 0.107 + 0.014*sl t f 0.150 0.121 + 0.015*sl 0.130 + 0.012*sl 0.141 + 0.012*sl t plh 0.278 0.255 + 0.012*sl 0.268 + 0.008*sl 0.292 + 0.007*sl t phl 0.291 0.263 + 0.014*sl 0.278 + 0.010*sl 0.312 + 0.008*sl s0 to y t r 0.134 0.106 + 0.014*sl 0.108 + 0.014*sl 0.110 + 0.014*sl t f 0.151 0.121 + 0.015*sl 0.129 + 0.013*sl 0.142 + 0.012*sl t plh 0.287 0.264 + 0.012*sl 0.277 + 0.008*sl 0.301 + 0.007*sl t phl 0.301 0.273 + 0.014*sl 0.289 + 0.010*sl 0.323 + 0.008*sl s1 to y t r 0.127 0.098 + 0.014*sl 0.099 + 0.014*sl 0.104 + 0.014*sl t f 0.141 0.111 + 0.015*sl 0.120 + 0.013*sl 0.133 + 0.012*sl t plh 0.213 0.189 + 0.012*sl 0.202 + 0.008*sl 0.226 + 0.007*sl t phl 0.231 0.203 + 0.014*sl 0.218 + 0.010*sl 0.252 + 0.008*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
samsung asic 3-493 STD111 mx4/mx4d2/mx4d4 4 > 1 non-inverting mux with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx4d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t r 0.169 0.156 + 0.006*sl 0.155 + 0.007*sl 0.154 + 0.007*sl t f 0.191 0.176 + 0.007*sl 0.179 + 0.007*sl 0.199 + 0.006*sl t plh 0.345 0.330 + 0.008*sl 0.340 + 0.005*sl 0.376 + 0.004*sl t phl 0.358 0.341 + 0.009*sl 0.352 + 0.006*sl 0.397 + 0.004*sl d1 to y t r 0.169 0.156 + 0.006*sl 0.155 + 0.007*sl 0.155 + 0.007*sl t f 0.192 0.176 + 0.008*sl 0.181 + 0.007*sl 0.200 + 0.006*sl t plh 0.344 0.329 + 0.008*sl 0.339 + 0.005*sl 0.375 + 0.004*sl t phl 0.359 0.342 + 0.009*sl 0.352 + 0.006*sl 0.398 + 0.004*sl d2 to y t r 0.167 0.154 + 0.007*sl 0.153 + 0.007*sl 0.154 + 0.007*sl t f 0.191 0.176 + 0.007*sl 0.180 + 0.007*sl 0.199 + 0.006*sl t plh 0.341 0.326 + 0.008*sl 0.336 + 0.005*sl 0.371 + 0.004*sl t phl 0.356 0.339 + 0.009*sl 0.350 + 0.006*sl 0.394 + 0.004*sl d3 to y t r 0.168 0.156 + 0.006*sl 0.154 + 0.007*sl 0.153 + 0.007*sl t f 0.191 0.176 + 0.008*sl 0.179 + 0.007*sl 0.199 + 0.006*sl t plh 0.342 0.327 + 0.008*sl 0.337 + 0.005*sl 0.372 + 0.004*sl t phl 0.359 0.342 + 0.009*sl 0.353 + 0.006*sl 0.398 + 0.004*sl s0 to y t r 0.169 0.156 + 0.006*sl 0.155 + 0.007*sl 0.155 + 0.007*sl t f 0.192 0.176 + 0.008*sl 0.181 + 0.007*sl 0.200 + 0.006*sl t plh 0.350 0.335 + 0.008*sl 0.345 + 0.005*sl 0.381 + 0.004*sl t phl 0.369 0.352 + 0.009*sl 0.362 + 0.006*sl 0.407 + 0.004*sl s1 to y t r 0.167 0.154 + 0.006*sl 0.153 + 0.007*sl 0.152 + 0.007*sl t f 0.188 0.174 + 0.007*sl 0.177 + 0.007*sl 0.196 + 0.006*sl t plh 0.273 0.257 + 0.008*sl 0.267 + 0.005*sl 0.303 + 0.004*sl t phl 0.298 0.281 + 0.009*sl 0.291 + 0.006*sl 0.337 + 0.004*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
STD111 3-494 samsung asic mx8/mx8d2/mx8d4 8 > 1 non-inverting mux with 1x/2x/4x drive logic symbol cell data input load (sl) gate count mx8 mx8 d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 0.7 0.7 0.8 0.7 0.7 0.8 0.7 0.8 1.0 1.8 1.2 10.00 mx8d2 mx8d2 d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 0.7 0.7 0.7 0.7 0.7 0.8 0.7 0.8 1.0 1.8 1.2 10.33 mx8d4 mx8d4 d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 0.7 0.7 0.8 0.7 0.7 0.8 0.7 0.8 1.0 1.8 1.2 11.00 y d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 truth table s0 s1 s2 y 000d0 100d1 010d2 110d3 001d4 101d5 011d6 111d7
samsung asic 3-495 STD111 mx8/mx8d2/mx8d4 8 > 1 non-inverting mux with 1x/2x/4x drive schematic diagram d0 d1 d2 d3 s0 s0b s0 s0b s0 s0 s0b s1b s1 s1 s0 s1b s1 s1 s1b s2b s2 y d4 d5 d6 d7 s0 s0b s0 s0b s1b s1 s1 s1b s2 s2b s2b s2 s2
STD111 3-496 samsung asic mx8/mx8d2/mx8d4 8 > 1 non-inverting mux with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t r 0.187 0.131 + 0.028*sl 0.133 + 0.027*sl 0.136 + 0.027*sl t f 0.216 0.161 + 0.027*sl 0.172 + 0.024*sl 0.184 + 0.023*sl t plh 0.391 0.350 + 0.021*sl 0.368 + 0.016*sl 0.389 + 0.014*sl t phl 0.417 0.367 + 0.025*sl 0.390 + 0.019*sl 0.422 + 0.015*sl d1 to y t r 0.186 0.131 + 0.028*sl 0.133 + 0.027*sl 0.136 + 0.027*sl t f 0.216 0.161 + 0.027*sl 0.172 + 0.024*sl 0.184 + 0.023*sl t plh 0.391 0.350 + 0.021*sl 0.368 + 0.016*sl 0.389 + 0.014*sl t phl 0.417 0.367 + 0.025*sl 0.391 + 0.019*sl 0.423 + 0.015*sl d2 to y t r 0.187 0.132 + 0.027*sl 0.134 + 0.027*sl 0.136 + 0.027*sl t f 0.217 0.162 + 0.027*sl 0.174 + 0.024*sl 0.185 + 0.023*sl t plh 0.393 0.351 + 0.021*sl 0.369 + 0.016*sl 0.391 + 0.014*sl t phl 0.420 0.370 + 0.025*sl 0.394 + 0.019*sl 0.426 + 0.015*sl d3 to y t r 0.187 0.132 + 0.027*sl 0.134 + 0.027*sl 0.136 + 0.027*sl t f 0.217 0.162 + 0.027*sl 0.174 + 0.024*sl 0.185 + 0.023*sl t plh 0.393 0.351 + 0.021*sl 0.370 + 0.016*sl 0.391 + 0.014*sl t phl 0.420 0.370 + 0.025*sl 0.394 + 0.019*sl 0.426 + 0.015*sl d4 to y t r 0.187 0.132 + 0.028*sl 0.134 + 0.027*sl 0.136 + 0.027*sl t f 0.216 0.161 + 0.027*sl 0.172 + 0.024*sl 0.184 + 0.023*sl t plh 0.390 0.349 + 0.021*sl 0.367 + 0.016*sl 0.388 + 0.014*sl t phl 0.417 0.367 + 0.025*sl 0.391 + 0.019*sl 0.422 + 0.015*sl d5 to y t r 0.187 0.132 + 0.028*sl 0.134 + 0.027*sl 0.136 + 0.027*sl t f 0.216 0.161 + 0.027*sl 0.172 + 0.024*sl 0.184 + 0.023*sl t plh 0.390 0.349 + 0.021*sl 0.367 + 0.016*sl 0.388 + 0.014*sl t phl 0.417 0.367 + 0.025*sl 0.391 + 0.019*sl 0.423 + 0.015*sl d6 to y t r 0.187 0.133 + 0.027*sl 0.134 + 0.027*sl 0.137 + 0.027*sl t f 0.217 0.162 + 0.028*sl 0.174 + 0.024*sl 0.186 + 0.023*sl t plh 0.392 0.351 + 0.021*sl 0.369 + 0.016*sl 0.391 + 0.014*sl t phl 0.421 0.371 + 0.025*sl 0.395 + 0.019*sl 0.427 + 0.015*sl d7 to y t r 0.187 0.133 + 0.027*sl 0.134 + 0.027*sl 0.137 + 0.027*sl t f 0.217 0.162 + 0.028*sl 0.174 + 0.024*sl 0.186 + 0.023*sl t plh 0.393 0.351 + 0.021*sl 0.370 + 0.016*sl 0.391 + 0.014*sl t phl 0.421 0.371 + 0.025*sl 0.395 + 0.019*sl 0.427 + 0.015*sl s0 to y t r 0.188 0.133 + 0.028*sl 0.135 + 0.027*sl 0.138 + 0.027*sl t f 0.217 0.161 + 0.028*sl 0.175 + 0.024*sl 0.185 + 0.023*sl t plh 0.556 0.514 + 0.021*sl 0.533 + 0.016*sl 0.554 + 0.014*sl t phl 0.578 0.528 + 0.025*sl 0.552 + 0.019*sl 0.584 + 0.015*sl s1 to y t r 0.180 0.124 + 0.028*sl 0.127 + 0.027*sl 0.130 + 0.027*sl t f 0.203 0.147 + 0.028*sl 0.160 + 0.025*sl 0.173 + 0.023*sl t plh 0.310 0.269 + 0.021*sl 0.287 + 0.016*sl 0.308 + 0.014*sl t phl 0.327 0.277 + 0.025*sl 0.301 + 0.019*sl 0.333 + 0.015*sl
samsung asic 3-497 STD111 mx8/mx8d2/mx8d4 8 > 1 non-inverting mux with 1x/2x/4x drive switching characteristics (cont.) (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s2 to y t r 0.157 0.097 + 0.030*sl 0.103 + 0.028*sl 0.110 + 0.027*sl t f 0.163 0.102 + 0.030*sl 0.117 + 0.026*sl 0.138 + 0.024*sl t plh 0.219 0.179 + 0.020*sl 0.195 + 0.016*sl 0.215 + 0.014*sl t phl 0.234 0.186 + 0.024*sl 0.207 + 0.018*sl 0.235 + 0.015*sl *group1 : sl < 4, *group2 : 4 sl < < = = 10, *group3 : 10 < sl
STD111 3-498 samsung asic mx8/mx8d2/mx8d4 8 > 1 non-inverting mux with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t r 0.180 0.151 + 0.014*sl 0.153 + 0.014*sl 0.157 + 0.013*sl t f 0.215 0.183 + 0.016*sl 0.196 + 0.013*sl 0.214 + 0.012*sl t plh 0.417 0.390 + 0.014*sl 0.406 + 0.009*sl 0.439 + 0.007*sl t phl 0.443 0.411 + 0.016*sl 0.429 + 0.011*sl 0.475 + 0.008*sl d1 to y t r 0.180 0.152 + 0.014*sl 0.153 + 0.014*sl 0.157 + 0.013*sl t f 0.215 0.183 + 0.016*sl 0.196 + 0.013*sl 0.214 + 0.012*sl t plh 0.417 0.390 + 0.014*sl 0.407 + 0.009*sl 0.439 + 0.007*sl t phl 0.443 0.411 + 0.016*sl 0.430 + 0.011*sl 0.475 + 0.008*sl d2 to y t r 0.180 0.152 + 0.014*sl 0.153 + 0.014*sl 0.158 + 0.013*sl t f 0.216 0.183 + 0.017*sl 0.197 + 0.013*sl 0.215 + 0.012*sl t plh 0.419 0.391 + 0.014*sl 0.408 + 0.009*sl 0.440 + 0.007*sl t phl 0.447 0.415 + 0.016*sl 0.433 + 0.011*sl 0.478 + 0.008*sl d3 to y t r 0.180 0.152 + 0.014*sl 0.153 + 0.014*sl 0.158 + 0.013*sl t f 0.216 0.183 + 0.017*sl 0.197 + 0.013*sl 0.215 + 0.012*sl t plh 0.419 0.391 + 0.014*sl 0.408 + 0.009*sl 0.440 + 0.007*sl t phl 0.447 0.415 + 0.016*sl 0.433 + 0.011*sl 0.478 + 0.008*sl d4 to y t r 0.180 0.151 + 0.014*sl 0.153 + 0.014*sl 0.157 + 0.013*sl t f 0.215 0.183 + 0.016*sl 0.196 + 0.013*sl 0.213 + 0.012*sl t plh 0.416 0.389 + 0.014*sl 0.405 + 0.009*sl 0.438 + 0.007*sl t phl 0.443 0.411 + 0.016*sl 0.430 + 0.011*sl 0.475 + 0.008*sl d5 to y t r 0.180 0.151 + 0.014*sl 0.153 + 0.014*sl 0.157 + 0.013*sl t f 0.215 0.183 + 0.016*sl 0.196 + 0.013*sl 0.213 + 0.012*sl t plh 0.416 0.389 + 0.014*sl 0.405 + 0.009*sl 0.438 + 0.007*sl t phl 0.443 0.412 + 0.016*sl 0.430 + 0.011*sl 0.475 + 0.008*sl d6 to y t r 0.181 0.152 + 0.014*sl 0.154 + 0.014*sl 0.158 + 0.013*sl t f 0.217 0.183 + 0.017*sl 0.198 + 0.013*sl 0.215 + 0.012*sl t plh 0.418 0.391 + 0.014*sl 0.408 + 0.009*sl 0.440 + 0.007*sl t phl 0.447 0.415 + 0.016*sl 0.434 + 0.011*sl 0.479 + 0.008*sl d7 to y t r 0.181 0.152 + 0.014*sl 0.154 + 0.014*sl 0.158 + 0.013*sl t f 0.216 0.183 + 0.017*sl 0.198 + 0.013*sl 0.215 + 0.012*sl t plh 0.419 0.391 + 0.014*sl 0.408 + 0.009*sl 0.440 + 0.007*sl t phl 0.447 0.416 + 0.016*sl 0.434 + 0.011*sl 0.479 + 0.008*sl s0 to y t r 0.181 0.152 + 0.014*sl 0.154 + 0.014*sl 0.158 + 0.013*sl t f 0.216 0.183 + 0.017*sl 0.198 + 0.013*sl 0.214 + 0.012*sl t plh 0.582 0.554 + 0.014*sl 0.571 + 0.009*sl 0.603 + 0.007*sl t phl 0.604 0.572 + 0.016*sl 0.590 + 0.011*sl 0.636 + 0.008*sl s1 to y t r 0.175 0.146 + 0.014*sl 0.149 + 0.014*sl 0.152 + 0.014*sl t f 0.207 0.174 + 0.016*sl 0.187 + 0.013*sl 0.206 + 0.012*sl t plh 0.334 0.307 + 0.014*sl 0.323 + 0.009*sl 0.356 + 0.007*sl t phl 0.351 0.319 + 0.016*sl 0.337 + 0.011*sl 0.383 + 0.008*sl
samsung asic 3-499 STD111 mx8/mx8d2/mx8d4 8 > 1 non-inverting mux with 1x/2x/4x drive switching characteristics (cont.) (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s2 to y t r 0.158 0.128 + 0.015*sl 0.131 + 0.014*sl 0.138 + 0.014*sl t f 0.172 0.136 + 0.018*sl 0.152 + 0.014*sl 0.176 + 0.012*sl t plh 0.239 0.212 + 0.014*sl 0.228 + 0.009*sl 0.260 + 0.007*sl t phl 0.250 0.218 + 0.016*sl 0.236 + 0.011*sl 0.281 + 0.008*sl *group1 : sl < 4, *group2 : 4 sl < < = = 16, *group3 : 16 < sl
STD111 3-500 samsung asic mx8/mx8d2/mx8d4 8 > 1 non-inverting mux with 1x/2x/4x drive switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx8d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t r 0.228 0.217 + 0.005*sl 0.211 + 0.007*sl 0.213 + 0.007*sl t f 0.276 0.261 + 0.007*sl 0.262 + 0.007*sl 0.291 + 0.006*sl t plh 0.504 0.486 + 0.009*sl 0.499 + 0.006*sl 0.544 + 0.004*sl t phl 0.547 0.527 + 0.010*sl 0.539 + 0.007*sl 0.594 + 0.005*sl d1 to y t r 0.227 0.216 + 0.005*sl 0.211 + 0.007*sl 0.213 + 0.007*sl t f 0.276 0.261 + 0.007*sl 0.262 + 0.007*sl 0.291 + 0.006*sl t plh 0.504 0.486 + 0.009*sl 0.498 + 0.006*sl 0.544 + 0.004*sl t phl 0.547 0.527 + 0.010*sl 0.539 + 0.007*sl 0.594 + 0.005*sl d2 to y t r 0.227 0.216 + 0.006*sl 0.211 + 0.007*sl 0.214 + 0.007*sl t f 0.276 0.261 + 0.007*sl 0.262 + 0.007*sl 0.292 + 0.006*sl t plh 0.503 0.485 + 0.009*sl 0.497 + 0.006*sl 0.543 + 0.004*sl t phl 0.548 0.528 + 0.010*sl 0.540 + 0.007*sl 0.595 + 0.005*sl d3 to y t r 0.227 0.216 + 0.006*sl 0.211 + 0.007*sl 0.213 + 0.007*sl t f 0.276 0.261 + 0.007*sl 0.262 + 0.007*sl 0.292 + 0.006*sl t plh 0.503 0.485 + 0.009*sl 0.497 + 0.006*sl 0.543 + 0.004*sl t phl 0.548 0.528 + 0.010*sl 0.540 + 0.007*sl 0.595 + 0.005*sl d4 to y t r 0.227 0.216 + 0.006*sl 0.211 + 0.007*sl 0.213 + 0.007*sl t f 0.274 0.259 + 0.007*sl 0.260 + 0.007*sl 0.290 + 0.006*sl t plh 0.499 0.481 + 0.009*sl 0.494 + 0.006*sl 0.539 + 0.004*sl t phl 0.543 0.524 + 0.010*sl 0.536 + 0.007*sl 0.590 + 0.005*sl d5 to y t r 0.227 0.216 + 0.006*sl 0.211 + 0.007*sl 0.213 + 0.007*sl t f 0.274 0.259 + 0.007*sl 0.260 + 0.007*sl 0.290 + 0.006*sl t plh 0.499 0.482 + 0.009*sl 0.494 + 0.006*sl 0.540 + 0.004*sl t phl 0.543 0.524 + 0.010*sl 0.536 + 0.007*sl 0.591 + 0.005*sl d6 to y t r 0.227 0.216 + 0.006*sl 0.211 + 0.007*sl 0.214 + 0.007*sl t f 0.275 0.261 + 0.007*sl 0.262 + 0.007*sl 0.291 + 0.006*sl t plh 0.502 0.484 + 0.009*sl 0.496 + 0.006*sl 0.542 + 0.004*sl t phl 0.547 0.528 + 0.010*sl 0.540 + 0.007*sl 0.595 + 0.005*sl d7 to y t r 0.227 0.216 + 0.006*sl 0.211 + 0.007*sl 0.214 + 0.007*sl t f 0.276 0.261 + 0.007*sl 0.262 + 0.007*sl 0.291 + 0.006*sl t plh 0.502 0.484 + 0.009*sl 0.496 + 0.006*sl 0.542 + 0.004*sl t phl 0.548 0.528 + 0.010*sl 0.540 + 0.007*sl 0.595 + 0.005*sl s0 to y t r 0.228 0.217 + 0.006*sl 0.212 + 0.007*sl 0.214 + 0.007*sl t f 0.275 0.261 + 0.007*sl 0.261 + 0.007*sl 0.292 + 0.006*sl t plh 0.666 0.648 + 0.009*sl 0.660 + 0.006*sl 0.706 + 0.004*sl t phl 0.705 0.685 + 0.010*sl 0.698 + 0.007*sl 0.753 + 0.005*sl s1 to y t r 0.225 0.214 + 0.006*sl 0.209 + 0.007*sl 0.211 + 0.007*sl t f 0.272 0.257 + 0.007*sl 0.258 + 0.007*sl 0.288 + 0.006*sl t plh 0.415 0.398 + 0.009*sl 0.410 + 0.006*sl 0.455 + 0.004*sl t phl 0.450 0.430 + 0.010*sl 0.442 + 0.007*sl 0.497 + 0.005*sl
samsung asic 3-501 STD111 mx8/mx8d2/mx8d4 8 > 1 non-inverting mux with 1x/2x/4x drive switching characteristics (cont.) (typical process, 25 c, 2.5v, t r /t f = 0.20ns, sl: standard load) mx8d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s2 to y t r 0.220 0.209 + 0.005*sl 0.203 + 0.007*sl 0.205 + 0.007*sl t f 0.254 0.239 + 0.007*sl 0.240 + 0.007*sl 0.270 + 0.006*sl t plh 0.318 0.300 + 0.009*sl 0.312 + 0.006*sl 0.358 + 0.004*sl t phl 0.342 0.323 + 0.010*sl 0.335 + 0.007*sl 0.391 + 0.005*sl *group1 : sl < 4, *group2 : 4 sl < < = = 27, *group3 : 27 < sl
4 input/output cells
contents overview....................................................................................................................... ........4-1 summary tables ................................................................................................................. ..4-2 input buffers .................................................................................................................. .......4-7 output buffers................................................................................................................. ......4-19 bi-directional buffers ......................................................................................................... ...4-58 input clock drivers ............................................................................................................ ...4-60 oscillators .................................................................................................................... .........4-69 pci buffers .................................................................................................................... .......4-87 usb (universal serial bus) i/o buffers ................................................................................4-92 power pads..................................................................................................................... ......4-103 analog interface............................................................................................................... .....4-104 slot cells ..................................................................................................................... .........4-111
input/output cells overview samsung asic 4-1 STD111 overview the fourth chapter describes various kinds of input/output cells only (2.5v/ 3.3v/ 5v-tolerant) in STD111 library. the switching characteristics of each cell are attached to its basic cell information. the ac characteristics of bi-directional buffers are not included in this data sheet. however, they can be derived from different combinations of input and output buffers. there are so many possible combinations of input/output cells, therefore, the naming conventions are adopted to help you memorize and use this cell library ef?iently. you can refer to the naming conventions contained in ?ummary tables?section. the ?ummary tables?section shows the list of 2.5v, 3.3v and 5v-tolerant i/o cells separated by the category (input, output, bi-directional, etc.), and the more detailed description tables can be found on the leading part of each category. all 2.5v, 3.3v-interface and 5v-tolerant buffers use 1 i/o slot. the default pitch of a regular i/o buffer is 52 m (in case of no limitation of bonding equipments). all 2.5v, 3.3v-interface and 5v-tolerant buffers use this regular i/o slot if the data sheet do not state differently. note: when both a and b driving signals do not exist, sec tolerant ios pad voltage goes high state. however, those 5v tolerant input and bi-directional cells with 100k ? pull-up resistor have nmos pass transistor like figure 4.1. therefore, pad voltage of 5v tolerant io for 3.3v interface could be 1.7v instead of vdd. figure 4-1. y po pi vdd pa d b a tn en a
summary tables input/output cells STD111 4-2 samsung asic summary tables input buffers output buffers cell type cell name page cmos level pic/picd/picu 4-8 phic/phicd/phicu ptic/pticd/pticu cmos schmitt trigger level pis/pisd/pisu 4-12 phis/phisd/phisu ptis/ptisd/ptisu lvttl level phit/phitd/phitu 4-16 ptit/ptitd/ptitu pvlab va b none normal operation c cmos level none no resistor h 3.3v interface s schmitt trigger level d pull-down resistor t 5v-tolerant t lvttl level u pull-up resistor cell type cell name current drive (ma) page normal poby 1/2/4/6/8/10/12 4-20 pobysm 4/6/8/10/12 pobysh 10/12 phoby 1/2/4/6/8/10/12 phobysm 4/6/8/10/12 phobysh 10/12 open drain pody 1/2/4/6/8/10/12 4-29 podysm 4/6/8/10/12 podysh 10/12 phody 1/2/4/6/8/10/12 phodysm 4/6/8/10/12 phodysh 10/12 ptody 1/2/3
input/output cells summary tables samsung asic 4-3 STD111 tri-state poty 1/2/4/6/8/10/12 4-39 potysm 4/6/8/10/12 potysh 10/12 photy 1/2/4/6/8/10/12 photysm 4/6/8/10/12 photysh 10/12 ptoty 1/2/3 p wo x y z wy none normal operation 1 1ma drive h 3.3v interface 2 2ma drive x 4 4ma drive b normal buffer 6 6ma drive d open drain buffer 8 8ma drive t tri-state buffer 10 10ma drive z 12 12ma drive none no slew-rate control sm medium slew-rate control sh high slew-rate control p t o x y xy d open drain buffer 1 1ma drive t tri-state buffer 2 2ma drive 3 3ma drive cell type cell name current drive (ma) page
summary tables input/output cells STD111 4-4 samsung asic bi-directional buffers cell type cell name page open drain pbadyz/pbaudyz 4-59 phbadyz/phbaudyz ptbadyz/ptbaudyz tri-state pbatyz/pbadtyz/pbautyz phbaty/phbadty/phbauty ptbaty/ptbadty/ptbauty pw b a b x y z wy none normal 1 1ma drive h 3.3v interface 2 2ma drive a 4 4ma drive c lvcmos level 6 6ma drive s lvcmos schmitt trigger level 8 8ma drive t lvttl level 10 10ma drive b 12 12ma drive none no resistor z d pull-down resistor none no slew-rate control u pull-up resistor sm medium slew -rate control x sh high slew-rate control b normal buffer d open drain buffer t tri-state buffer p t b a b x y ax c lvcmos level d open drain buffer s lvcmos schmitt trigger level t tri-state buffer t lvttl level y b 1 1ma drive none no resistor 2 2ma drive d pull-down resistor 3 3ma drive u pull-up resistor
input/output cells summary tables samsung asic 4-5 STD111 input clock drivers with pad oscillators pci buffers usb (universal serial bus) i/o buffers (under development) cell type cell name current drive (ma) page lvcmos level psckdcaby 2/4/6/8 4-61 lvcmos schmitt trigger level psckdsaby 2/4/6/8 4-65 psckd a b y ay c lvcmos level 2 2ma drive s lvcmos schmitt trigger level 4 4ma drive b 6 6ma drive none no resistor 8 8ma drive d pull-down resistor u pull-up resistor cell type cell name page oscillator phsosck1/k2/m1/m2/m3 4-70 phsosck17/k27/m16/m26/m36 4-76 psosck1/k2/m1/m2 4-82 cell type cell name page 5v-tolerant pci input ptipci 4-89 5v-tolerant pci input ptopci 4-90 5v-tolerant pci bi-directional ptbpci 4-91 cell type cell name page bidirectional usb buffer pbusb/pbusb1 4-94 pbusb_ls 4-95 pbusb_fs 4-96
summary tables input/output cells STD111 4-6 samsung asic power pads analog interface slot cells cell type cell name page 2.5v vdd vdd2(i/p/o/ip/op/t) 4-103 3.3v vdd vdd3(p/o/op) vss vss2(i/p/o/ip/op/t) vss3(p/o/op) analog vdd power pad vdd2i_abb/vdd2op_abb/vdd2t_abb 4-103 analog vss power pads vss2i_abb/vss2op_abb/vss2t_abb vbb_abb/vssbb_abb cell type cell name page analog input with separated bulk-bias pic_abb 4-105 picc_abb picen_abb analog output with separated bulk-bias pot1/2/4/8_abb 4-108 cell type cell name page esd slot cells ev2i/ev2p/ev2o/ev2ip/ev2op/ev2t 4-111 ev3p/ev3o/ev3op ev2i_abb/ev2op_abb/ev2t/abb common slot cells ec0c0/ec0c0d 4-112 ec0ca0/ec0ca0d ec0c0_bb/ec0c0d_bb/ ec0c0_vbb/ec0c0d_vbb 4-112
samsung asic 4-7 STD111 input buffers cell list cell name function description pic/picd/picu 2.5v lvcmos level input buffers phic/phicd/phicu 3.3v lvcmos level input buffers ptic/pticd/pticu 5v-tolerant lvcmos level input buffers pis/pisd/pisu 2.5v lvcmos schmitt trigger level input buffers phis/phisd/phisu 3.3v lvcmos schmitt trigger level input buffers ptis/ptisd/ptisu 5v-tolerant lvcmos schmitt trigger level input buffers phit/phitd/phitu 3.3v lvttl level input buffers ptit/ptitd/ptitu 5v-tolerant lvttl level input buffers
STD111 4-8 samsung asic pvic/pvicd/pvicu lvcmos level input buffers cell availability logic symbol 2.5v only 3.3v interface 5v tolerant pic/picd/picu phic/phicd/phicu ptic/pticd/pticu truth table standard load (sl) pa d p i y p o 1110 0x01 1011 cell name pi pic/picd/picu 2.897 phic/phicd/phicu 2.897 ptic/pticd/pticu 2.897 y po pi pa d y po pi pa d y po pi pa d pic picd picu
samsung asic 4-9 STD111 pvic/pvicd/pvicu lvcmos level input buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 3.00ns, sl: standard load) pic picd picu note: the delay measure point of lvcmos input buffer is from pad(vdd/2) to y(vdd/2). path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.204 0.186 + 0.009*sl 0.184 + 0.010*sl 0.165 + 0.010*sl t f 0.151 0.138 + 0.006*sl 0.141 + 0.006*sl 0.128 + 0.006*sl t plh 0.629 0.615 + 0.007*sl 0.621 + 0.005*sl 0.637 + 0.005*sl t phl 0.547 0.535 + 0.006*sl 0.542 + 0.004*sl 0.571 + 0.003*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.204 0.186 + 0.009*sl 0.183 + 0.010*sl 0.165 + 0.010*sl t f 0.153 0.141 + 0.006*sl 0.143 + 0.006*sl 0.131 + 0.006*sl t plh 0.684 0.669 + 0.007*sl 0.675 + 0.005*sl 0.692 + 0.005*sl t phl 0.518 0.506 + 0.006*sl 0.512 + 0.004*sl 0.542 + 0.003*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.206 0.188 + 0.009*sl 0.186 + 0.010*sl 0.166 + 0.010*sl t f 0.151 0.139 + 0.006*sl 0.140 + 0.006*sl 0.128 + 0.006*sl t plh 0.588 0.574 + 0.007*sl 0.580 + 0.005*sl 0.597 + 0.005*sl t phl 0.603 0.591 + 0.006*sl 0.598 + 0.004*sl 0.627 + 0.003*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
STD111 4-10 samsung asic pvic/pvicd/pvicu lvcmos level input buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, sl: standard load) phic phicd phicu note: the delay measure point of lvcmos input buffer is from pad(vdd/2) to y(vdd/2). path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.133 0.124 + 0.005*sl 0.124 + 0.005*sl 0.117 + 0.005*sl t f 0.139 0.130 + 0.005*sl 0.132 + 0.004*sl 0.137 + 0.004*sl t plh 0.770 0.763 + 0.003*sl 0.765 + 0.003*sl 0.775 + 0.003*sl t phl 0.893 0.885 + 0.004*sl 0.888 + 0.003*sl 0.913 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.133 0.123 + 0.005*sl 0.123 + 0.005*sl 0.117 + 0.005*sl t f 0.139 0.130 + 0.004*sl 0.132 + 0.004*sl 0.137 + 0.004*sl t plh 0.847 0.840 + 0.003*sl 0.842 + 0.003*sl 0.853 + 0.003*sl t phl 0.856 0.849 + 0.004*sl 0.852 + 0.003*sl 0.877 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.133 0.124 + 0.005*sl 0.123 + 0.005*sl 0.117 + 0.005*sl t f 0.139 0.129 + 0.005*sl 0.132 + 0.004*sl 0.137 + 0.004*sl t plh 0.714 0.708 + 0.003*sl 0.710 + 0.003*sl 0.720 + 0.003*sl t phl 0.968 0.960 + 0.004*sl 0.964 + 0.003*sl 0.989 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
samsung asic 4-11 STD111 pvic/pvicd/pvicu lvcmos level input buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, sl: standard load) ptic pticd pticu note: the delay measure point of lvcmos input buffer is from pad(vdd/2) to y(vdd/2). path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.134 0.124 + 0.005*sl 0.124 + 0.005*sl 0.118 + 0.005*sl t f 0.139 0.129 + 0.005*sl 0.132 + 0.004*sl 0.137 + 0.004*sl t plh 0.920 0.913 + 0.003*sl 0.916 + 0.003*sl 0.926 + 0.003*sl t phl 1.274 1.266 + 0.004*sl 1.270 + 0.003*sl 1.294 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.134 0.124 + 0.005*sl 0.124 + 0.005*sl 0.117 + 0.005*sl t f 0.139 0.130 + 0.005*sl 0.132 + 0.004*sl 0.137 + 0.004*sl t plh 1.002 0.995 + 0.003*sl 0.997 + 0.003*sl 1.008 + 0.003*sl t phl 1.239 1.231 + 0.004*sl 1.234 + 0.003*sl 1.259 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.134 0.124 + 0.005*sl 0.123 + 0.005*sl 0.118 + 0.005*sl t f 0.139 0.130 + 0.004*sl 0.132 + 0.004*sl 0.136 + 0.004*sl t plh 0.767 0.760 + 0.003*sl 0.762 + 0.003*sl 0.772 + 0.003*sl t phl 1.469 1.461 + 0.004*sl 1.464 + 0.003*sl 1.489 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
STD111 4-12 samsung asic pvis/pvisd/pvisu lvcmos schmitt trigger level input buffers cell availability logic symbol 2.5v only 3.3v interface 5v tolerant pis/pisd/pisu phis/phisd/phisu ptis/ptisd/ptisu truth table standard load (sl) pa d p i y p o 1110 0x01 1011 cell name pi pis/pisd/pisu 2.897 phis/phisd/phisu 2.897 ptis/ptisd/ptisu 2.897 y po pi pa d y po pi pa d y po pi pa d pis pisd pisu
samsung asic 4-13 STD111 pvis/pvisd/pvisu lvcmos schmitt trigger level input buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 3.00ns, sl: standard load) pis pisd pisu path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.225 0.203 + 0.011*sl 0.206 + 0.010*sl 0.199 + 0.010*sl t f 0.165 0.150 + 0.008*sl 0.155 + 0.006*sl 0.173 + 0.006*sl t plh 0.992 0.976 + 0.008*sl 0.983 + 0.006*sl 1.019 + 0.005*sl t phl 0.935 0.921 + 0.007*sl 0.928 + 0.005*sl 0.973 + 0.004*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.224 0.203 + 0.011*sl 0.206 + 0.010*sl 0.198 + 0.010*sl t f 0.167 0.152 + 0.007*sl 0.156 + 0.006*sl 0.174 + 0.006*sl t plh 1.045 1.029 + 0.008*sl 1.036 + 0.006*sl 1.072 + 0.005*sl t phl 0.921 0.908 + 0.007*sl 0.914 + 0.005*sl 0.960 + 0.004*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.226 0.205 + 0.011*sl 0.208 + 0.010*sl 0.201 + 0.010*sl t f 0.165 0.150 + 0.008*sl 0.155 + 0.006*sl 0.173 + 0.006*sl t plh 0.961 0.944 + 0.008*sl 0.952 + 0.006*sl 0.989 + 0.005*sl t phl 0.991 0.978 + 0.007*sl 0.985 + 0.005*sl 1.029 + 0.004*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
STD111 4-14 samsung asic pvis/pvisd/pvisu lvcmos schmitt trigger level input buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, sl: standard load) phis phisd phisu path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.133 0.123 + 0.005*sl 0.123 + 0.005*sl 0.117 + 0.005*sl t f 0.139 0.130 + 0.005*sl 0.132 + 0.004*sl 0.137 + 0.004*sl t plh 0.998 0.992 + 0.003*sl 0.994 + 0.003*sl 1.004 + 0.003*sl t phl 1.339 1.331 + 0.004*sl 1.334 + 0.003*sl 1.359 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.133 0.123 + 0.005*sl 0.123 + 0.005*sl 0.117 + 0.005*sl t f 0.139 0.130 + 0.004*sl 0.131 + 0.004*sl 0.137 + 0.004*sl t plh 1.076 1.069 + 0.003*sl 1.071 + 0.003*sl 1.081 + 0.003*sl t phl 1.337 1.329 + 0.004*sl 1.332 + 0.003*sl 1.357 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.133 0.123 + 0.005*sl 0.123 + 0.005*sl 0.117 + 0.005*sl t f 0.139 0.129 + 0.005*sl 0.132 + 0.004*sl 0.136 + 0.004*sl t plh 0.944 0.937 + 0.003*sl 0.939 + 0.003*sl 0.949 + 0.003*sl t phl 1.416 1.408 + 0.004*sl 1.412 + 0.003*sl 1.437 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
samsung asic 4-15 STD111 pvis/pvisd/pvisu lvcmos schmitt trigger level input buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, sl: standard load) ptis ptisd ptisu note: the delay measure point of lvcmos input buffer is from pad(vdd/2) to y(vdd/2). path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.136 0.126 + 0.005*sl 0.126 + 0.005*sl 0.119 + 0.005*sl t f 0.139 0.130 + 0.004*sl 0.132 + 0.004*sl 0.137 + 0.004*sl t plh 1.164 1.158 + 0.003*sl 1.160 + 0.003*sl 1.170 + 0.003*sl t phl 1.387 1.379 + 0.004*sl 1.382 + 0.003*sl 1.407 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.136 0.127 + 0.005*sl 0.126 + 0.005*sl 0.119 + 0.005*sl t f 0.139 0.129 + 0.005*sl 0.132 + 0.004*sl 0.137 + 0.004*sl t plh 1.248 1.241 + 0.003*sl 1.243 + 0.003*sl 1.253 + 0.003*sl t phl 1.374 1.366 + 0.004*sl 1.370 + 0.003*sl 1.394 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.136 0.126 + 0.005*sl 0.126 + 0.005*sl 0.119 + 0.005*sl t f 0.139 0.129 + 0.005*sl 0.132 + 0.004*sl 0.137 + 0.004*sl t plh 1.017 1.010 + 0.003*sl 1.013 + 0.003*sl 1.023 + 0.003*sl t phl 1.536 1.528 + 0.004*sl 1.532 + 0.003*sl 1.557 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
STD111 4-16 samsung asic pvit/pvitd/pvitu lvttl level input buffers cell availability logic symbol 3.3v interface 5v tolerant phit/phitd/phitu ptit/ptitd/ptitu truth table standard load (sl) pa d p i y p o 1110 0x01 1011 cell name pi phit/phitd/phitu 2.897 ptit/ptitd/ptitu 2.897 y po pi pa d y po pi pa d y po pi pa d pit pitd pitu
samsung asic 4-17 STD111 pvit/pvitd/pvitu lvttl level input buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, sl: standard load) phit phitd phitu note: the delay measure point of lvttl input buffer is from pad(1.4) to y(vdd/2). path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.133 0.123 + 0.005*sl 0.123 + 0.005*sl 0.117 + 0.005*sl t f 0.139 0.130 + 0.005*sl 0.132 + 0.004*sl 0.137 + 0.004*sl t plh 0.665 0.658 + 0.003*sl 0.660 + 0.003*sl 0.670 + 0.003*sl t phl 0.930 0.922 + 0.004*sl 0.925 + 0.003*sl 0.950 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.133 0.124 + 0.005*sl 0.123 + 0.005*sl 0.117 + 0.005*sl t f 0.139 0.130 + 0.004*sl 0.131 + 0.004*sl 0.137 + 0.004*sl t plh 0.750 0.743 + 0.003*sl 0.746 + 0.003*sl 0.756 + 0.003*sl t phl 0.905 0.897 + 0.004*sl 0.900 + 0.003*sl 0.925 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.133 0.123 + 0.005*sl 0.123 + 0.005*sl 0.117 + 0.005*sl t f 0.139 0.129 + 0.005*sl 0.132 + 0.004*sl 0.137 + 0.004*sl t plh 0.601 0.594 + 0.003*sl 0.596 + 0.003*sl 0.606 + 0.003*sl t phl 1.006 0.998 + 0.004*sl 1.001 + 0.003*sl 1.026 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
STD111 4-18 samsung asic pvit/pvitd/pvitu lvttl level input buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, sl: standard load) ptit ptitd ptitu path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.133 0.123 + 0.005*sl 0.123 + 0.005*sl 0.117 + 0.005*sl t f 0.139 0.130 + 0.005*sl 0.132 + 0.004*sl 0.137 + 0.004*sl t plh 0.751 0.744 + 0.003*sl 0.746 + 0.003*sl 0.757 + 0.003*sl t phl 1.194 1.186 + 0.004*sl 1.190 + 0.003*sl 1.215 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.133 0.123 + 0.005*sl 0.123 + 0.005*sl 0.117 + 0.005*sl t f 0.139 0.129 + 0.005*sl 0.132 + 0.004*sl 0.137 + 0.004*sl t plh 0.899 0.892 + 0.003*sl 0.895 + 0.003*sl 0.905 + 0.003*sl t phl 1.194 1.186 + 0.004*sl 1.189 + 0.003*sl 1.214 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.133 0.124 + 0.005*sl 0.123 + 0.005*sl 0.117 + 0.005*sl t f 0.139 0.130 + 0.005*sl 0.132 + 0.004*sl 0.137 + 0.004*sl t plh 0.653 0.646 + 0.003*sl 0.648 + 0.003*sl 0.658 + 0.003*sl t phl 1.438 1.430 + 0.004*sl 1.433 + 0.003*sl 1.458 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
samsung asic 4-19 STD111 output buffers cell list cell name function description pob(1/2/4/6/8/10/12) 2.5v lvcmos normal output buffers pob(4/6/8/10/12)sm 2.5v lvcmos normal output buffers with medium slew-rate pob(10/12)sh 2.5v lvcmos normal output buffers with high slew-rate phob(1/2/4/6/8/10/12) 3.3v lvcmos normal output buffers phob(4/6/8/10/12)sm 3.3v lvcmos normal output buffers with medium slew-rate phob(10/12)sh 3.3v lvcmos normal output buffers with high slew-rate pod(1/2/4/6/8/10/12) 2.5v lvcmos open drain output buffers pod(4/6/8/10/12)sm 2.5v lvcmos open drain output buffers with medium slew-rate pod(10/12)sh 2.5v lvcmos open drain output buffers with high slew-rate phod(1/2/4/6/8/10/12) 3.3v lvcmos open drain output buffers phod(4/6/8/10/12)sm 3.3v lvcmos open drain output buffers with medium slew-rate phod(10/12)sh 3.3v lvcmos open drain output buffers with high slew-rate ptod(1/2/3) 5v tolerant open drain output buffers pot(1/2/4/6/8/10/12) 2.5v lvcmos tri-state output buffers pot(4/6/8/10/12)sm 2.5v lvcmos tri-state output buffers with medium slew-rate pot(10/12)sh 2.5v lvcmos tri-state output buffers with high slew-rate phot(1/2/4/6/8/10/12) 3.3v lvcmos tri-state output buffers phot(4/6/8/10/12)sm 3.3v lvcmos tri-state output buffers with medium slew-rate phot(10/12)sh 3.3v lvcmos tri-state output buffers with high slew-rate ptot(1/2/3) 5v tolerant tri-state output buffers
STD111 4-20 samsung asic pvobyz normal output buffers cell availability logic symbol standard load (sl) only 2.5v 3.3v interface pob(1/2/4/6/8/10/12) pob(4/6/8/10/12)sm pob(10/12)sh phob(1/2/4/6/8/10/12) phob(4/6/8/10/12)sm phob(10/12)sh cell name a pob(1/2/4/6/8) 9.801 pob(8/10/12)sm 16.532 pob(10/12) 19.614 pob(10/12)sh 25.576 phob(1/2/4/6/8/10/12) 5.444 phob(4/6/8/10/12)sm 5.444 phob(10/12)sh 5.444 truth table apad 00 11 pa d a
samsung asic 4-21 STD111 pvobyz normal output buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load[pf]) pob1 pob2 pob4 pob6 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 31.508 1.210 + 0.606*cl 1.212 + 0.606*cl 1.209 + 0.606*cl t f 33.275 1.275 + 0.640*cl 1.279 + 0.640*cl 1.276 + 0.640*cl t plh 15.295 0.789 + 0.290*cl 0.787 + 0.290*cl 0.790 + 0.290*cl t phl 17.054 0.944 + 0.322*cl 0.946 + 0.322*cl 0.946 + 0.322*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 15.772 0.624 + 0.303*cl 0.622 + 0.303*cl 0.625 + 0.303*cl t f 18.210 0.685 + 0.351*cl 0.688 + 0.350*cl 0.685 + 0.350*cl t plh 7.843 0.590 + 0.145*cl 0.590 + 0.145*cl 0.589 + 0.145*cl t phl 9.699 0.580 + 0.182*cl 0.580 + 0.182*cl 0.578 + 0.182*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 7.917 0.348 + 0.151*cl 0.342 + 0.151*cl 0.343 + 0.151*cl t f 9.121 0.359 + 0.175*cl 0.359 + 0.175*cl 0.359 + 0.175*cl t plh 4.271 0.643 + 0.073*cl 0.644 + 0.073*cl 0.644 + 0.073*cl t phl 5.026 0.468 + 0.091*cl 0.467 + 0.091*cl 0.466 + 0.091*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 5.317 0.308 + 0.100*cl 0.280 + 0.101*cl 0.265 + 0.101*cl t f 6.097 0.261 + 0.117*cl 0.256 + 0.117*cl 0.256 + 0.117*cl t plh 3.204 0.785 + 0.048*cl 0.786 + 0.048*cl 0.786 + 0.048*cl t phl 3.520 0.487 + 0.061*cl 0.483 + 0.061*cl 0.481 + 0.061*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-22 samsung asic pvobyz normal output buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load[pf]) pob8 pob10 pob12 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 5.293 0.230 + 0.101*cl 0.228 + 0.101*cl 0.228 + 0.101*cl t f 4.572 0.205 + 0.087*cl 0.202 + 0.087*cl 0.201 + 0.087*cl t plh 3.470 1.129 + 0.047*cl 1.128 + 0.047*cl 1.127 + 0.047*cl t phl 3.069 0.845 + 0.044*cl 0.845 + 0.044*cl 0.845 + 0.044*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 3.217 0.236 + 0.060*cl 0.207 + 0.060*cl 0.189 + 0.060*cl t f 3.668 0.174 + 0.070*cl 0.166 + 0.070*cl 0.163 + 0.070*cl t plh 2.107 0.654 + 0.029*cl 0.656 + 0.029*cl 0.656 + 0.029*cl t phl 2.218 0.401 + 0.036*cl 0.397 + 0.036*cl 0.395 + 0.036*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 2.719 0.264 + 0.049*cl 0.229 + 0.050*cl 0.202 + 0.050*cl t f 3.069 0.166 + 0.058*cl 0.154 + 0.058*cl 0.148 + 0.058*cl t plh 1.950 0.734 + 0.024*cl 0.739 + 0.024*cl 0.740 + 0.024*cl t phl 1.942 0.433 + 0.030*cl 0.427 + 0.030*cl 0.424 + 0.030*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-23 STD111 pvobyz normal output buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load[pf]) pob4sm pob6sm pob8sm pob10sm path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 8.135 0.752 + 0.148*cl 0.660 + 0.149*cl 0.586 + 0.150*cl t f 9.483 1.001 + 0.170*cl 0.889 + 0.172*cl 0.787 + 0.173*cl t plh 5.457 1.802 + 0.073*cl 1.823 + 0.073*cl 1.829 + 0.073*cl t phl 6.998 2.362 + 0.093*cl 2.422 + 0.092*cl 2.439 + 0.091*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 6.045 1.305 + 0.095*cl 1.245 + 0.096*cl 1.147 + 0.097*cl t f 6.980 1.447 + 0.111*cl 1.410 + 0.111*cl 1.318 + 0.113*cl t plh 5.100 2.394 + 0.054*cl 2.575 + 0.051*cl 2.676 + 0.049*cl t phl 6.308 2.898 + 0.068*cl 3.119 + 0.064*cl 3.254 + 0.062*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 5.152 1.648 + 0.070*cl 1.663 + 0.070*cl 1.594 + 0.071*cl t f 5.708 1.557 + 0.083*cl 1.595 + 0.082*cl 1.543 + 0.083*cl t plh 4.762 2.427 + 0.047*cl 2.708 + 0.041*cl 2.900 + 0.039*cl t phl 5.616 2.839 + 0.056*cl 3.103 + 0.050*cl 3.289 + 0.048*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 4.204 1.322 + 0.058*cl 1.361 + 0.057*cl 1.342 + 0.057*cl t f 4.729 1.356 + 0.067*cl 1.416 + 0.066*cl 1.403 + 0.066*cl t plh 4.405 2.495 + 0.038*cl 2.718 + 0.034*cl 2.886 + 0.032*cl t phl 5.175 2.861 + 0.046*cl 3.101 + 0.041*cl 3.281 + 0.039*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-24 samsung asic pvobyz normal output buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load[pf]) pob12sm pob10sh pob12sh path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 4.190 1.629 + 0.051*cl 1.774 + 0.048*cl 1.847 + 0.047*cl t f 4.546 1.542 + 0.060*cl 1.723 + 0.056*cl 1.811 + 0.055*cl t plh 4.640 2.688 + 0.039*cl 2.990 + 0.033*cl 3.244 + 0.030*cl t phl 5.372 3.145 + 0.045*cl 3.432 + 0.039*cl 3.677 + 0.036*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 6.202 2.922 + 0.066*cl 3.205 + 0.060*cl 3.394 + 0.057*cl t f 6.442 2.722 + 0.074*cl 2.995 + 0.069*cl 3.168 + 0.067*cl t plh 7.316 4.395 + 0.058*cl 4.943 + 0.047*cl 5.408 + 0.041*cl t phl 7.953 4.743 + 0.064*cl 5.265 + 0.054*cl 5.711 + 0.048*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 6.575 3.532 + 0.061*cl 3.914 + 0.053*cl 4.189 + 0.050*cl t f 6.532 3.087 + 0.069*cl 3.482 + 0.061*cl 3.754 + 0.057*cl t plh 7.825 4.698 + 0.063*cl 5.373 + 0.049*cl 5.946 + 0.041*cl t phl 8.410 5.170 + 0.065*cl 5.765 + 0.053*cl 6.283 + 0.046*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-25 STD111 pvobyz normal output buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 0.17ns, cl: capacitive load[pf]) phob1 phob2 phob4 phob6 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 42.148 1.623 + 0.811*cl 1.624 + 0.810*cl 1.621 + 0.811*cl t f 33.014 1.269 + 0.635*cl 1.270 + 0.635*cl 1.267 + 0.635*cl t plh 20.150 1.403 + 0.375*cl 1.404 + 0.375*cl 1.401 + 0.375*cl t phl 16.887 1.325 + 0.311*cl 1.321 + 0.311*cl 1.324 + 0.311*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 21.098 0.836 + 0.405*cl 0.836 + 0.405*cl 0.833 + 0.405*cl t f 18.188 0.706 + 0.350*cl 0.702 + 0.350*cl 0.705 + 0.350*cl t plh 10.450 1.078 + 0.187*cl 1.076 + 0.187*cl 1.076 + 0.187*cl t phl 9.844 0.948 + 0.178*cl 0.949 + 0.178*cl 0.947 + 0.178*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 10.563 0.433 + 0.203*cl 0.431 + 0.203*cl 0.431 + 0.203*cl t f 9.114 0.371 + 0.175*cl 0.371 + 0.175*cl 0.372 + 0.175*cl t plh 5.676 0.991 + 0.094*cl 0.990 + 0.094*cl 0.990 + 0.094*cl t phl 5.280 0.832 + 0.089*cl 0.832 + 0.089*cl 0.833 + 0.089*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 7.047 0.294 + 0.135*cl 0.294 + 0.135*cl 0.293 + 0.135*cl t f 6.082 0.254 + 0.117*cl 0.254 + 0.117*cl 0.255 + 0.117*cl t plh 4.232 1.109 + 0.062*cl 1.108 + 0.062*cl 1.108 + 0.062*cl t phl 3.804 0.839 + 0.059*cl 0.839 + 0.059*cl 0.840 + 0.059*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-26 samsung asic pvobyz normal output buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 0.17ns, cl: capacitive load[pf]) phob8 phob10 phob12 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 5.293 0.230 + 0.101*cl 0.228 + 0.101*cl 0.228 + 0.101*cl t f 4.572 0.205 + 0.087*cl 0.202 + 0.087*cl 0.201 + 0.087*cl t plh 3.470 1.129 + 0.047*cl 1.128 + 0.047*cl 1.127 + 0.047*cl t phl 3.069 0.845 + 0.044*cl 0.845 + 0.044*cl 0.845 + 0.044*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 4.243 0.197 + 0.081*cl 0.191 + 0.081*cl 0.190 + 0.081*cl t f 3.669 0.183 + 0.070*cl 0.174 + 0.070*cl 0.172 + 0.070*cl t plh 3.030 1.160 + 0.037*cl 1.157 + 0.037*cl 1.156 + 0.037*cl t phl 2.643 0.863 + 0.036*cl 0.863 + 0.036*cl 0.863 + 0.036*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 3.544 0.181 + 0.067*cl 0.170 + 0.067*cl 0.167 + 0.068*cl t f 3.070 0.176 + 0.058*cl 0.162 + 0.058*cl 0.156 + 0.058*cl t plh 2.751 1.197 + 0.031*cl 1.193 + 0.031*cl 1.190 + 0.031*cl t phl 2.370 0.887 + 0.030*cl 0.887 + 0.030*cl 0.887 + 0.030*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-27 STD111 pvobyz normal output buffers switching characteristics (typical process, 25 c, 2.5v,3.3v, t r /t f = 0.17ns, cl: capacitive load[pf]) phob4sm phob6sm phob8sm phob10sm path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 10.608 0.517 + 0.202*cl 0.486 + 0.202*cl 0.477 + 0.203*cl t f 9.435 0.947 + 0.170*cl 0.842 + 0.172*cl 0.750 + 0.173*cl t plh 6.404 1.715 + 0.094*cl 1.716 + 0.094*cl 1.718 + 0.094*cl t phl 7.039 2.530 + 0.090*cl 2.579 + 0.089*cl 2.594 + 0.089*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 7.211 0.618 + 0.132*cl 0.540 + 0.133*cl 0.478 + 0.134*cl t f 6.910 1.355 + 0.111*cl 1.328 + 0.112*cl 1.248 + 0.113*cl t plh 5.165 2.022 + 0.063*cl 2.037 + 0.063*cl 2.041 + 0.063*cl t phl 6.311 3.000 + 0.066*cl 3.208 + 0.062*cl 3.333 + 0.060*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 5.691 0.888 + 0.096*cl 0.802 + 0.098*cl 0.711 + 0.099*cl t f 6.059 1.788 + 0.085*cl 1.905 + 0.083*cl 1.926 + 0.083*cl t plh 4.807 2.352 + 0.049*cl 2.434 + 0.047*cl 2.466 + 0.047*cl t phl 6.336 3.367 + 0.059*cl 3.714 + 0.052*cl 3.984 + 0.049*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 4.501 0.614 + 0.078*cl 0.553 + 0.079*cl 0.502 + 0.080*cl t f 5.283 1.821 + 0.069*cl 1.971 + 0.066*cl 2.023 + 0.066*cl t plh 4.008 2.093 + 0.038*cl 2.129 + 0.038*cl 2.140 + 0.037*cl t phl 5.781 3.176 + 0.052*cl 3.541 + 0.045*cl 3.833 + 0.041*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-28 samsung asic pvobyz normal output buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 0.17ns, cl: capacitive load[pf]) phob12sm phob10sh phob12sh path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 4.002 0.794 + 0.064*cl 0.770 + 0.065*cl 0.723 + 0.065*cl t f 4.483 1.509 + 0.059*cl 1.656 + 0.057*cl 1.734 + 0.056*cl t plh 3.970 2.249 + 0.034*cl 2.350 + 0.032*cl 2.408 + 0.032*cl t phl 5.356 3.141 + 0.044*cl 3.442 + 0.038*cl 3.692 + 0.035*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 5.281 1.455 + 0.077*cl 1.475 + 0.076*cl 1.424 + 0.077*cl t f 6.213 2.435 + 0.076*cl 2.714 + 0.070*cl 2.902 + 0.067*cl t plh 5.749 3.412 + 0.047*cl 3.654 + 0.042*cl 3.825 + 0.040*cl t phl 7.639 4.521 + 0.062*cl 5.020 + 0.052*cl 5.446 + 0.047*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 4.972 1.688 + 0.066*cl 1.804 + 0.063*cl 1.821 + 0.063*cl t f 6.233 2.772 + 0.069*cl 3.130 + 0.062*cl 3.403 + 0.058*cl t plh 5.899 3.670 + 0.045*cl 3.971 + 0.039*cl 4.210 + 0.035*cl t phl 7.963 4.796 + 0.063*cl 5.374 + 0.052*cl 5.877 + 0.045*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-29 STD111 pvodyz open drain output buffers cell availability logic symbol standard load (sl) 2.5v only 3.3v interface 5v tolerant pod(1/2/4/6/8/10/12) pod(4/6/8/10/12)sm pod(10/12)sh phod(1/2/4/6/8/10/12) phod(4/6/8/10/12)sm phod(10/12)sh ptod(1/2/3) cell name tn en pod(1/2/4/6/8/10/12) 2.897 2.916 pod(4/6/8/10/12)sm 2.897 2.916 pod(10/12)sh 2.897 2.916 phod(1/2/4/6/8/10/12) 2.897 2.916 phod(4/6/8/10/12)sm 2.897 2.916 phod(10/12)sh 2.897 2.916 ptod(1/2/3) 2.897 2.916 truth table tn en pad 100 0 x hi-z x 1 hi-z pa d tn en
STD111 4-30 samsung asic pvodyz open drain output buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load[pf]) pod1 pod2 pod4 pod6 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 33.275 1.275 + 0.640*cl 1.279 + 0.640*cl 1.276 + 0.640*cl t phl 24.790 1.900 + 0.458*cl 1.764 + 0.461*cl 1.764 + 0.461*cl t plz 0.875 0.874 + 0.000*cl 0.875 + 0.000*cl 0.875 + 0.000*cl en to pad t f 33.275 1.275 + 0.640*cl 1.279 + 0.640*cl 1.276 + 0.640*cl t phl 24.888 1.998 + 0.458*cl 1.862 + 0.461*cl 1.862 + 0.461*cl t plz 0.917 0.917 + 0.000*cl 0.917 + 0.000*cl 0.917 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 18.210 0.685 + 0.351*cl 0.688 + 0.350*cl 0.685 + 0.350*cl t phl 14.231 1.304 + 0.259*cl 1.229 + 0.260*cl 1.229 + 0.260*cl t plz 0.728 0.728 + 0.000*cl 0.728 + 0.000*cl 0.728 + 0.000*cl en to pad t f 18.210 0.685 + 0.351*cl 0.688 + 0.350*cl 0.685 + 0.350*cl t phl 14.329 1.403 + 0.259*cl 1.327 + 0.260*cl 1.324 + 0.260*cl t plz 0.772 0.772 + 0.000*cl 0.771 + 0.000*cl 0.772 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 9.121 0.359 + 0.175*cl 0.359 + 0.175*cl 0.359 + 0.175*cl t phl 7.510 1.047 + 0.129*cl 1.008 + 0.130*cl 1.011 + 0.130*cl t plz 0.857 0.857 + 0.000*cl 0.857 + 0.000*cl 0.857 + 0.000*cl en to pad t f 9.121 0.359 + 0.175*cl 0.359 + 0.175*cl 0.359 + 0.175*cl t phl 7.609 1.146 + 0.129*cl 1.106 + 0.130*cl 1.110 + 0.130*cl t plz 0.900 0.900 + 0.000*cl 0.900 + 0.000*cl 0.900 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 6.097 0.255 + 0.117*cl 0.255 + 0.117*cl 0.256 + 0.117*cl t phl 5.319 1.010 + 0.086*cl 0.984 + 0.087*cl 0.984 + 0.087*cl t plz 0.984 0.984 + 0.000*cl 0.984 + 0.000*cl 0.984 + 0.000*cl en to pad t f 6.097 0.255 + 0.117*cl 0.255 + 0.117*cl 0.256 + 0.117*cl t phl 5.418 1.108 + 0.086*cl 1.083 + 0.087*cl 1.083 + 0.087*cl t plz 1.026 1.026 + 0.000*cl 1.026 + 0.000*cl 1.026 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-31 STD111 pvodyz open drain output buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load[pf]) pod8 pod10 pod12 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 4.588 0.206 + 0.088*cl 0.207 + 0.088*cl 0.207 + 0.088*cl t phl 4.260 1.028 + 0.065*cl 1.009 + 0.065*cl 1.009 + 0.065*cl t plz 1.111 1.111 + 0.000*cl 1.111 + 0.000*cl 1.111 + 0.000*cl en to pad t f 4.588 0.206 + 0.088*cl 0.207 + 0.088*cl 0.207 + 0.088*cl t phl 4.358 1.126 + 0.065*cl 1.107 + 0.065*cl 1.108 + 0.065*cl t plz 1.153 1.153 + 0.000*cl 1.153 + 0.000*cl 1.153 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 3.667 0.161 + 0.070*cl 0.162 + 0.070*cl 0.162 + 0.070*cl t phl 3.524 0.938 + 0.052*cl 0.923 + 0.052*cl 0.923 + 0.052*cl t plz 0.968 0.968 + 0.000*cl 0.968 + 0.000*cl 0.968 + 0.000*cl en to pad t f 3.667 0.161 + 0.070*cl 0.162 + 0.070*cl 0.162 + 0.070*cl t phl 3.623 1.037 + 0.052*cl 1.022 + 0.052*cl 1.022 + 0.052*cl t plz 1.011 1.011 + 0.000*cl 1.011 + 0.000*cl 1.011 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 3.064 0.143 + 0.058*cl 0.143 + 0.058*cl 0.144 + 0.058*cl t phl 3.108 0.953 + 0.043*cl 0.941 + 0.043*cl 0.941 + 0.043*cl t plz 1.032 1.031 + 0.000*cl 1.032 + 0.000*cl 1.032 + 0.000*cl en to pad t f 3.064 0.143 + 0.058*cl 0.143 + 0.058*cl 0.144 + 0.058*cl t phl 3.207 1.052 + 0.043*cl 1.039 + 0.043*cl 1.040 + 0.043*cl t plz 1.075 1.075 + 0.000*cl 1.075 + 0.000*cl 1.075 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-32 samsung asic pvodyz open drain output buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load[pf]) pod4sm pod6sm pod8sm path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 9.279 0.637 + 0.173*cl 0.549 + 0.175*cl 0.510 + 0.175*cl t phl 9.580 3.085 + 0.130*cl 3.073 + 0.130*cl 3.078 + 0.130*cl t plz 1.000 0.999 + 0.000*cl 1.000 + 0.000*cl 1.000 + 0.000*cl en to pad t f 9.279 0.637 + 0.173*cl 0.549 + 0.175*cl 0.510 + 0.175*cl t phl 9.679 3.183 + 0.130*cl 3.172 + 0.130*cl 3.177 + 0.130*cl t plz 1.043 1.042 + 0.000*cl 1.043 + 0.000*cl 1.043 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 6.521 0.979 + 0.111*cl 0.863 + 0.113*cl 0.735 + 0.115*cl t phl 8.285 3.720 + 0.091*cl 3.870 + 0.088*cl 3.952 + 0.087*cl t plz 1.275 1.275 + 0.000*cl 1.275 + 0.000*cl 1.275 + 0.000*cl en to pad t f 6.521 0.979 + 0.111*cl 0.863 + 0.113*cl 0.735 + 0.115*cl t phl 8.383 3.819 + 0.091*cl 3.968 + 0.088*cl 4.054 + 0.087*cl t plz 1.317 1.317 + 0.000*cl 1.317 + 0.000*cl 1.317 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 5.166 1.112 + 0.081*cl 1.028 + 0.083*cl 0.893 + 0.085*cl t phl 7.288 3.655 + 0.073*cl 3.883 + 0.068*cl 4.028 + 0.066*cl t plz 1.883 1.882 + 0.000*cl 1.883 + 0.000*cl 1.883 + 0.000*cl en to pad t f 5.166 1.112 + 0.081*cl 1.028 + 0.083*cl 0.893 + 0.085*cl t phl 7.387 3.754 + 0.073*cl 3.981 + 0.068*cl 4.126 + 0.066*cl t plz 1.926 1.924 + 0.000*cl 1.925 + 0.000*cl 1.925 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-33 STD111 pvodyz open drain output buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load[pf]) pod10sm pod12sm pod10sh pod12sh path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 4.261 0.986 + 0.066*cl 0.954 + 0.066*cl 0.867 + 0.067*cl t phl 6.653 3.655 + 0.060*cl 3.871 + 0.056*cl 4.025 + 0.054*cl t plz 1.883 1.882 + 0.000*cl 1.883 + 0.000*cl 1.883 + 0.000*cl en to pad t f 4.261 0.985 + 0.066*cl 0.955 + 0.066*cl 0.867 + 0.067*cl t phl 6.752 3.754 + 0.060*cl 3.970 + 0.056*cl 4.123 + 0.054*cl t plz 1.926 1.924 + 0.000*cl 1.925 + 0.000*cl 1.925 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 3.987 1.230 + 0.055*cl 1.278 + 0.054*cl 1.248 + 0.055*cl t phl 6.787 3.941 + 0.057*cl 4.253 + 0.051*cl 4.507 + 0.047*cl t plz 2.251 2.250 + 0.000*cl 2.251 + 0.000*cl 2.251 + 0.000*cl en to pad t f 3.987 1.230 + 0.055*cl 1.278 + 0.054*cl 1.248 + 0.055*cl t phl 6.886 4.040 + 0.057*cl 4.351 + 0.051*cl 4.606 + 0.047*cl t plz 2.294 2.292 + 0.000*cl 2.293 + 0.000*cl 2.293 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 5.431 2.047 + 0.068*cl 2.179 + 0.065*cl 2.213 + 0.065*cl t phl 9.785 5.852 + 0.079*cl 6.395 + 0.068*cl 6.860 + 0.062*cl t plz 2.322 2.321 + 0.000*cl 2.322 + 0.000*cl 2.322 + 0.000*cl en to pad t f 5.431 2.047 + 0.068*cl 2.179 + 0.065*cl 2.213 + 0.065*cl t phl 9.884 5.950 + 0.079*cl 6.494 + 0.068*cl 6.959 + 0.062*cl t plz 2.365 2.363 + 0.000*cl 2.364 + 0.000*cl 2.365 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 5.378 2.451 + 0.059*cl 2.627 + 0.055*cl 2.722 + 0.054*cl t phl 10.235 6.317 + 0.078*cl 6.969 + 0.065*cl 7.539 + 0.058*cl t plz 2.690 2.688 + 0.000*cl 2.689 + 0.000*cl 2.690 + 0.000*cl en to pad t f 5.378 2.451 + 0.059*cl 2.627 + 0.055*cl 2.722 + 0.054*cl t phl 10.334 6.416 + 0.078*cl 7.068 + 0.065*cl 7.638 + 0.058*cl t plz 2.733 2.730 + 0.000*cl 2.732 + 0.000*cl 2.733 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-34 samsung asic pvodyz open drain output buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 0.17ns, cl: capacitive load[pf]) phod1 phod2 phod4 phod6 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 33.014 1.269 + 0.635*cl 1.270 + 0.635*cl 1.267 + 0.635*cl t phl 17.228 1.663 + 0.311*cl 1.664 + 0.311*cl 1.664 + 0.311*cl t plz 1.199 1.198 + 0.000*cl 1.199 + 0.000*cl 1.199 + 0.000*cl en to pad t f 33.014 1.269 + 0.635*cl 1.270 + 0.635*cl 1.267 + 0.635*cl t phl 17.327 1.762 + 0.311*cl 1.763 + 0.311*cl 1.763 + 0.311*cl t plz 1.242 1.242 + 0.000*cl 1.242 + 0.000*cl 1.242 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 18.188 0.706 + 0.350*cl 0.702 + 0.350*cl 0.705 + 0.350*cl t phl 10.187 1.292 + 0.178*cl 1.291 + 0.178*cl 1.294 + 0.178*cl t plz 1.056 1.056 + 0.000*cl 1.056 + 0.000*cl 1.056 + 0.000*cl en to pad t f 18.188 0.706 + 0.350*cl 0.702 + 0.350*cl 0.705 + 0.350*cl t phl 10.286 1.391 + 0.178*cl 1.390 + 0.178*cl 1.393 + 0.178*cl t plz 1.100 1.100 + 0.000*cl 1.100 + 0.000*cl 1.100 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 9.114 0.371 + 0.175*cl 0.371 + 0.175*cl 0.372 + 0.175*cl t phl 5.622 1.175 + 0.089*cl 1.175 + 0.089*cl 1.175 + 0.089*cl t plz 1.206 1.206 + 0.000*cl 1.206 + 0.000*cl 1.206 + 0.000*cl en to pad t f 9.114 0.371 + 0.175*cl 0.371 + 0.175*cl 0.372 + 0.175*cl t phl 5.721 1.273 + 0.089*cl 1.274 + 0.089*cl 1.274 + 0.089*cl t plz 1.249 1.249 + 0.000*cl 1.249 + 0.000*cl 1.249 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 6.082 0.254 + 0.117*cl 0.254 + 0.117*cl 0.255 + 0.117*cl t phl 4.080 1.115 + 0.059*cl 1.115 + 0.059*cl 1.115 + 0.059*cl t plz 1.166 1.166 + 0.000*cl 1.166 + 0.000*cl 1.166 + 0.000*cl en to pad t f 6.082 0.254 + 0.117*cl 0.254 + 0.117*cl 0.255 + 0.117*cl t phl 4.179 1.214 + 0.059*cl 1.214 + 0.059*cl 1.214 + 0.059*cl t plz 1.209 1.209 + 0.000*cl 1.209 + 0.000*cl 1.209 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-35 STD111 pvodyz open drain output buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 0.17ns, cl: capacitive load[pf]) phod8 phod10 phod12 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 4.572 0.205 + 0.087*cl 0.202 + 0.087*cl 0.201 + 0.087*cl t phl 3.344 1.120 + 0.044*cl 1.120 + 0.044*cl 1.120 + 0.044*cl t plz 1.240 1.240 + 0.000*cl 1.240 + 0.000*cl 1.240 + 0.000*cl en to pad t f 4.572 0.205 + 0.087*cl 0.202 + 0.087*cl 0.201 + 0.087*cl t phl 3.443 1.219 + 0.044*cl 1.219 + 0.044*cl 1.219 + 0.044*cl t plz 1.284 1.284 + 0.000*cl 1.284 + 0.000*cl 1.284 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 3.669 0.183 + 0.070*cl 0.175 + 0.070*cl 0.172 + 0.070*cl t phl 2.917 1.137 + 0.036*cl 1.138 + 0.036*cl 1.137 + 0.036*cl t plz 1.315 1.315 + 0.000*cl 1.315 + 0.000*cl 1.315 + 0.000*cl en to pad t f 3.669 0.183 + 0.070*cl 0.175 + 0.070*cl 0.172 + 0.070*cl t phl 3.016 1.236 + 0.036*cl 1.236 + 0.036*cl 1.237 + 0.036*cl t plz 1.359 1.359 + 0.000*cl 1.359 + 0.000*cl 1.359 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 3.071 0.177 + 0.058*cl 0.163 + 0.058*cl 0.156 + 0.058*cl t phl 2.644 1.161 + 0.030*cl 1.161 + 0.030*cl 1.161 + 0.030*cl t plz 1.390 1.390 + 0.000*cl 1.390 + 0.000*cl 1.390 + 0.000*cl en to pad t f 3.071 0.177 + 0.058*cl 0.163 + 0.058*cl 0.156 + 0.058*cl t phl 2.743 1.260 + 0.030*cl 1.260 + 0.030*cl 1.260 + 0.030*cl t plz 1.433 1.433 + 0.000*cl 1.433 + 0.000*cl 1.433 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-36 samsung asic pvodyz open drain output buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load[pf]) phod4sm phod6sm phod8sm path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 9.439 0.956 + 0.170*cl 0.850 + 0.172*cl 0.752 + 0.173*cl t phl 7.343 2.833 + 0.090*cl 2.883 + 0.089*cl 2.896 + 0.089*cl t plz 1.304 1.305 + 0.000*cl 1.303 + 0.000*cl 1.305 + 0.000*cl en to pad t f 9.439 0.956 + 0.170*cl 0.850 + 0.172*cl 0.752 + 0.173*cl t phl 7.441 2.932 + 0.090*cl 2.981 + 0.089*cl 2.995 + 0.089*cl t plz 1.349 1.348 + 0.000*cl 1.349 + 0.000*cl 1.349 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 6.922 1.379 + 0.111*cl 1.347 + 0.111*cl 1.264 + 0.113*cl t phl 6.621 3.306 + 0.066*cl 3.516 + 0.062*cl 3.643 + 0.060*cl t plz 1.609 1.609 + 0.000*cl 1.609 + 0.000*cl 1.609 + 0.000*cl en to pad t f 6.922 1.379 + 0.111*cl 1.347 + 0.111*cl 1.264 + 0.113*cl t phl 6.720 3.405 + 0.066*cl 3.615 + 0.062*cl 3.742 + 0.060*cl t plz 1.653 1.653 + 0.000*cl 1.653 + 0.000*cl 1.653 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 6.080 1.825 + 0.085*cl 1.936 + 0.083*cl 1.953 + 0.083*cl t phl 6.644 3.669 + 0.059*cl 4.019 + 0.052*cl 4.291 + 0.049*cl t plz 1.913 1.913 + 0.000*cl 1.913 + 0.000*cl 1.913 + 0.000*cl en to pad t f 6.080 1.825 + 0.085*cl 1.936 + 0.083*cl 1.953 + 0.083*cl t phl 6.743 3.768 + 0.059*cl 4.118 + 0.053*cl 4.390 + 0.049*cl t plz 1.957 1.957 + 0.000*cl 1.956 + 0.000*cl 1.957 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-37 STD111 pvodyz open drain output buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 0.17ns, cl: capacitive load[pf]) phod10sm phod12sm phod10sh phod12sh path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 5.308 1.865 + 0.069*cl 2.008 + 0.066*cl 2.054 + 0.065*cl t phl 6.099 3.486 + 0.052*cl 3.855 + 0.045*cl 4.150 + 0.041*cl t plz 2.661 2.661 + 0.000*cl 2.661 + 0.000*cl 2.661 + 0.000*cl en to pad t f 5.308 1.865 + 0.069*cl 2.008 + 0.066*cl 2.054 + 0.065*cl t phl 6.198 3.585 + 0.052*cl 3.955 + 0.045*cl 4.249 + 0.041*cl t plz 2.705 2.705 + 0.000*cl 2.705 + 0.000*cl 2.704 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 4.505 1.544 + 0.059*cl 1.686 + 0.056*cl 1.760 + 0.055*cl t phl 5.672 3.452 + 0.044*cl 3.756 + 0.038*cl 4.008 + 0.035*cl t plz 2.661 2.661 + 0.000*cl 2.661 + 0.000*cl 2.661 + 0.000*cl en to pad t f 4.505 1.544 + 0.059*cl 1.686 + 0.056*cl 1.760 + 0.055*cl t phl 5.771 3.551 + 0.044*cl 3.855 + 0.038*cl 4.107 + 0.035*cl t plz 2.705 2.705 + 0.000*cl 2.705 + 0.000*cl 2.705 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 6.249 2.489 + 0.075*cl 2.762 + 0.070*cl 2.945 + 0.067*cl t phl 7.897 4.768 + 0.063*cl 5.272 + 0.052*cl 5.704 + 0.047*cl t plz 2.715 2.715 + 0.000*cl 2.715 + 0.000*cl 2.715 + 0.000*cl en to pad t f 6.249 2.489 + 0.075*cl 2.762 + 0.070*cl 2.945 + 0.067*cl t phl 7.996 4.867 + 0.063*cl 5.371 + 0.052*cl 5.803 + 0.047*cl t plz 2.757 2.757 + 0.000*cl 2.757 + 0.000*cl 2.757 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 6.277 2.841 + 0.069*cl 3.190 + 0.062*cl 3.455 + 0.058*cl t phl 8.214 5.033 + 0.064*cl 5.618 + 0.052*cl 6.126 + 0.045*cl t plz 3.120 3.119 + 0.000*cl 3.120 + 0.000*cl 3.120 + 0.000*cl en to pad t f 6.277 2.841 + 0.069*cl 3.190 + 0.062*cl 3.455 + 0.058*cl t phl 8.313 5.132 + 0.064*cl 5.717 + 0.052*cl 6.226 + 0.045*cl t plz 3.162 3.161 + 0.000*cl 3.162 + 0.000*cl 3.162 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-38 samsung asic pvodyz open drain output buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 0.17ns, cl: capacitive load[pf]) ptod1 ptod2 ptod3 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 33.498 2.496 + 0.620*cl 2.456 + 0.621*cl 2.426 + 0.621*cl t phl 16.998 1.635 + 0.307*cl 1.632 + 0.307*cl 1.641 + 0.307*cl t plz 1.028 1.028 + 0.000*cl 1.028 + 0.000*cl 1.028 + 0.000*cl en to pad t f 33.498 2.496 + 0.620*cl 2.456 + 0.621*cl 2.426 + 0.621*cl t phl 17.097 1.734 + 0.307*cl 1.733 + 0.307*cl 1.736 + 0.307*cl t plz 1.072 1.072 + 0.000*cl 1.072 + 0.000*cl 1.072 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 16.748 1.240 + 0.310*cl 1.234 + 0.310*cl 1.222 + 0.310*cl t phl 8.985 1.312 + 0.153*cl 1.315 + 0.153*cl 1.312 + 0.153*cl t plz 1.151 1.151 + 0.000*cl 1.151 + 0.000*cl 1.151 + 0.000*cl en to pad t f 16.748 1.240 + 0.310*cl 1.234 + 0.310*cl 1.222 + 0.310*cl t phl 9.084 1.411 + 0.153*cl 1.414 + 0.153*cl 1.411 + 0.153*cl t plz 1.195 1.195 + 0.000*cl 1.195 + 0.000*cl 1.195 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t f 11.158 0.810 + 0.207*cl 0.812 + 0.207*cl 0.809 + 0.207*cl t phl 6.351 1.235 + 0.102*cl 1.238 + 0.102*cl 1.239 + 0.102*cl t plz 1.272 1.272 + 0.000*cl 1.272 + 0.000*cl 1.272 + 0.000*cl en to pad t f 11.158 0.810 + 0.207*cl 0.812 + 0.207*cl 0.809 + 0.207*cl t phl 6.450 1.334 + 0.102*cl 1.337 + 0.102*cl 1.338 + 0.102*cl t plz 1.316 1.316 + 0.000*cl 1.316 + 0.000*cl 1.316 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-39 STD111 pvotyz tri-state output buffers cell availability logic symbol standard load (sl) 2.5v only 3.3v interface 5v tolerant pot(1/2/4/6/8/10/12) pot(4/6/8/10/12)sm pot(10/12)sh phot(1/2/4/6/8/10/12) phot(4/6/8/10/12)sm phot(10/12)sh ptot(1/2/3) cell name tn en a pot(1/2/4/6/8/10/12) 2.898 2.916 3.023 pot(4/6/8/10/12)sm 2.898 2.916 3.023 pot(10/12)sh 2.898 2.916 3.023 phot(1/2/4/6/8/10/12) 2.898 2.916 5.444 phot(4/6/8/10/12)sm 2.898 2.916 5.444 phot(10/12)sh 2.898 2.916 5.444 ptot(1/2/3) 2.898 2.916 5.444 truth table tn en a pad 1000 1011 x 1 x hi-z 0 x x hi-z pa d a tn en
STD111 4-40 samsung asic pvotyz tri-state output buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load[pf]) pot1 pot2 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 31.508 1.210 + 0.606*cl 1.212 + 0.606*cl 1.209 + 0.606*cl t f 33.275 1.275 + 0.640*cl 1.279 + 0.640*cl 1.276 + 0.640*cl t plh 15.732 1.226 + 0.290*cl 1.224 + 0.290*cl 1.224 + 0.290*cl t phl 17.556 1.448 + 0.322*cl 1.448 + 0.322*cl 1.445 + 0.322*cl tn to pad t r 31.508 1.210 + 0.606*cl 1.212 + 0.606*cl 1.209 + 0.606*cl t f 33.275 1.275 + 0.640*cl 1.279 + 0.640*cl 1.276 + 0.640*cl t plh 15.780 1.271 + 0.290*cl 1.272 + 0.290*cl 1.275 + 0.290*cl t phl 17.679 1.572 + 0.322*cl 1.569 + 0.322*cl 1.572 + 0.322*cl t plz 0.958 0.958 + 0.000*cl 0.958 + 0.000*cl 0.958 + 0.000*cl t phz 0.662 0.662 + 0.000*cl 0.662 + 0.000*cl 0.662 + 0.000*cl en to pad t r 31.508 1.210 + 0.606*cl 1.212 + 0.606*cl 1.209 + 0.606*cl t f 33.274 1.277 + 0.640*cl 1.276 + 0.640*cl 1.276 + 0.640*cl t plh 15.882 1.375 + 0.290*cl 1.374 + 0.290*cl 1.377 + 0.290*cl t phl 17.782 1.675 + 0.322*cl 1.674 + 0.322*cl 1.671 + 0.322*cl t plz 1.000 1.000 + 0.000*cl 1.000 + 0.000*cl 1.000 + 0.000*cl t phz 0.705 0.705 + 0.000*cl 0.705 + 0.000*cl 0.705 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 15.772 0.624 + 0.303*cl 0.622 + 0.303*cl 0.625 + 0.303*cl t f 18.210 0.685 + 0.351*cl 0.688 + 0.350*cl 0.685 + 0.350*cl t plh 8.290 1.036 + 0.145*cl 1.037 + 0.145*cl 1.035 + 0.145*cl t phl 10.194 1.074 + 0.182*cl 1.076 + 0.182*cl 1.073 + 0.182*cl tn to pad t r 15.772 0.624 + 0.303*cl 0.622 + 0.303*cl 0.625 + 0.303*cl t f 18.210 0.685 + 0.351*cl 0.688 + 0.350*cl 0.685 + 0.350*cl t plh 8.337 1.083 + 0.145*cl 1.083 + 0.145*cl 1.083 + 0.145*cl t phl 10.317 1.197 + 0.182*cl 1.197 + 0.182*cl 1.200 + 0.182*cl t plz 0.808 0.808 + 0.000*cl 0.808 + 0.000*cl 0.808 + 0.000*cl t phz 0.768 0.768 + 0.000*cl 0.768 + 0.000*cl 0.768 + 0.000*cl en to pad t r 15.772 0.624 + 0.303*cl 0.622 + 0.303*cl 0.625 + 0.303*cl t f 18.210 0.685 + 0.351*cl 0.688 + 0.350*cl 0.685 + 0.350*cl t plh 8.440 1.186 + 0.145*cl 1.187 + 0.145*cl 1.185 + 0.145*cl t phl 10.420 1.300 + 0.182*cl 1.302 + 0.182*cl 1.299 + 0.182*cl t plz 0.851 0.851 + 0.000*cl 0.851 + 0.000*cl 0.851 + 0.000*cl t phz 0.810 0.810 + 0.000*cl 0.810 + 0.000*cl 0.810 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-41 STD111 pvotyz tri-state output buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load[pf]) pot4 pot6 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 7.917 0.348 + 0.151*cl 0.342 + 0.151*cl 0.343 + 0.151*cl t f 9.121 0.359 + 0.175*cl 0.359 + 0.175*cl 0.359 + 0.175*cl t plh 4.724 1.097 + 0.073*cl 1.097 + 0.073*cl 1.097 + 0.073*cl t phl 5.527 0.969 + 0.091*cl 0.968 + 0.091*cl 0.969 + 0.091*cl tn to pad t r 7.917 0.348 + 0.151*cl 0.342 + 0.151*cl 0.343 + 0.151*cl t f 9.121 0.359 + 0.175*cl 0.359 + 0.175*cl 0.359 + 0.175*cl t plh 4.772 1.144 + 0.073*cl 1.144 + 0.073*cl 1.145 + 0.073*cl t phl 5.649 1.088 + 0.091*cl 1.089 + 0.091*cl 1.090 + 0.091*cl t plz 0.940 0.940 + 0.000*cl 0.940 + 0.000*cl 0.940 + 0.000*cl t phz 0.978 0.978 + 0.000*cl 0.978 + 0.000*cl 0.978 + 0.000*cl en to pad t r 7.917 0.348 + 0.151*cl 0.342 + 0.151*cl 0.343 + 0.151*cl t f 9.121 0.359 + 0.175*cl 0.359 + 0.175*cl 0.359 + 0.175*cl t plh 4.874 1.247 + 0.073*cl 1.247 + 0.073*cl 1.247 + 0.073*cl t phl 5.752 1.192 + 0.091*cl 1.192 + 0.091*cl 1.191 + 0.091*cl t plz 0.982 0.982 + 0.000*cl 0.982 + 0.000*cl 0.982 + 0.000*cl t phz 1.020 1.020 + 0.000*cl 1.020 + 0.000*cl 1.020 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 5.317 0.309 + 0.100*cl 0.280 + 0.101*cl 0.265 + 0.101*cl t f 6.097 0.261 + 0.117*cl 0.256 + 0.117*cl 0.256 + 0.117*cl t plh 3.660 1.240 + 0.048*cl 1.241 + 0.048*cl 1.242 + 0.048*cl t phl 4.024 0.989 + 0.061*cl 0.986 + 0.061*cl 0.985 + 0.061*cl tn to pad t r 5.317 0.309 + 0.100*cl 0.280 + 0.101*cl 0.265 + 0.101*cl t f 6.097 0.260 + 0.117*cl 0.256 + 0.117*cl 0.256 + 0.117*cl t plh 3.708 1.288 + 0.048*cl 1.289 + 0.048*cl 1.289 + 0.048*cl t phl 4.142 1.099 + 0.061*cl 1.101 + 0.061*cl 1.102 + 0.061*cl t plz 1.067 1.067 + 0.000*cl 1.067 + 0.000*cl 1.067 + 0.000*cl t phz 1.188 1.187 + 0.000*cl 1.188 + 0.000*cl 1.188 + 0.000*cl en to pad t r 5.317 0.309 + 0.100*cl 0.280 + 0.101*cl 0.265 + 0.101*cl t f 6.097 0.260 + 0.117*cl 0.256 + 0.117*cl 0.256 + 0.117*cl t plh 3.810 1.391 + 0.048*cl 1.392 + 0.048*cl 1.392 + 0.048*cl t phl 4.245 1.203 + 0.061*cl 1.204 + 0.061*cl 1.205 + 0.061*cl t plz 1.111 1.111 + 0.000*cl 1.111 + 0.000*cl 1.111 + 0.000*cl t phz 1.230 1.230 + 0.000*cl 1.230 + 0.000*cl 1.230 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-42 samsung asic pvotyz tri-state output buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load[pf]) pot8 pot10 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 4.049 0.351 + 0.074*cl 0.303 + 0.075*cl 0.269 + 0.075*cl t f 4.592 0.229 + 0.087*cl 0.216 + 0.088*cl 0.210 + 0.088*cl t plh 3.220 1.401 + 0.036*cl 1.406 + 0.036*cl 1.407 + 0.036*cl t phl 3.313 1.044 + 0.045*cl 1.038 + 0.045*cl 1.035 + 0.046*cl tn to pad t r 4.049 0.351 + 0.074*cl 0.303 + 0.075*cl 0.269 + 0.075*cl t f 4.591 0.227 + 0.087*cl 0.214 + 0.088*cl 0.209 + 0.088*cl t plh 3.268 1.448 + 0.036*cl 1.453 + 0.036*cl 1.454 + 0.036*cl t phl 3.424 1.140 + 0.046*cl 1.143 + 0.046*cl 1.144 + 0.046*cl t plz 1.195 1.195 + 0.000*cl 1.195 + 0.000*cl 1.195 + 0.000*cl t phz 1.397 1.397 + 0.000*cl 1.397 + 0.000*cl 1.397 + 0.000*cl en to pad t r 4.049 0.351 + 0.074*cl 0.303 + 0.075*cl 0.269 + 0.075*cl t f 4.591 0.227 + 0.087*cl 0.214 + 0.088*cl 0.209 + 0.088*cl t plh 3.371 1.552 + 0.036*cl 1.556 + 0.036*cl 1.557 + 0.036*cl t phl 3.527 1.243 + 0.046*cl 1.245 + 0.046*cl 1.247 + 0.046*cl t plz 1.238 1.238 + 0.000*cl 1.238 + 0.000*cl 1.238 + 0.000*cl t phz 1.439 1.439 + 0.000*cl 1.439 + 0.000*cl 1.439 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 3.219 0.240 + 0.060*cl 0.210 + 0.060*cl 0.190 + 0.060*cl t f 3.669 0.176 + 0.070*cl 0.166 + 0.070*cl 0.164 + 0.070*cl t plh 2.653 1.200 + 0.029*cl 1.201 + 0.029*cl 1.202 + 0.029*cl t phl 2.807 0.985 + 0.036*cl 0.984 + 0.036*cl 0.983 + 0.036*cl tn to pad t r 3.218 0.240 + 0.060*cl 0.209 + 0.060*cl 0.191 + 0.060*cl t f 3.668 0.174 + 0.070*cl 0.166 + 0.070*cl 0.163 + 0.070*cl t plh 2.704 1.250 + 0.029*cl 1.253 + 0.029*cl 1.253 + 0.029*cl t phl 2.925 1.097 + 0.037*cl 1.099 + 0.037*cl 1.100 + 0.036*cl t plz 1.095 1.095 + 0.000*cl 1.095 + 0.000*cl 1.095 + 0.000*cl t phz 1.144 1.144 + 0.000*cl 1.143 + 0.000*cl 1.144 + 0.000*cl en to pad t r 3.218 0.240 + 0.060*cl 0.209 + 0.060*cl 0.191 + 0.060*cl t f 3.668 0.174 + 0.070*cl 0.166 + 0.070*cl 0.163 + 0.070*cl t plh 2.807 1.354 + 0.029*cl 1.355 + 0.029*cl 1.356 + 0.029*cl t phl 3.027 1.201 + 0.037*cl 1.202 + 0.036*cl 1.203 + 0.036*cl t plz 1.138 1.138 + 0.000*cl 1.138 + 0.000*cl 1.138 + 0.000*cl t phz 1.186 1.185 + 0.000*cl 1.186 + 0.000*cl 1.186 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-43 STD111 pvotyz tri-state output buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load[pf]) pot12 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 2.721 0.269 + 0.049*cl 0.232 + 0.050*cl 0.204 + 0.050*cl t f 3.069 0.169 + 0.058*cl 0.155 + 0.058*cl 0.148 + 0.058*cl t plh 2.497 1.281 + 0.024*cl 1.286 + 0.024*cl 1.287 + 0.024*cl t phl 2.531 1.016 + 0.030*cl 1.014 + 0.030*cl 1.012 + 0.030*cl tn to pad t r 2.721 0.269 + 0.049*cl 0.232 + 0.050*cl 0.204 + 0.050*cl t f 3.069 0.167 + 0.058*cl 0.154 + 0.058*cl 0.147 + 0.058*cl t plh 2.548 1.332 + 0.024*cl 1.338 + 0.024*cl 1.339 + 0.024*cl t phl 2.646 1.122 + 0.030*cl 1.125 + 0.030*cl 1.126 + 0.030*cl t plz 1.160 1.160 + 0.000*cl 1.160 + 0.000*cl 1.160 + 0.000*cl t phz 1.248 1.248 + 0.000*cl 1.248 + 0.000*cl 1.248 + 0.000*cl en to pad t r 2.721 0.269 + 0.049*cl 0.232 + 0.050*cl 0.204 + 0.050*cl t f 3.069 0.167 + 0.058*cl 0.154 + 0.058*cl 0.147 + 0.058*cl t plh 2.651 1.435 + 0.024*cl 1.440 + 0.024*cl 1.442 + 0.024*cl t phl 2.749 1.225 + 0.030*cl 1.228 + 0.030*cl 1.229 + 0.030*cl t plz 1.203 1.203 + 0.000*cl 1.203 + 0.000*cl 1.203 + 0.000*cl t phz 1.290 1.290 + 0.000*cl 1.290 + 0.000*cl 1.290 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-44 samsung asic pvotyz tri-state output buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load[pf]) pot4sm pot6sm path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 8.136 0.756 + 0.148*cl 0.663 + 0.149*cl 0.590 + 0.150*cl t f 9.485 1.005 + 0.170*cl 0.893 + 0.172*cl 0.791 + 0.173*cl t plh 5.943 2.288 + 0.073*cl 2.310 + 0.073*cl 2.315 + 0.073*cl t phl 7.625 2.988 + 0.093*cl 3.050 + 0.092*cl 3.069 + 0.091*cl tn to pad t r 8.136 0.756 + 0.148*cl 0.663 + 0.149*cl 0.590 + 0.150*cl t f 9.485 1.005 + 0.170*cl 0.893 + 0.172*cl 0.791 + 0.173*cl t plh 5.992 2.336 + 0.073*cl 2.358 + 0.073*cl 2.364 + 0.073*cl t phl 7.747 3.110 + 0.093*cl 3.171 + 0.092*cl 3.189 + 0.091*cl t plz 1.169 1.169 + 0.000*cl 1.169 + 0.000*cl 1.169 + 0.000*cl t phz 1.521 1.521 + 0.000*cl 1.521 + 0.000*cl 1.521 + 0.000*cl en to pad t r 8.136 0.756 + 0.148*cl 0.663 + 0.149*cl 0.590 + 0.150*cl t f 9.485 1.005 + 0.170*cl 0.893 + 0.172*cl 0.791 + 0.173*cl t plh 6.094 2.439 + 0.073*cl 2.461 + 0.073*cl 2.466 + 0.073*cl t phl 7.850 3.213 + 0.093*cl 3.275 + 0.091*cl 3.291 + 0.091*cl t plz 1.212 1.212 + 0.000*cl 1.212 + 0.000*cl 1.212 + 0.000*cl t phz 1.563 1.563 + 0.000*cl 1.563 + 0.000*cl 1.563 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 6.049 1.312 + 0.095*cl 1.251 + 0.096*cl 1.155 + 0.097*cl t f 6.982 1.450 + 0.111*cl 1.413 + 0.111*cl 1.321 + 0.113*cl t plh 5.589 2.881 + 0.054*cl 3.063 + 0.051*cl 3.165 + 0.049*cl t phl 6.936 3.524 + 0.068*cl 3.747 + 0.064*cl 3.882 + 0.062*cl tn to pad t r 6.049 1.312 + 0.095*cl 1.252 + 0.096*cl 1.155 + 0.097*cl t f 6.982 1.451 + 0.111*cl 1.414 + 0.111*cl 1.322 + 0.113*cl t plh 5.638 2.930 + 0.054*cl 3.112 + 0.051*cl 3.214 + 0.049*cl t phl 7.057 3.645 + 0.068*cl 3.868 + 0.064*cl 4.002 + 0.062*cl t plz 1.448 1.448 + 0.000*cl 1.448 + 0.000*cl 1.448 + 0.000*cl t phz 2.401 2.401 + 0.000*cl 2.401 + 0.000*cl 2.400 + 0.000*cl en to pad t r 6.049 1.312 + 0.095*cl 1.252 + 0.096*cl 1.155 + 0.097*cl t f 6.982 1.451 + 0.111*cl 1.414 + 0.111*cl 1.322 + 0.113*cl t plh 5.740 3.034 + 0.054*cl 3.215 + 0.051*cl 3.316 + 0.049*cl t phl 7.160 3.748 + 0.068*cl 3.971 + 0.064*cl 4.106 + 0.062*cl t plz 1.491 1.491 + 0.000*cl 1.491 + 0.000*cl 1.491 + 0.000*cl t phz 2.443 2.442 + 0.000*cl 2.443 + 0.000*cl 2.443 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-45 STD111 pvotyz tri-state output buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load[pf]) pot8sm pot10sm path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 5.157 1.658 + 0.070*cl 1.671 + 0.070*cl 1.601 + 0.071*cl t f 5.712 1.575 + 0.083*cl 1.605 + 0.082*cl 1.549 + 0.083*cl t plh 5.234 2.895 + 0.047*cl 3.178 + 0.041*cl 3.371 + 0.039*cl t phl 6.241 3.455 + 0.056*cl 3.724 + 0.050*cl 3.913 + 0.048*cl tn to pad t r 5.158 1.661 + 0.070*cl 1.673 + 0.070*cl 1.602 + 0.071*cl t f 5.723 1.615 + 0.082*cl 1.625 + 0.082*cl 1.561 + 0.083*cl t plh 5.282 2.942 + 0.047*cl 3.226 + 0.041*cl 3.419 + 0.039*cl t phl 6.351 3.546 + 0.056*cl 3.827 + 0.050*cl 4.021 + 0.048*cl t plz 2.053 2.053 + 0.000*cl 2.053 + 0.000*cl 2.053 + 0.000*cl t phz 3.255 3.255 + 0.000*cl 3.255 + 0.000*cl 3.255 + 0.000*cl en to pad t r 5.158 1.661 + 0.070*cl 1.673 + 0.070*cl 1.602 + 0.071*cl t f 5.723 1.615 + 0.082*cl 1.625 + 0.082*cl 1.561 + 0.083*cl t plh 5.385 3.046 + 0.047*cl 3.329 + 0.041*cl 3.522 + 0.039*cl t phl 6.454 3.649 + 0.056*cl 3.930 + 0.050*cl 4.125 + 0.048*cl t plz 2.096 2.096 + 0.000*cl 2.096 + 0.000*cl 2.096 + 0.000*cl t phz 3.297 3.297 + 0.000*cl 3.297 + 0.000*cl 3.297 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 4.208 1.327 + 0.058*cl 1.366 + 0.057*cl 1.346 + 0.057*cl t f 4.733 1.366 + 0.067*cl 1.422 + 0.066*cl 1.407 + 0.066*cl t plh 4.875 2.962 + 0.038*cl 3.187 + 0.034*cl 3.355 + 0.032*cl t phl 5.800 3.480 + 0.046*cl 3.724 + 0.042*cl 3.905 + 0.039*cl tn to pad t r 4.208 1.327 + 0.058*cl 1.366 + 0.057*cl 1.346 + 0.057*cl t f 4.736 1.381 + 0.067*cl 1.430 + 0.066*cl 1.412 + 0.066*cl t plh 4.924 3.012 + 0.038*cl 3.236 + 0.034*cl 3.404 + 0.032*cl t phl 5.917 3.591 + 0.047*cl 3.839 + 0.042*cl 4.023 + 0.039*cl t plz 2.053 2.053 + 0.000*cl 2.053 + 0.000*cl 2.053 + 0.000*cl t phz 3.255 3.254 + 0.000*cl 3.255 + 0.000*cl 3.255 + 0.000*cl en to pad t r 4.208 1.327 + 0.058*cl 1.366 + 0.057*cl 1.346 + 0.057*cl t f 4.736 1.381 + 0.067*cl 1.430 + 0.066*cl 1.412 + 0.066*cl t plh 5.027 3.115 + 0.038*cl 3.339 + 0.034*cl 3.507 + 0.032*cl t phl 6.020 3.694 + 0.047*cl 3.942 + 0.042*cl 4.126 + 0.039*cl t plz 2.095 2.096 + 0.000*cl 2.095 + 0.000*cl 2.095 + 0.000*cl t phz 3.297 3.297 + 0.000*cl 3.297 + 0.000*cl 3.297 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-46 samsung asic pvotyz tri-state output buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load[pf]) pot12sm path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 4.196 1.635 + 0.051*cl 1.781 + 0.048*cl 1.853 + 0.047*cl t f 4.558 1.568 + 0.060*cl 1.742 + 0.056*cl 1.824 + 0.055*cl t plh 5.110 3.154 + 0.039*cl 3.458 + 0.033*cl 3.713 + 0.030*cl t phl 5.995 3.754 + 0.045*cl 4.049 + 0.039*cl 4.298 + 0.036*cl tn to pad t r 4.196 1.637 + 0.051*cl 1.781 + 0.048*cl 1.854 + 0.047*cl t f 4.583 1.655 + 0.059*cl 1.791 + 0.056*cl 1.853 + 0.055*cl t plh 5.159 3.203 + 0.039*cl 3.507 + 0.033*cl 3.763 + 0.030*cl t phl 6.095 3.815 + 0.046*cl 4.134 + 0.039*cl 4.395 + 0.036*cl t plz 2.421 2.421 + 0.000*cl 2.421 + 0.000*cl 2.421 + 0.000*cl t phz 4.133 4.133 + 0.000*cl 4.133 + 0.000*cl 4.133 + 0.000*cl en to pad t r 4.196 1.637 + 0.051*cl 1.782 + 0.048*cl 1.854 + 0.047*cl t f 4.583 1.655 + 0.059*cl 1.790 + 0.056*cl 1.854 + 0.055*cl t plh 5.261 3.307 + 0.039*cl 3.610 + 0.033*cl 3.865 + 0.030*cl t phl 6.197 3.918 + 0.046*cl 4.236 + 0.039*cl 4.498 + 0.036*cl t plz 2.464 2.464 + 0.000*cl 2.464 + 0.000*cl 2.464 + 0.000*cl t phz 4.175 4.175 + 0.000*cl 4.175 + 0.000*cl 4.175 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-47 STD111 pvotyz tri-state output buffers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load[pf]) pot10sh pot12sh path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 6.218 2.940 + 0.066*cl 3.224 + 0.060*cl 3.412 + 0.057*cl t f 6.448 2.737 + 0.074*cl 3.005 + 0.069*cl 3.175 + 0.067*cl t plh 7.876 4.948 + 0.059*cl 5.499 + 0.048*cl 5.966 + 0.041*cl t phl 8.633 5.417 + 0.064*cl 5.943 + 0.054*cl 6.389 + 0.048*cl tn to pad t r 6.219 2.942 + 0.066*cl 3.225 + 0.060*cl 3.414 + 0.057*cl t f 6.460 2.782 + 0.074*cl 3.029 + 0.069*cl 3.189 + 0.066*cl t plh 7.929 5.001 + 0.059*cl 5.553 + 0.048*cl 6.019 + 0.041*cl t phl 8.748 5.516 + 0.065*cl 6.051 + 0.054*cl 6.505 + 0.048*cl t plz 2.532 2.532 + 0.000*cl 2.532 + 0.000*cl 2.532 + 0.000*cl t phz 4.231 4.230 + 0.000*cl 4.231 + 0.000*cl 4.231 + 0.000*cl en to pad t r 6.219 2.942 + 0.066*cl 3.226 + 0.060*cl 3.413 + 0.057*cl t f 6.460 2.782 + 0.074*cl 3.029 + 0.069*cl 3.189 + 0.066*cl t plh 8.031 5.105 + 0.059*cl 5.655 + 0.048*cl 6.122 + 0.041*cl t phl 8.850 5.620 + 0.065*cl 6.155 + 0.054*cl 6.607 + 0.048*cl t plz 2.575 2.575 + 0.000*cl 2.575 + 0.000*cl 2.575 + 0.000*cl t phz 4.273 4.272 + 0.000*cl 4.273 + 0.000*cl 4.273 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 6.593 3.555 + 0.061*cl 3.937 + 0.053*cl 4.211 + 0.049*cl t f 6.548 3.126 + 0.068*cl 3.509 + 0.061*cl 3.773 + 0.057*cl t plh 8.385 5.248 + 0.063*cl 5.928 + 0.049*cl 6.505 + 0.041*cl t phl 9.094 5.840 + 0.065*cl 6.443 + 0.053*cl 6.966 + 0.046*cl tn to pad t r 6.596 3.560 + 0.061*cl 3.941 + 0.053*cl 4.213 + 0.049*cl t f 6.599 3.299 + 0.066*cl 3.606 + 0.060*cl 3.832 + 0.057*cl t plh 8.439 5.302 + 0.063*cl 5.982 + 0.049*cl 6.558 + 0.041*cl t phl 9.189 5.880 + 0.066*cl 6.518 + 0.053*cl 7.056 + 0.046*cl t plz 2.900 2.900 + 0.000*cl 2.900 + 0.000*cl 2.900 + 0.000*cl t phz 5.109 5.108 + 0.000*cl 5.109 + 0.000*cl 5.109 + 0.000*cl en to pad t r 6.596 3.560 + 0.061*cl 3.941 + 0.053*cl 4.214 + 0.049*cl t f 6.599 3.299 + 0.066*cl 3.606 + 0.060*cl 3.832 + 0.057*cl t plh 8.541 5.405 + 0.063*cl 6.085 + 0.049*cl 6.661 + 0.041*cl t phl 9.291 5.983 + 0.066*cl 6.620 + 0.053*cl 7.159 + 0.046*cl t plz 2.943 2.943 + 0.000*cl 2.943 + 0.000*cl 2.943 + 0.000*cl t phz 5.151 5.150 + 0.000*cl 5.150 + 0.000*cl 5.151 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-48 samsung asic pvotyz tri-state output buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 0.17ns, cl: capacitive load[pf]) phot1 phot2 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 42.148 1.623 + 0.811*cl 1.624 + 0.810*cl 1.621 + 0.811*cl t f 33.014 1.269 + 0.635*cl 1.270 + 0.635*cl 1.267 + 0.635*cl t plh 20.296 1.549 + 0.375*cl 1.548 + 0.375*cl 1.548 + 0.375*cl t phl 17.148 1.586 + 0.311*cl 1.584 + 0.311*cl 1.581 + 0.311*cl tn to pad t r 42.146 1.623 + 0.810*cl 1.620 + 0.811*cl 1.623 + 0.810*cl t f 33.014 1.269 + 0.635*cl 1.270 + 0.635*cl 1.267 + 0.635*cl t plh 20.383 1.633 + 0.375*cl 1.635 + 0.375*cl 1.635 + 0.375*cl t phl 17.350 1.785 + 0.311*cl 1.786 + 0.311*cl 1.783 + 0.311*cl t plz 1.249 1.249 + 0.000*cl 1.249 + 0.000*cl 1.249 + 0.000*cl t phz 0.951 0.951 + 0.000*cl 0.951 + 0.000*cl 0.951 + 0.000*cl en to pad t r 42.146 1.623 + 0.810*cl 1.620 + 0.811*cl 1.623 + 0.810*cl t f 33.014 1.269 + 0.635*cl 1.270 + 0.635*cl 1.267 + 0.635*cl t plh 20.485 1.738 + 0.375*cl 1.737 + 0.375*cl 1.737 + 0.375*cl t phl 17.453 1.888 + 0.311*cl 1.889 + 0.311*cl 1.889 + 0.311*cl t plz 1.292 1.292 + 0.000*cl 1.292 + 0.000*cl 1.292 + 0.000*cl t phz 0.995 0.995 + 0.000*cl 0.995 + 0.000*cl 0.995 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 21.098 0.836 + 0.405*cl 0.836 + 0.405*cl 0.833 + 0.405*cl t f 18.188 0.706 + 0.350*cl 0.702 + 0.350*cl 0.705 + 0.350*cl t plh 10.592 1.218 + 0.187*cl 1.218 + 0.187*cl 1.218 + 0.187*cl t phl 10.105 1.209 + 0.178*cl 1.211 + 0.178*cl 1.208 + 0.178*cl tn to pad t r 21.098 0.836 + 0.405*cl 0.836 + 0.405*cl 0.833 + 0.405*cl t f 18.188 0.706 + 0.350*cl 0.702 + 0.350*cl 0.705 + 0.350*cl t plh 10.678 1.304 + 0.187*cl 1.304 + 0.187*cl 1.304 + 0.187*cl t phl 10.306 1.411 + 0.178*cl 1.410 + 0.178*cl 1.410 + 0.178*cl t plz 1.104 1.104 + 0.000*cl 1.104 + 0.000*cl 1.104 + 0.000*cl t phz 0.998 0.998 + 0.000*cl 0.998 + 0.000*cl 0.998 + 0.000*cl en to pad t r 21.098 0.836 + 0.405*cl 0.836 + 0.405*cl 0.833 + 0.405*cl t f 18.188 0.706 + 0.350*cl 0.702 + 0.350*cl 0.705 + 0.350*cl t plh 10.781 1.406 + 0.187*cl 1.407 + 0.187*cl 1.410 + 0.187*cl t phl 10.409 1.513 + 0.178*cl 1.513 + 0.178*cl 1.516 + 0.178*cl t plz 1.149 1.149 + 0.000*cl 1.149 + 0.000*cl 1.149 + 0.000*cl t phz 1.042 1.042 + 0.000*cl 1.042 + 0.000*cl 1.042 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-49 STD111 pvotyz tri-state output buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 0.17ns, cl: capacitive load[pf]) phot4 phot6 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 10.563 0.433 + 0.203*cl 0.431 + 0.203*cl 0.431 + 0.203*cl t f 9.114 0.371 + 0.175*cl 0.371 + 0.175*cl 0.372 + 0.175*cl t plh 5.815 1.128 + 0.094*cl 1.128 + 0.094*cl 1.128 + 0.094*cl t phl 5.544 1.096 + 0.089*cl 1.096 + 0.089*cl 1.096 + 0.089*cl tn to pad t r 10.563 0.433 + 0.203*cl 0.431 + 0.203*cl 0.431 + 0.203*cl t f 9.114 0.371 + 0.175*cl 0.371 + 0.175*cl 0.372 + 0.175*cl t plh 5.901 1.213 + 0.094*cl 1.214 + 0.094*cl 1.215 + 0.094*cl t phl 5.746 1.297 + 0.089*cl 1.297 + 0.089*cl 1.298 + 0.089*cl t plz 1.255 1.256 + 0.000*cl 1.255 + 0.000*cl 1.255 + 0.000*cl t phz 1.091 1.091 + 0.000*cl 1.091 + 0.000*cl 1.091 + 0.000*cl en to pad t r 10.563 0.433 + 0.203*cl 0.431 + 0.203*cl 0.431 + 0.203*cl t f 9.114 0.371 + 0.175*cl 0.371 + 0.175*cl 0.372 + 0.175*cl t plh 6.003 1.316 + 0.094*cl 1.317 + 0.094*cl 1.318 + 0.094*cl t phl 5.848 1.400 + 0.089*cl 1.401 + 0.089*cl 1.401 + 0.089*cl t plz 1.300 1.300 + 0.000*cl 1.300 + 0.000*cl 1.300 + 0.000*cl t phz 1.135 1.135 + 0.000*cl 1.135 + 0.000*cl 1.135 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 7.047 0.293 + 0.135*cl 0.294 + 0.135*cl 0.293 + 0.135*cl t f 6.082 0.254 + 0.117*cl 0.254 + 0.117*cl 0.255 + 0.117*cl t plh 4.212 1.087 + 0.063*cl 1.087 + 0.062*cl 1.087 + 0.062*cl t phl 4.022 1.057 + 0.059*cl 1.057 + 0.059*cl 1.057 + 0.059*cl tn to pad t r 7.047 0.293 + 0.135*cl 0.294 + 0.135*cl 0.293 + 0.135*cl t f 6.082 0.254 + 0.117*cl 0.254 + 0.117*cl 0.255 + 0.117*cl t plh 4.298 1.172 + 0.063*cl 1.173 + 0.063*cl 1.173 + 0.063*cl t phl 4.223 1.256 + 0.059*cl 1.257 + 0.059*cl 1.257 + 0.059*cl t plz 1.246 1.246 + 0.000*cl 1.246 + 0.000*cl 1.246 + 0.000*cl t phz 1.094 1.094 + 0.000*cl 1.094 + 0.000*cl 1.094 + 0.000*cl en to pad t r 7.047 0.293 + 0.135*cl 0.294 + 0.135*cl 0.293 + 0.135*cl t f 6.082 0.254 + 0.117*cl 0.254 + 0.117*cl 0.255 + 0.117*cl t plh 4.400 1.275 + 0.063*cl 1.276 + 0.062*cl 1.276 + 0.062*cl t phl 4.325 1.359 + 0.059*cl 1.360 + 0.059*cl 1.359 + 0.059*cl t plz 1.289 1.290 + 0.000*cl 1.289 + 0.000*cl 1.289 + 0.000*cl t phz 1.137 1.137 + 0.000*cl 1.137 + 0.000*cl 1.137 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-50 samsung asic pvotyz tri-state output buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 0.17ns, cl: capacitive load[pf]) phot8 phot10 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 5.293 0.229 + 0.101*cl 0.228 + 0.101*cl 0.227 + 0.101*cl t f 4.572 0.205 + 0.087*cl 0.202 + 0.087*cl 0.201 + 0.087*cl t plh 3.444 1.100 + 0.047*cl 1.101 + 0.047*cl 1.101 + 0.047*cl t phl 3.289 1.064 + 0.044*cl 1.065 + 0.044*cl 1.065 + 0.044*cl tn to pad t r 5.293 0.229 + 0.101*cl 0.228 + 0.101*cl 0.227 + 0.101*cl t f 4.572 0.205 + 0.087*cl 0.202 + 0.087*cl 0.201 + 0.087*cl t plh 3.530 1.185 + 0.047*cl 1.186 + 0.047*cl 1.186 + 0.047*cl t phl 3.489 1.263 + 0.045*cl 1.264 + 0.044*cl 1.265 + 0.044*cl t plz 1.322 1.322 + 0.000*cl 1.322 + 0.000*cl 1.322 + 0.000*cl t phz 1.140 1.140 + 0.000*cl 1.140 + 0.000*cl 1.140 + 0.000*cl en to pad t r 5.293 0.229 + 0.101*cl 0.228 + 0.101*cl 0.227 + 0.101*cl t f 4.572 0.205 + 0.087*cl 0.202 + 0.087*cl 0.201 + 0.087*cl t plh 3.632 1.288 + 0.047*cl 1.288 + 0.047*cl 1.289 + 0.047*cl t phl 3.591 1.367 + 0.044*cl 1.367 + 0.044*cl 1.367 + 0.044*cl t plz 1.366 1.366 + 0.000*cl 1.366 + 0.000*cl 1.366 + 0.000*cl t phz 1.184 1.184 + 0.000*cl 1.184 + 0.000*cl 1.184 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 4.242 0.194 + 0.081*cl 0.191 + 0.081*cl 0.190 + 0.081*cl t f 3.669 0.183 + 0.070*cl 0.175 + 0.070*cl 0.172 + 0.070*cl t plh 3.000 1.124 + 0.038*cl 1.125 + 0.037*cl 1.125 + 0.037*cl t phl 2.863 1.083 + 0.036*cl 1.084 + 0.036*cl 1.084 + 0.036*cl tn to pad t r 4.242 0.194 + 0.081*cl 0.191 + 0.081*cl 0.190 + 0.081*cl t f 3.669 0.183 + 0.070*cl 0.175 + 0.070*cl 0.172 + 0.070*cl t plh 3.085 1.208 + 0.038*cl 1.209 + 0.038*cl 1.210 + 0.038*cl t phl 3.063 1.282 + 0.036*cl 1.283 + 0.036*cl 1.284 + 0.036*cl t plz 1.397 1.397 + 0.000*cl 1.397 + 0.000*cl 1.397 + 0.000*cl t phz 1.186 1.186 + 0.000*cl 1.186 + 0.000*cl 1.186 + 0.000*cl en to pad t r 4.242 0.195 + 0.081*cl 0.190 + 0.081*cl 0.190 + 0.081*cl t f 3.669 0.183 + 0.070*cl 0.175 + 0.070*cl 0.172 + 0.070*cl t plh 3.188 1.311 + 0.038*cl 1.312 + 0.038*cl 1.313 + 0.037*cl t phl 3.166 1.386 + 0.036*cl 1.386 + 0.036*cl 1.387 + 0.036*cl t plz 1.441 1.441 + 0.000*cl 1.441 + 0.000*cl 1.441 + 0.000*cl t phz 1.230 1.230 + 0.000*cl 1.230 + 0.000*cl 1.230 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-51 STD111 pvotyz tri-state output buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 0.17ns, cl: capacitive load[pf]) phot12 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 3.544 0.178 + 0.067*cl 0.169 + 0.067*cl 0.166 + 0.068*cl t f 3.071 0.176 + 0.058*cl 0.163 + 0.058*cl 0.156 + 0.058*cl t plh 2.717 1.154 + 0.031*cl 1.154 + 0.031*cl 1.154 + 0.031*cl t phl 2.592 1.108 + 0.030*cl 1.109 + 0.030*cl 1.109 + 0.030*cl tn to pad t r 3.544 0.178 + 0.067*cl 0.169 + 0.067*cl 0.166 + 0.068*cl t f 3.071 0.176 + 0.058*cl 0.163 + 0.058*cl 0.156 + 0.058*cl t plh 2.802 1.236 + 0.031*cl 1.238 + 0.031*cl 1.239 + 0.031*cl t phl 2.792 1.307 + 0.030*cl 1.308 + 0.030*cl 1.309 + 0.030*cl t plz 1.471 1.472 + 0.000*cl 1.471 + 0.000*cl 1.471 + 0.000*cl t phz 1.232 1.232 + 0.000*cl 1.232 + 0.000*cl 1.232 + 0.000*cl en to pad t r 3.544 0.178 + 0.067*cl 0.169 + 0.067*cl 0.166 + 0.068*cl t f 3.071 0.176 + 0.058*cl 0.163 + 0.058*cl 0.156 + 0.058*cl t plh 2.904 1.340 + 0.031*cl 1.341 + 0.031*cl 1.341 + 0.031*cl t phl 2.894 1.410 + 0.030*cl 1.411 + 0.030*cl 1.411 + 0.030*cl t plz 1.515 1.516 + 0.000*cl 1.515 + 0.000*cl 1.515 + 0.000*cl t phz 1.276 1.276 + 0.000*cl 1.276 + 0.000*cl 1.276 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-52 samsung asic pvotyz tri-state output buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 0.17ns, cl: capacitive load[pf]) phot4sm phot6sm path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 10.608 0.513 + 0.202*cl 0.486 + 0.202*cl 0.477 + 0.203*cl t f 9.436 0.949 + 0.170*cl 0.845 + 0.172*cl 0.747 + 0.173*cl t plh 6.340 1.651 + 0.094*cl 1.652 + 0.094*cl 1.653 + 0.094*cl t phl 7.303 2.794 + 0.090*cl 2.843 + 0.089*cl 2.855 + 0.089*cl tn to pad t r 10.608 0.513 + 0.202*cl 0.486 + 0.202*cl 0.477 + 0.203*cl t f 9.436 0.949 + 0.170*cl 0.845 + 0.172*cl 0.747 + 0.173*cl t plh 6.426 1.736 + 0.094*cl 1.738 + 0.094*cl 1.739 + 0.094*cl t phl 7.503 2.993 + 0.090*cl 3.043 + 0.089*cl 3.057 + 0.089*cl t plz 1.417 1.417 + 0.000*cl 1.417 + 0.000*cl 1.417 + 0.000*cl t phz 1.355 1.355 + 0.000*cl 1.355 + 0.000*cl 1.355 + 0.000*cl en to pad t r 10.608 0.513 + 0.202*cl 0.486 + 0.202*cl 0.477 + 0.203*cl t f 9.436 0.949 + 0.170*cl 0.845 + 0.172*cl 0.747 + 0.173*cl t plh 6.529 1.840 + 0.094*cl 1.841 + 0.094*cl 1.842 + 0.094*cl t phl 7.606 3.097 + 0.090*cl 3.146 + 0.089*cl 3.160 + 0.089*cl t plz 1.461 1.461 + 0.000*cl 1.461 + 0.000*cl 1.460 + 0.000*cl t phz 1.399 1.399 + 0.000*cl 1.399 + 0.000*cl 1.399 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 7.208 0.611 + 0.132*cl 0.535 + 0.133*cl 0.477 + 0.134*cl t f 6.913 1.361 + 0.111*cl 1.333 + 0.112*cl 1.254 + 0.113*cl t plh 5.098 1.955 + 0.063*cl 1.969 + 0.063*cl 1.973 + 0.063*cl t phl 6.581 3.267 + 0.066*cl 3.476 + 0.062*cl 3.603 + 0.060*cl tn to pad t r 7.208 0.611 + 0.132*cl 0.535 + 0.133*cl 0.477 + 0.134*cl t f 6.914 1.361 + 0.111*cl 1.334 + 0.112*cl 1.251 + 0.113*cl t plh 5.184 2.040 + 0.063*cl 2.056 + 0.063*cl 2.059 + 0.063*cl t phl 6.781 3.468 + 0.066*cl 3.677 + 0.062*cl 3.803 + 0.060*cl t plz 1.724 1.724 + 0.000*cl 1.724 + 0.000*cl 1.724 + 0.000*cl t phz 1.742 1.742 + 0.000*cl 1.742 + 0.000*cl 1.742 + 0.000*cl en to pad t r 7.208 0.611 + 0.132*cl 0.535 + 0.133*cl 0.477 + 0.134*cl t f 6.914 1.361 + 0.111*cl 1.334 + 0.112*cl 1.251 + 0.113*cl t plh 5.287 2.144 + 0.063*cl 2.158 + 0.063*cl 2.162 + 0.063*cl t phl 6.884 3.571 + 0.066*cl 3.779 + 0.062*cl 3.906 + 0.060*cl t plz 1.768 1.768 + 0.000*cl 1.768 + 0.000*cl 1.768 + 0.000*cl t phz 1.786 1.786 + 0.000*cl 1.786 + 0.000*cl 1.786 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-53 STD111 pvotyz tri-state output buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 0.17ns, cl: capacitive load[pf]) phot8sm phot10sm path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 5.686 0.878 + 0.096*cl 0.794 + 0.098*cl 0.705 + 0.099*cl t f 6.065 1.797 + 0.085*cl 1.914 + 0.083*cl 1.934 + 0.083*cl t plh 4.736 2.280 + 0.049*cl 2.363 + 0.047*cl 2.395 + 0.047*cl t phl 6.607 3.635 + 0.059*cl 3.984 + 0.052*cl 4.255 + 0.049*cl tn to pad t r 5.687 0.884 + 0.096*cl 0.796 + 0.098*cl 0.707 + 0.099*cl t f 6.065 1.798 + 0.085*cl 1.915 + 0.083*cl 1.935 + 0.083*cl t plh 4.821 2.363 + 0.049*cl 2.447 + 0.047*cl 2.480 + 0.047*cl t phl 6.807 3.835 + 0.059*cl 4.184 + 0.052*cl 4.454 + 0.049*cl t plz 2.028 2.029 + 0.000*cl 2.028 + 0.000*cl 2.028 + 0.000*cl t phz 2.128 2.128 + 0.000*cl 2.128 + 0.000*cl 2.128 + 0.000*cl en to pad t r 5.687 0.884 + 0.096*cl 0.797 + 0.098*cl 0.707 + 0.099*cl t f 6.065 1.798 + 0.085*cl 1.915 + 0.083*cl 1.935 + 0.083*cl t plh 4.924 2.466 + 0.049*cl 2.550 + 0.047*cl 2.582 + 0.047*cl t phl 6.910 3.939 + 0.059*cl 4.287 + 0.052*cl 4.557 + 0.049*cl t plz 2.072 2.072 + 0.000*cl 2.072 + 0.000*cl 2.072 + 0.000*cl t phz 2.172 2.172 + 0.000*cl 2.172 + 0.000*cl 2.172 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 4.499 0.605 + 0.078*cl 0.551 + 0.079*cl 0.500 + 0.080*cl t f 5.289 1.831 + 0.069*cl 1.980 + 0.066*cl 2.030 + 0.066*cl t plh 3.975 2.054 + 0.038*cl 2.093 + 0.038*cl 2.105 + 0.037*cl t phl 6.063 3.455 + 0.052*cl 3.822 + 0.045*cl 4.115 + 0.041*cl tn to pad t r 4.509 0.633 + 0.078*cl 0.572 + 0.079*cl 0.511 + 0.080*cl t f 5.290 1.834 + 0.069*cl 1.981 + 0.066*cl 2.031 + 0.066*cl t plh 4.038 2.086 + 0.039*cl 2.142 + 0.038*cl 2.163 + 0.038*cl t phl 6.264 3.655 + 0.052*cl 4.022 + 0.045*cl 4.315 + 0.041*cl t plz 2.773 2.774 + 0.000*cl 2.773 + 0.000*cl 2.773 + 0.000*cl t phz 2.109 2.110 + 0.000*cl 2.109 + 0.000*cl 2.109 + 0.000*cl en to pad t r 4.509 0.633 + 0.078*cl 0.572 + 0.079*cl 0.511 + 0.080*cl t f 5.290 1.834 + 0.069*cl 1.981 + 0.066*cl 2.031 + 0.066*cl t plh 4.140 2.189 + 0.039*cl 2.245 + 0.038*cl 2.266 + 0.038*cl t phl 6.366 3.758 + 0.052*cl 4.125 + 0.045*cl 4.418 + 0.041*cl t plz 2.817 2.817 + 0.000*cl 2.817 + 0.000*cl 2.817 + 0.000*cl t phz 2.153 2.153 + 0.000*cl 2.153 + 0.000*cl 2.153 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-54 samsung asic pvotyz tri-state output buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 0.17ns, cl: capacitive load[pf]) phot12sm path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 3.998 0.788 + 0.064*cl 0.767 + 0.065*cl 0.718 + 0.065*cl t f 4.487 1.515 + 0.059*cl 1.662 + 0.057*cl 1.739 + 0.055*cl t plh 3.937 2.211 + 0.035*cl 2.314 + 0.032*cl 2.373 + 0.032*cl t phl 5.635 3.418 + 0.044*cl 3.720 + 0.038*cl 3.971 + 0.035*cl tn to pad t r 4.011 0.830 + 0.064*cl 0.793 + 0.064*cl 0.733 + 0.065*cl t f 4.489 1.518 + 0.059*cl 1.664 + 0.056*cl 1.740 + 0.055*cl t plh 4.005 2.253 + 0.035*cl 2.372 + 0.033*cl 2.438 + 0.032*cl t phl 5.835 3.617 + 0.044*cl 3.920 + 0.038*cl 4.170 + 0.035*cl t plz 2.773 2.774 + 0.000*cl 2.773 + 0.000*cl 2.773 + 0.000*cl t phz 2.495 2.495 + 0.000*cl 2.495 + 0.000*cl 2.495 + 0.000*cl en to pad t r 4.011 0.830 + 0.064*cl 0.793 + 0.064*cl 0.733 + 0.065*cl t f 4.489 1.518 + 0.059*cl 1.664 + 0.056*cl 1.740 + 0.055*cl t plh 4.108 2.356 + 0.035*cl 2.475 + 0.033*cl 2.542 + 0.032*cl t phl 5.938 3.720 + 0.044*cl 4.023 + 0.038*cl 4.274 + 0.035*cl t plz 2.817 2.818 + 0.000*cl 2.817 + 0.000*cl 2.817 + 0.000*cl t phz 2.538 2.539 + 0.000*cl 2.538 + 0.000*cl 2.538 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-55 STD111 pvotyz tri-state output buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 0.17ns, cl: capacitive load[pf]) phot10sh phot12sh path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 5.273 1.448 + 0.077*cl 1.465 + 0.076*cl 1.414 + 0.077*cl t f 6.224 2.449 + 0.075*cl 2.727 + 0.070*cl 2.915 + 0.067*cl t plh 5.546 3.210 + 0.047*cl 3.452 + 0.042*cl 3.622 + 0.040*cl t phl 7.875 4.751 + 0.062*cl 5.253 + 0.052*cl 5.682 + 0.047*cl tn to pad t r 5.279 1.469 + 0.076*cl 1.475 + 0.076*cl 1.420 + 0.077*cl t f 6.225 2.451 + 0.075*cl 2.728 + 0.070*cl 2.916 + 0.067*cl t plh 5.629 3.285 + 0.047*cl 3.532 + 0.042*cl 3.704 + 0.040*cl t phl 8.076 4.952 + 0.062*cl 5.454 + 0.052*cl 5.882 + 0.047*cl t plz 2.857 2.857 + 0.000*cl 2.857 + 0.000*cl 2.856 + 0.000*cl t phz 2.572 2.572 + 0.000*cl 2.572 + 0.000*cl 2.571 + 0.000*cl en to pad t r 5.279 1.469 + 0.076*cl 1.475 + 0.076*cl 1.419 + 0.077*cl t f 6.225 2.451 + 0.075*cl 2.728 + 0.070*cl 2.916 + 0.067*cl t plh 5.732 3.388 + 0.047*cl 3.635 + 0.042*cl 3.807 + 0.040*cl t phl 8.178 5.056 + 0.062*cl 5.557 + 0.052*cl 5.985 + 0.047*cl t plz 2.900 2.901 + 0.000*cl 2.900 + 0.000*cl 2.900 + 0.000*cl t phz 2.615 2.616 + 0.000*cl 2.615 + 0.000*cl 2.615 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 4.965 1.691 + 0.065*cl 1.798 + 0.063*cl 1.812 + 0.063*cl t f 6.246 2.790 + 0.069*cl 3.146 + 0.062*cl 3.418 + 0.058*cl t plh 5.693 3.462 + 0.045*cl 3.765 + 0.039*cl 4.004 + 0.035*cl t phl 8.197 5.024 + 0.063*cl 5.605 + 0.052*cl 6.112 + 0.045*cl tn to pad t r 4.983 1.756 + 0.065*cl 1.833 + 0.063*cl 1.833 + 0.063*cl t f 6.248 2.799 + 0.069*cl 3.151 + 0.062*cl 3.421 + 0.058*cl t plh 5.769 3.514 + 0.045*cl 3.832 + 0.039*cl 4.077 + 0.035*cl t phl 8.397 5.221 + 0.064*cl 5.805 + 0.052*cl 6.310 + 0.045*cl t plz 3.262 3.262 + 0.000*cl 3.262 + 0.000*cl 3.261 + 0.000*cl t phz 2.957 2.957 + 0.000*cl 2.957 + 0.000*cl 2.957 + 0.000*cl en to pad t r 4.983 1.756 + 0.065*cl 1.833 + 0.063*cl 1.833 + 0.063*cl t f 6.248 2.799 + 0.069*cl 3.151 + 0.062*cl 3.421 + 0.058*cl t plh 5.871 3.618 + 0.045*cl 3.935 + 0.039*cl 4.180 + 0.035*cl t phl 8.500 5.325 + 0.063*cl 5.908 + 0.052*cl 6.413 + 0.045*cl t plz 3.306 3.306 + 0.000*cl 3.306 + 0.000*cl 3.305 + 0.000*cl t phz 3.001 3.001 + 0.000*cl 3.001 + 0.000*cl 3.001 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-56 samsung asic pvotyz tri-state output buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 0.17ns, cl: capacitive load[pf]) ptot1 ptot2 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 44.026 2.843 + 0.824*cl 2.992 + 0.821*cl 3.100 + 0.819*cl t f 33.890 2.747 + 0.623*cl 2.704 + 0.624*cl 2.677 + 0.624*cl t plh 21.514 2.654 + 0.377*cl 2.712 + 0.376*cl 2.748 + 0.376*cl t phl 17.371 1.761 + 0.312*cl 1.781 + 0.312*cl 1.799 + 0.312*cl tn to pad t r 44.026 2.843 + 0.824*cl 2.992 + 0.821*cl 3.100 + 0.819*cl t f 33.854 2.744 + 0.622*cl 2.692 + 0.623*cl 2.662 + 0.624*cl t plh 21.600 2.740 + 0.377*cl 2.798 + 0.376*cl 2.834 + 0.376*cl t phl 17.491 1.944 + 0.311*cl 1.951 + 0.311*cl 1.963 + 0.311*cl t plz 1.075 1.075 + 0.000*cl 1.075 + 0.000*cl 1.075 + 0.000*cl t phz 1.801 1.800 + 0.000*cl 1.800 + 0.000*cl 1.801 + 0.000*cl en to pad t r 44.026 2.843 + 0.824*cl 2.992 + 0.821*cl 3.100 + 0.819*cl t f 33.854 2.744 + 0.622*cl 2.692 + 0.623*cl 2.662 + 0.624*cl t plh 21.702 2.845 + 0.377*cl 2.900 + 0.376*cl 2.936 + 0.376*cl t phl 17.593 2.048 + 0.311*cl 2.051 + 0.311*cl 2.069 + 0.311*cl t plz 1.120 1.120 + 0.000*cl 1.120 + 0.000*cl 1.120 + 0.000*cl t phz 1.844 1.844 + 0.000*cl 1.844 + 0.000*cl 1.844 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 22.250 1.485 + 0.415*cl 1.620 + 0.413*cl 1.725 + 0.411*cl t f 17.034 1.379 + 0.313*cl 1.416 + 0.312*cl 1.419 + 0.312*cl t plh 11.348 1.857 + 0.190*cl 1.908 + 0.189*cl 1.947 + 0.188*cl t phl 9.224 1.372 + 0.157*cl 1.399 + 0.157*cl 1.422 + 0.156*cl tn to pad t r 22.250 1.485 + 0.415*cl 1.620 + 0.413*cl 1.725 + 0.411*cl t f 16.992 1.367 + 0.312*cl 1.396 + 0.312*cl 1.402 + 0.312*cl t plh 11.434 1.944 + 0.190*cl 1.994 + 0.189*cl 2.030 + 0.188*cl t phl 9.348 1.545 + 0.156*cl 1.563 + 0.156*cl 1.579 + 0.155*cl t plz 1.201 1.201 + 0.000*cl 1.201 + 0.000*cl 1.201 + 0.000*cl t phz 2.304 2.304 + 0.000*cl 2.304 + 0.000*cl 2.303 + 0.000*cl en to pad t r 22.250 1.485 + 0.415*cl 1.620 + 0.413*cl 1.725 + 0.411*cl t f 16.992 1.367 + 0.312*cl 1.396 + 0.312*cl 1.402 + 0.312*cl t plh 11.537 2.046 + 0.190*cl 2.097 + 0.189*cl 2.136 + 0.188*cl t phl 9.450 1.648 + 0.156*cl 1.664 + 0.156*cl 1.685 + 0.155*cl t plz 1.245 1.245 + 0.000*cl 1.245 + 0.000*cl 1.245 + 0.000*cl t phz 2.347 2.347 + 0.000*cl 2.347 + 0.000*cl 2.347 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-57 STD111 pvotyz tri-state output buffers switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 0.17ns, cl: capacitive load[pf]) ptot3 path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 14.950 1.003 + 0.279*cl 1.124 + 0.277*cl 1.223 + 0.275*cl t f 11.398 0.929 + 0.209*cl 0.952 + 0.209*cl 0.976 + 0.209*cl t plh 7.984 1.628 + 0.127*cl 1.665 + 0.126*cl 1.702 + 0.126*cl t phl 6.545 1.288 + 0.105*cl 1.308 + 0.105*cl 1.327 + 0.104*cl tn to pad t r 14.950 1.005 + 0.279*cl 1.122 + 0.277*cl 1.227 + 0.275*cl t f 11.350 0.906 + 0.209*cl 0.926 + 0.208*cl 0.947 + 0.208*cl t plh 8.070 1.714 + 0.127*cl 1.751 + 0.126*cl 1.789 + 0.126*cl t phl 6.666 1.450 + 0.104*cl 1.462 + 0.104*cl 1.481 + 0.104*cl t plz 1.323 1.323 + 0.000*cl 1.323 + 0.000*cl 1.323 + 0.000*cl t phz 2.808 2.809 + 0.000*cl 2.808 + 0.000*cl 2.808 + 0.000*cl en to pad t r 14.950 1.005 + 0.279*cl 1.122 + 0.277*cl 1.227 + 0.275*cl t f 11.350 0.906 + 0.209*cl 0.926 + 0.208*cl 0.947 + 0.208*cl t plh 8.173 1.817 + 0.127*cl 1.855 + 0.126*cl 1.891 + 0.126*cl t phl 6.768 1.553 + 0.104*cl 1.565 + 0.104*cl 1.584 + 0.104*cl t plz 1.367 1.367 + 0.000*cl 1.367 + 0.000*cl 1.367 + 0.000*cl t phz 2.852 2.853 + 0.000*cl 2.852 + 0.000*cl 2.851 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-58 samsung asic bi-directional buffers cell list cell name function description pbadyz 2.5v open-drain bi-directional buffers pbaudyz 2.5v open-drain bi-directional buffers with pull-up phbadyz 3.3v interface open-drain bi-directional buffers with pull-down phbaudyz 3.3v interface open-drain bi-directional buffers with pull-up ptbady 5v - tolerant open-drain bi-directional buffers ptbaudy 5v - tolerant open-drain bi-directional buffers with pull-up pbatyz 2.5v tri-state bi-directional buffers pbadtyz 2.5v tri-state bi-directional buffers with pull-down pbautyz 2.5v tri-state bi-directional buffers with pull-up phbatyz 3.3v interface tri-state bi-directional buffers phbadtyz 3.3v interface tri-state bi-directional buffers with pull-down phbautyz 3.3v interface tri-state bi-directional buffers with pull-up ptbaty 5v - tolerant tri-state bi-directional buffers ptbadty 5v - tolerant tri-state bi-directional buffers with pull-down ptbauty 5v - tolerant tri-state bi-directional buffers with pull-up
samsung asic 4-59 STD111 open drain bi-directional buffers pvbadyz pvbaudyz tri-state bi-directional buffers pvbatyz pvbadtyz pvbautyz pa d tn en y po pi pa d tn en y po pi pa d a tn en y po pi pa d a tn en y po pi pa d a tn en y po pi bi-directional buffers
STD111 4-60 samsung asic input clock drivers cell list cell name function description psckdc(2/4/6/8) 2.5v lvcmos level input clock driver psckdcd(2/4/6/8) 2.5v lvcmos level input clock driver with pull-down psckdcu(2/4/6/8) 2.5v lvcmos level input clock driver with pull-up psckds(2/4/6/8) 2.5v lvcmos-schmitt trigger level input clock driver psckdsd(2/4/6/8) 2.5v lvcmos-schmitt trigger level input clock driver with pull-down psckdsu(2/4/6/8) 2.5v lvcmos-schmitt trigger level input clock driver with pull-up
samsung asic 4-61 STD111 psckdcby lvcmos level input clock drivers logic symbol y po pi pa d y po pi pa d y po pi pa d psckdc psckdcd psckdcu cell availability truth table standard load (sl) only 2.5v psckdc/psckdcd/psckdcu (2/4/6/8) pa d p i y p o 1110 0x01 1011 cell name pi psckdc/psckdcd/psckdcu (2/4/6/8) 4.193
STD111 4-62 samsung asic psckdcby lvcmos level input clock drivers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 3.00ns, sl: standard load) psckdc2 psckdc4 psckdc6 psckdc8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.175 0.169 + 0.003*sl 0.124 + 0.003*sl 0.100 + 0.003*sl t f 0.142 0.134 + 0.004*sl 0.101 + 0.004*sl 0.086 + 0.004*sl t plh 0.813 0.811 + 0.001*sl 0.807 + 0.001*sl 0.806 + 0.001*sl t phl 0.795 0.791 + 0.002*sl 0.788 + 0.002*sl 0.789 + 0.002*sl *group1 : sl < 482, *group2 : 482 sl < < = = 722, *group3 : 722 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.235 0.232 + 0.002*sl 0.175 + 0.002*sl 0.136 + 0.002*sl t f 0.182 0.178 + 0.002*sl 0.126 + 0.002*sl 0.099 + 0.002*sl t plh 1.051 1.049 + 0.001*sl 1.050 + 0.001*sl 1.048 + 0.001*sl t phl 1.036 1.034 + 0.001*sl 1.031 + 0.001*sl 1.028 + 0.001*sl *group1 : sl < 962, *group2 : 962 sl < < = = 1443, *group3 : 1443 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.291 0.289 + 0.001*sl 0.226 + 0.001*sl 0.181 + 0.001*sl t f 0.224 0.222 + 0.001*sl 0.160 + 0.001*sl 0.122 + 0.001*sl t plh 1.246 1.245 + 0.000*sl 1.254 + 0.000*sl 1.251 + 0.000*sl t phl 1.237 1.235 + 0.001*sl 1.232 + 0.001*sl 1.227 + 0.001*sl *group1 : sl < 1443, *group2 : 1443 sl < < = = 2165, *group3 : 2165 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.341 0.340 + 0.001*sl 0.273 + 0.001*sl 0.224 + 0.001*sl t f 0.263 0.262 + 0.001*sl 0.196 + 0.001*sl 0.149 + 0.001*sl t plh 1.415 1.414 + 0.000*sl 1.431 + 0.000*sl 1.429 + 0.000*sl t phl 1.410 1.409 + 0.000*sl 1.407 + 0.000*sl 1.402 + 0.000*sl *group1 : sl < 1923, *group2 : 1923 sl < < = = 2887, *group3 : 2887 < sl
samsung asic 4-63 STD111 psckdcby lvcmos level input clock drivers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 3.00ns, sl: standard load) psckdcd2 psckdcd4 psckdcd6 psckdcd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.172 0.165 + 0.003*sl 0.122 + 0.003*sl 0.099 + 0.003*sl t f 0.146 0.139 + 0.004*sl 0.104 + 0.004*sl 0.087 + 0.004*sl t plh 0.903 0.900 + 0.001*sl 0.897 + 0.001*sl 0.896 + 0.001*sl t phl 0.796 0.792 + 0.002*sl 0.789 + 0.002*sl 0.790 + 0.002*sl *group1 : sl < 482, *group2 : 482 sl < < = = 722, *group3 : 722 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.231 0.228 + 0.002*sl 0.171 + 0.002*sl 0.135 + 0.002*sl t f 0.189 0.185 + 0.002*sl 0.130 + 0.002*sl 0.102 + 0.002*sl t plh 1.137 1.135 + 0.001*sl 1.136 + 0.001*sl 1.133 + 0.001*sl t phl 1.048 1.046 + 0.001*sl 1.042 + 0.001*sl 1.039 + 0.001*sl *group1 : sl < 962, *group2 : 962 sl < < = = 1443, *group3 : 1443 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.287 0.285 + 0.001*sl 0.222 + 0.001*sl 0.178 + 0.001*sl t f 0.234 0.231 + 0.001*sl 0.167 + 0.001*sl 0.127 + 0.001*sl t plh 1.330 1.329 + 0.000*sl 1.338 + 0.000*sl 1.334 + 0.000*sl t phl 1.256 1.255 + 0.001*sl 1.252 + 0.001*sl 1.246 + 0.001*sl *group1 : sl < 1443, *group2 : 1443 sl < < = = 2165, *group3 : 2165 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.337 0.335 + 0.001*sl 0.270 + 0.001*sl 0.222 + 0.001*sl t f 0.274 0.273 + 0.001*sl 0.205 + 0.001*sl 0.156 + 0.001*sl t plh 1.497 1.496 + 0.000*sl 1.513 + 0.000*sl 1.511 + 0.000*sl t phl 1.436 1.435 + 0.000*sl 1.434 + 0.000*sl 1.427 + 0.000*sl *group1 : sl < 1923, *group2 : 1923 sl < < = = 2887, *group3 : 2887 < sl
STD111 4-64 samsung asic psckdcby lvcmos level input clock drivers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 3.00ns, sl: standard load) psckdcu2 psckdcu4 psckdcu6 psckdcu8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.181 0.174 + 0.003*sl 0.128 + 0.003*sl 0.102 + 0.003*sl t f 0.140 0.133 + 0.004*sl 0.100 + 0.004*sl 0.086 + 0.004*sl t plh 0.810 0.807 + 0.001*sl 0.804 + 0.001*sl 0.802 + 0.001*sl t phl 0.879 0.875 + 0.002*sl 0.873 + 0.002*sl 0.873 + 0.002*sl *group1 : sl < 482, *group2 : 482 sl < < = = 722, *group3 : 722 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.243 0.240 + 0.002*sl 0.181 + 0.002*sl 0.141 + 0.002*sl t f 0.179 0.175 + 0.002*sl 0.124 + 0.002*sl 0.098 + 0.002*sl t plh 1.055 1.053 + 0.001*sl 1.054 + 0.001*sl 1.052 + 0.001*sl t phl 1.117 1.115 + 0.001*sl 1.112 + 0.001*sl 1.108 + 0.001*sl *group1 : sl < 962, *group2 : 962 sl < < = = 1443, *group3 : 1443 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.301 0.299 + 0.001*sl 0.233 + 0.001*sl 0.187 + 0.001*sl t f 0.221 0.219 + 0.001*sl 0.158 + 0.001*sl 0.121 + 0.001*sl t plh 1.255 1.254 + 0.000*sl 1.264 + 0.000*sl 1.261 + 0.000*sl t phl 1.315 1.314 + 0.001*sl 1.311 + 0.001*sl 1.306 + 0.001*sl *group1 : sl < 1443, *group2 : 1443 sl < < = = 2165, *group3 : 2165 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.352 0.350 + 0.001*sl 0.282 + 0.001*sl 0.231 + 0.001*sl t f 0.260 0.258 + 0.001*sl 0.194 + 0.001*sl 0.148 + 0.001*sl t plh 1.428 1.427 + 0.000*sl 1.446 + 0.000*sl 1.444 + 0.000*sl t phl 1.487 1.486 + 0.000*sl 1.484 + 0.000*sl 1.479 + 0.000*sl *group1 : sl < 1923, *group2 : 1923 sl < < = = 2887, *group3 : 2887 < sl
samsung asic 4-65 STD111 psckdsby lvcmos schmitt trigger level input clock drivers logic symbol y po pi pa d y po pi pa d y po pi pa d psckds psckdsd psckdsu cell availability truth table standard load (sl) only 2.5v psckds/psckdsd/psckdsu(2/4/6/8) pa d p i y p o 1110 0x01 1011 pi psckds/psckdsd/psckdsu (2/4/6/8) 4.193
STD111 4-66 samsung asic psckdsby lvcmos schmitt trigger level input clock drivers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 3.00ns, sl: standard load) psckds2 psckds4 psckds6 psckds8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.201 0.195 + 0.003*sl 0.157 + 0.003*sl 0.130 + 0.003*sl t f 0.194 0.187 + 0.004*sl 0.149 + 0.004*sl 0.124 + 0.004*sl t plh 1.142 1.139 + 0.001*sl 1.142 + 0.001*sl 1.142 + 0.001*sl t phl 1.195 1.191 + 0.002*sl 1.197 + 0.002*sl 1.196 + 0.002*sl *group1 : sl < 482, *group2 : 482 sl < < = = 722, *group3 : 722 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.270 0.267 + 0.002*sl 0.219 + 0.002*sl 0.182 + 0.002*sl t f 0.264 0.260 + 0.002*sl 0.215 + 0.002*sl 0.178 + 0.002*sl t plh 1.401 1.399 + 0.001*sl 1.415 + 0.001*sl 1.418 + 0.001*sl t phl 1.484 1.482 + 0.001*sl 1.500 + 0.001*sl 1.501 + 0.001*sl *group1 : sl < 962, *group2 : 962 sl < < = = 1443, *group3 : 1443 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.331 0.329 + 0.001*sl 0.278 + 0.001*sl 0.239 + 0.001*sl t f 0.356 0.354 + 0.001*sl 0.307 + 0.001*sl 0.261 + 0.001*sl t plh 1.610 1.609 + 0.001*sl 1.639 + 0.000*sl 1.645 + 0.000*sl t phl 1.743 1.742 + 0.001*sl 1.775 + 0.001*sl 1.783 + 0.001*sl *group1 : sl < 1443, *group2 : 1443 sl < < = = 2165, *group3 : 2165 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.384 0.383 + 0.001*sl 0.334 + 0.001*sl 0.293 + 0.001*sl t f 0.456 0.454 + 0.001*sl 0.406 + 0.001*sl 0.359 + 0.001*sl t plh 1.788 1.788 + 0.000*sl 1.829 + 0.000*sl 1.841 + 0.000*sl t phl 1.990 1.989 + 0.001*sl 2.039 + 0.000*sl 2.055 + 0.000*sl *group1 : sl < 1923, *group2 : 1923 sl < < = = 2887, *group3 : 2887 < sl
samsung asic 4-67 STD111 psckdsby lvcmos schmitt trigger level input clock drivers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 3.00ns, sl: standard load) psckdsd2 psckdsd4 psckdsd6 psckdsd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.199 0.193 + 0.003*sl 0.155 + 0.003*sl 0.129 + 0.003*sl t f 0.198 0.191 + 0.004*sl 0.153 + 0.004*sl 0.127 + 0.004*sl t plh 1.208 1.205 + 0.001*sl 1.208 + 0.001*sl 1.209 + 0.001*sl t phl 1.243 1.239 + 0.002*sl 1.246 + 0.002*sl 1.245 + 0.002*sl *group1 : sl < 482, *group2 : 482 sl < < = = 722, *group3 : 722 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.267 0.264 + 0.002*sl 0.217 + 0.002*sl 0.181 + 0.002*sl t f 0.269 0.266 + 0.002*sl 0.220 + 0.002*sl 0.182 + 0.002*sl t plh 1.464 1.463 + 0.001*sl 1.478 + 0.001*sl 1.481 + 0.001*sl t phl 1.547 1.545 + 0.001*sl 1.562 + 0.001*sl 1.564 + 0.001*sl *group1 : sl < 962, *group2 : 962 sl < < = = 1443, *group3 : 1443 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.328 0.326 + 0.001*sl 0.276 + 0.001*sl 0.237 + 0.001*sl t f 0.361 0.358 + 0.001*sl 0.310 + 0.001*sl 0.264 + 0.001*sl t plh 1.671 1.670 + 0.001*sl 1.700 + 0.000*sl 1.706 + 0.000*sl t phl 1.815 1.813 + 0.001*sl 1.846 + 0.001*sl 1.853 + 0.001*sl *group1 : sl < 1443, *group2 : 1443 sl < < = = 2165, *group3 : 2165 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.382 0.381 + 0.001*sl 0.332 + 0.001*sl 0.291 + 0.001*sl t f 0.458 0.457 + 0.001*sl 0.408 + 0.001*sl 0.360 + 0.001*sl t plh 1.849 1.848 + 0.000*sl 1.889 + 0.000*sl 1.901 + 0.000*sl t phl 2.066 2.065 + 0.001*sl 2.115 + 0.000*sl 2.131 + 0.000*sl *group1 : sl < 1923, *group2 : 1923 sl < < = = 2887, *group3 : 2887 < sl
STD111 4-68 samsung asic psckdsby lvcmos schmitt trigger level input clock drivers switching characteristics (typical process, 25 c, 2.5v, t r /t f = 3.00ns, sl: standard load) psckdsu2 psckdsu4 psckdsu6 psckdsu8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.206 0.200 + 0.003*sl 0.160 + 0.003*sl 0.133 + 0.003*sl t f 0.193 0.186 + 0.004*sl 0.149 + 0.004*sl 0.124 + 0.004*sl t plh 1.168 1.165 + 0.001*sl 1.168 + 0.001*sl 1.168 + 0.001*sl t phl 1.253 1.249 + 0.002*sl 1.256 + 0.002*sl 1.255 + 0.002*sl *group1 : sl < 482, *group2 : 482 sl < < = = 722, *group3 : 722 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.276 0.273 + 0.002*sl 0.225 + 0.002*sl 0.187 + 0.002*sl t f 0.268 0.264 + 0.002*sl 0.220 + 0.002*sl 0.182 + 0.002*sl t plh 1.435 1.434 + 0.001*sl 1.451 + 0.001*sl 1.453 + 0.001*sl t phl 1.545 1.543 + 0.001*sl 1.562 + 0.001*sl 1.564 + 0.001*sl *group1 : sl < 962, *group2 : 962 sl < < = = 1443, *group3 : 1443 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.339 0.337 + 0.001*sl 0.285 + 0.001*sl 0.245 + 0.001*sl t f 0.365 0.362 + 0.001*sl 0.315 + 0.001*sl 0.269 + 0.001*sl t plh 1.651 1.650 + 0.001*sl 1.681 + 0.000*sl 1.688 + 0.000*sl t phl 1.811 1.810 + 0.001*sl 1.845 + 0.001*sl 1.853 + 0.001*sl *group1 : sl < 1443, *group2 : 1443 sl < < = = 2165, *group3 : 2165 < sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.394 0.392 + 0.001*sl 0.342 + 0.001*sl 0.300 + 0.001*sl t f 0.469 0.467 + 0.001*sl 0.418 + 0.001*sl 0.370 + 0.001*sl t plh 1.835 1.834 + 0.000*sl 1.877 + 0.000*sl 1.890 + 0.000*sl t phl 2.066 2.065 + 0.001*sl 2.117 + 0.000*sl 2.134 + 0.000*sl *group1 : sl < 1923, *group2 : 1923 sl < < = = 2887, *group3 : 2887 < sl
STD111 4-69 samsung asic oscillators cell list note: use i/o 3.3v and core 2.5v note: use i/o 2.5v and core 2.5v cell name function description phsosck1 oscillator cell with enable (~ 100khz) phsosck2 oscillator cell with enable (100k ~ 1mhz) phsosck17 oscillator cell with enable and feedback resistor (~ 100khz) phsosck27 oscillator cell with enable and feedback resistor (100k ~ 1mhz) phsoscm1 oscillator cell with enable (1m ~ 10mhz) phsoscm2 oscillator cell with enable (10m ~ 40mhz) phsoscm3 oscillator cell with enable (40m ~ 100mhz) phsoscm16 oscillator cell with enable and feedback resistor (1m ~ 10mhz) phsoscm26 oscillator cell with enable and feedback resistor (10m ~ 40mhz) phsoscm36 oscillator cell with enable and feedback resistor (40m ~ 100mhz) cell name function description psosck1 oscillator cell with enable (~ 100khz) psosck2 oscillator cell with enable (100k ~ 1mhz) psoscm1 oscillator cell with enable (1m ~ 10mhz) psoscm2 oscillator cell with enable (10m ~ 40mhz)
STD111 4-70 samsung asic phsosck1/k2/m1/m2/m3 oscillator cell with enable logic symbol truth table cell data e pada pady yn pi po 000001 000011 010001 010011 101101 101110 110001 110011 input load (sl) i/o sizes phsosck1/k2 phsoscm1/m2/m3 phsosck1/k2 phsoscm1/m2/m3 ee 3.55 3.55 2 i/o slots 2 i/o slots e pa da pa dy yn po pi
samsung asic 4-71 STD111 phsosck1/k2/m1/m2/m3 oscillator cell with enable switching characteristics phsosck1 (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, cl: capacitive load) (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, sl: standard load) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t r 2030.800 40.550 + 39.805*cl 40.800 + 39.800*cl 40.500 + 39.804*cl t f 1973.700 39.450 + 38.685*cl 39.300 + 38.688*cl 39.600 + 38.684*cl t plh 909.370 19.320 + 17.801*cl 19.310 + 17.801*cl 19.400 + 17.800*cl t phl 957.810 20.335 + 18.749*cl 20.430 + 18.748*cl 20.100 + 18.752*cl e to pady t r 2030.800 40.550 + 39.805*cl 40.800 + 39.800*cl 40.500 + 39.804*cl t f 1973.700 39.450 + 38.685*cl 39.300 + 38.688*cl 39.600 + 38.684*cl t plh 909.250 19.200 + 17.801*cl 19.150 + 17.802*cl 19.300 + 17.800*cl t phl 957.470 20.020 + 18.749*cl 20.010 + 18.749*cl 20.100 + 18.748*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t r 0.203 0.187 + 0.008*sl 0.190 + 0.007*sl 0.189 + 0.007*sl t f 0.201 0.186 + 0.007*sl 0.189 + 0.007*sl 0.200 + 0.006*sl t plh 10.400 10.389 + 0.006*sl 10.394 + 0.004*sl 10.426 + 0.003*sl t phl 12.561 12.550 + 0.006*sl 12.555 + 0.004*sl 12.592 + 0.004*sl e to yn t r 0.203 0.187 + 0.008*sl 0.190 + 0.007*sl 0.189 + 0.007*sl t f 0.201 0.186 + 0.008*sl 0.189 + 0.007*sl 0.199 + 0.006*sl t plh 9.676 9.665 + 0.006*sl 9.669 + 0.004*sl 9.702 + 0.003*sl t phl 12.364 12.353 + 0.006*sl 12.357 + 0.004*sl 12.396 + 0.004*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
STD111 4-72 samsung asic phsosck1/k2/m1/m2/m3 oscillator cell with enable switching characteristics phsosck2 (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, cl: capacitive load) (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, sl: standard load) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t r 261.510 5.285 + 5.124*cl 5.270 + 5.125*cl 5.270 + 5.125*cl t f 246.440 4.965 + 4.830*cl 4.940 + 4.830*cl 4.940 + 4.830*cl t plh 96.965 2.873 + 1.882*cl 2.875 + 1.882*cl 2.860 + 1.882*cl t phl 97.991 2.901 + 1.902*cl 2.893 + 1.902*cl 2.920 + 1.902*cl e to pady t r 261.510 5.285 + 5.124*cl 5.270 + 5.125*cl 5.270 + 5.125*cl t f 246.440 4.965 + 4.830*cl 4.940 + 4.830*cl 4.970 + 4.830*cl t plh 96.810 2.720 + 1.882*cl 2.710 + 1.882*cl 2.710 + 1.882*cl t phl 97.596 2.503 + 1.902*cl 2.508 + 1.902*cl 2.490 + 1.902*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t r 0.187 0.170 + 0.008*sl 0.175 + 0.007*sl 0.168 + 0.007*sl t f 0.177 0.162 + 0.008*sl 0.166 + 0.007*sl 0.172 + 0.006*sl t plh 2.286 2.276 + 0.005*sl 2.280 + 0.004*sl 2.306 + 0.003*sl t phl 2.131 2.119 + 0.006*sl 2.124 + 0.004*sl 2.157 + 0.004*sl e to yn t r 0.186 0.170 + 0.008*sl 0.175 + 0.007*sl 0.168 + 0.007*sl t f 0.177 0.162 + 0.008*sl 0.166 + 0.007*sl 0.172 + 0.006*sl t plh 2.149 2.138 + 0.005*sl 2.143 + 0.004*sl 2.169 + 0.003*sl t phl 1.687 1.676 + 0.006*sl 1.681 + 0.004*sl 1.714 + 0.004*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
samsung asic 4-73 STD111 phsosck1/k2/m1/m2/m3 oscillator cell with enable switching characteristics phsoscm1 (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, cl: capacitive load) (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, sl: standard load) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t r 16.399 0.541 + 0.317*cl 0.289 + 0.322*cl 0.310 + 0.322*cl t f 17.023 0.453 + 0.331*cl 0.571 + 0.329*cl 0.331 + 0.332*cl t plh 8.556 1.164 + 0.148*cl 1.131 + 0.149*cl 1.139 + 0.148*cl t phl 9.600 1.162 + 0.169*cl 1.138 + 0.169*cl 1.147 + 0.169*cl e to pady t r 16.474 0.549 + 0.319*cl 0.448 + 0.321*cl 0.454 + 0.320*cl t f 17.028 0.513 + 0.330*cl 0.532 + 0.330*cl 0.484 + 0.331*cl t plh 8.505 1.045 + 0.149*cl 1.110 + 0.148*cl 1.073 + 0.148*cl t phl 9.491 1.019 + 0.169*cl 1.036 + 0.169*cl 1.026 + 0.169*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t r 0.140 0.125 + 0.007*sl 0.126 + 0.007*sl 0.121 + 0.007*sl t f 0.128 0.113 + 0.007*sl 0.116 + 0.007*sl 0.114 + 0.007*sl t plh 1.378 1.369 + 0.004*sl 1.372 + 0.004*sl 1.384 + 0.003*sl t phl 1.140 1.131 + 0.005*sl 1.134 + 0.004*sl 1.149 + 0.003*sl e to yn t r 0.139 0.123 + 0.008*sl 0.126 + 0.007*sl 0.121 + 0.007*sl t f 0.128 0.114 + 0.007*sl 0.116 + 0.007*sl 0.115 + 0.007*sl t plh 1.558 1.549 + 0.004*sl 1.552 + 0.004*sl 1.565 + 0.003*sl t phl 1.243 1.234 + 0.005*sl 1.237 + 0.004*sl 1.251 + 0.003*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
STD111 4-74 samsung asic phsosck1/k2/m1/m2/m3 oscillator cell with enable switching characteristics phsoscm2 (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, cl: capacitive load) (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, sl: standard load) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t r 4.378 0.613 + 0.075*cl 0.480 + 0.078*cl 0.361 + 0.080*cl t f 4.588 0.819 + 0.075*cl 0.650 + 0.079*cl 0.499 + 0.081*cl t plh 3.414 1.536 + 0.038*cl 1.548 + 0.037*cl 1.546 + 0.037*cl t phl 3.720 1.579 + 0.043*cl 1.610 + 0.042*cl 1.612 + 0.042*cl e to pady t r 4.294 0.370 + 0.078*cl 0.310 + 0.080*cl 0.263 + 0.080*cl t f 4.466 0.504 + 0.079*cl 0.423 + 0.081*cl 0.358 + 0.082*cl t plh 3.458 1.565 + 0.038*cl 1.580 + 0.038*cl 1.584 + 0.038*cl t phl 3.971 1.827 + 0.043*cl 1.851 + 0.042*cl 1.856 + 0.042*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t r 0.109 0.096 + 0.006*sl 0.095 + 0.007*sl 0.094 + 0.007*sl t f 0.095 0.082 + 0.007*sl 0.082 + 0.007*sl 0.081 + 0.007*sl t plh 1.719 1.711 + 0.004*sl 1.713 + 0.003*sl 1.718 + 0.003*sl t phl 1.436 1.428 + 0.004*sl 1.430 + 0.004*sl 1.437 + 0.003*sl e to yn t r 0.109 0.096 + 0.006*sl 0.095 + 0.007*sl 0.094 + 0.007*sl t f 0.095 0.082 + 0.006*sl 0.082 + 0.007*sl 0.081 + 0.007*sl t plh 1.862 1.855 + 0.004*sl 1.857 + 0.003*sl 1.862 + 0.003*sl t phl 1.827 1.819 + 0.004*sl 1.821 + 0.004*sl 1.827 + 0.003*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
samsung asic 4-75 STD111 phsosck1/k2/m1/m2/m3 oscillator cell with enable switching characteristics phsoscm3 (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, cl: capacitive load) (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, sl: standard load) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t r 2.653 0.973 + 0.034*cl 1.264 + 0.028*cl 1.165 + 0.029*cl t f 2.830 1.187 + 0.033*cl 1.297 + 0.031*cl 1.220 + 0.032*cl t plh 3.235 2.217 + 0.020*cl 2.343 + 0.018*cl 2.425 + 0.017*cl t phl 3.349 2.145 + 0.024*cl 2.286 + 0.021*cl 2.416 + 0.020*cl e to pady t r 2.570 1.026 + 0.031*cl 1.207 + 0.027*cl 0.867 + 0.032*cl t f 2.801 1.194 + 0.032*cl 1.223 + 0.032*cl 1.346 + 0.030*cl t plh 3.433 2.410 + 0.020*cl 2.530 + 0.018*cl 2.625 + 0.017*cl t phl 4.374 3.161 + 0.024*cl 3.311 + 0.021*cl 3.446 + 0.019*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t r 0.093 0.086 + 0.003*sl 0.086 + 0.003*sl 0.084 + 0.004*sl t f 0.074 0.067 + 0.003*sl 0.067 + 0.003*sl 0.067 + 0.004*sl t plh 2.577 2.573 + 0.002*sl 2.574 + 0.002*sl 2.582 + 0.002*sl t phl 2.203 2.198 + 0.002*sl 2.199 + 0.002*sl 2.207 + 0.002*sl e to yn t r 0.093 0.087 + 0.003*sl 0.085 + 0.003*sl 0.084 + 0.004*sl t f 0.074 0.067 + 0.004*sl 0.067 + 0.003*sl 0.067 + 0.004*sl t plh 2.759 2.755 + 0.002*sl 2.756 + 0.002*sl 2.763 + 0.002*sl t phl 3.209 3.205 + 0.002*sl 3.206 + 0.002*sl 3.213 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
STD111 4-76 samsung asic phsosck17/k27/m16/m26/m36 oscillator cell with enable and feedback resistor logic symbol truth table cell data e pada pady yn pi po 000001 000011 010001 010011 101101 101110 110001 110011 input load (sl) i/o sizes phsosck17/k27 phsoscm16/m26/m36 phsosck17/k27 phsoscm16/m26/m36 ee 3.55 3.55 2 i/o slots 2 i/o slots e pa da pa dy yn po pi mos feedback resistor
samsung asic 4-77 STD111 phsosck17/k27/m16/m26/m36 oscillator cell with enable and 10mohm resistor switching characteristics phsosck17 (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, cl: capacitive load) (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, sl: standard load) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t r 2042.700 42.700 + 40.000*cl 43.100 + 39.992*cl 42.800 + 39.996*cl t f 1997.600 40.850 + 39.135*cl 41.000 + 39.132*cl 41.000 + 39.132*cl t plh 905.240 19.065 + 17.724*cl 19.120 + 17.722*cl 19.000 + 17.724*cl t phl 959.380 21.530 + 18.757*cl 21.540 + 18.757*cl 21.600 + 18.756*cl e to pady t r 2043.000 43.500 + 39.990*cl 43.400 + 39.992*cl 43.400 + 39.992*cl t f 1973.800 39.550 + 38.685*cl 39.600 + 38.684*cl 39.300 + 38.688*cl t plh 909.710 19.560 + 17.803*cl 19.530 + 17.804*cl 19.800 + 17.800*cl t phl 953.620 21.120 + 18.650*cl 21.060 + 18.651*cl 21.300 + 18.648*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t r 0.202 0.186 + 0.008*sl 0.190 + 0.007*sl 0.189 + 0.007*sl t f 0.201 0.185 + 0.008*sl 0.189 + 0.007*sl 0.199 + 0.006*sl t plh 10.406 10.396 + 0.005*sl 10.400 + 0.004*sl 10.432 + 0.003*sl t phl 12.617 12.606 + 0.006*sl 12.611 + 0.004*sl 12.648 + 0.004*sl e to yn t r 0.202 0.187 + 0.008*sl 0.190 + 0.007*sl 0.189 + 0.007*sl t f 0.201 0.186 + 0.007*sl 0.189 + 0.007*sl 0.199 + 0.006*sl t plh 9.695 9.684 + 0.006*sl 9.688 + 0.004*sl 9.720 + 0.003*sl t phl 12.361 12.350 + 0.006*sl 12.355 + 0.004*sl 12.392 + 0.004*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
STD111 4-78 samsung asic phsosck17/k27/m16/m26/m36 oscillator cell with enable and feedback resistor switching characteristics phsosck27 (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, cl: capacitive load) (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, sl: standard load) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t r 261.840 5.415 + 5.128*cl 5.400 + 5.129*cl 5.400 + 5.129*cl t f 246.770 4.995 + 4.836*cl 4.990 + 4.836*cl 4.960 + 4.836*cl t plh 96.999 2.934 + 1.881*cl 2.917 + 1.882*cl 2.950 + 1.881*cl t phl 98.217 3.074 + 1.903*cl 3.071 + 1.903*cl 3.080 + 1.903*cl e to pady t r 261.890 5.465 + 5.128*cl 5.470 + 5.128*cl 5.470 + 5.128*cl t f 246.440 4.965 + 4.830*cl 4.940 + 4.830*cl 4.940 + 4.830*cl t plh 96.895 2.798 + 1.882*cl 2.785 + 1.882*cl 2.800 + 1.882*cl t phl 97.654 2.607 + 1.901*cl 2.602 + 1.901*cl 2.590 + 1.901*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t r 0.187 0.171 + 0.008*sl 0.175 + 0.007*sl 0.168 + 0.007*sl t f 0.177 0.162 + 0.008*sl 0.166 + 0.007*sl 0.172 + 0.006*sl t plh 2.302 2.292 + 0.005*sl 2.296 + 0.004*sl 2.323 + 0.003*sl t phl 2.183 2.172 + 0.006*sl 2.177 + 0.004*sl 2.209 + 0.004*sl e to yn t r 0.187 0.171 + 0.008*sl 0.175 + 0.007*sl 0.168 + 0.007*sl t f 0.177 0.163 + 0.007*sl 0.165 + 0.007*sl 0.172 + 0.006*sl t plh 2.161 2.150 + 0.005*sl 2.154 + 0.004*sl 2.181 + 0.003*sl t phl 1.685 1.674 + 0.006*sl 1.679 + 0.004*sl 1.712 + 0.004*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
samsung asic 4-79 STD111 phsosck17/k27/m16/m26/m36 oscillator cell with enable and feedback resistor switching characteristics phsoscm16 (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, cl: capacitive load) (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, sl: standard load) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t r 16.421 0.399 + 0.320*cl 0.367 + 0.321*cl 0.250 + 0.323*cl t f 17.016 0.619 + 0.328*cl 0.498 + 0.330*cl 0.309 + 0.333*cl t plh 8.557 1.168 + 0.148*cl 1.122 + 0.149*cl 1.154 + 0.148*cl t phl 9.628 1.153 + 0.169*cl 1.179 + 0.169*cl 1.166 + 0.169*cl e to pady t r 16.450 0.607 + 0.317*cl 0.360 + 0.322*cl 0.420 + 0.321*cl t f 17.030 0.557 + 0.329*cl 0.522 + 0.330*cl 0.543 + 0.330*cl t plh 8.503 1.070 + 0.149*cl 1.110 + 0.148*cl 1.034 + 0.149*cl t phl 9.492 1.021 + 0.169*cl 1.037 + 0.169*cl 1.029 + 0.169*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t r 0.139 0.125 + 0.007*sl 0.125 + 0.007*sl 0.121 + 0.007*sl t f 0.129 0.116 + 0.007*sl 0.116 + 0.007*sl 0.114 + 0.007*sl t plh 1.386 1.378 + 0.004*sl 1.380 + 0.004*sl 1.392 + 0.003*sl t phl 1.146 1.137 + 0.005*sl 1.140 + 0.004*sl 1.155 + 0.003*sl e to yn t r 0.139 0.123 + 0.008*sl 0.126 + 0.007*sl 0.121 + 0.007*sl t f 0.128 0.114 + 0.007*sl 0.116 + 0.007*sl 0.115 + 0.007*sl t plh 1.562 1.553 + 0.004*sl 1.556 + 0.004*sl 1.568 + 0.003*sl t phl 1.242 1.232 + 0.005*sl 1.236 + 0.004*sl 1.250 + 0.003*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
STD111 4-80 samsung asic phsosck17/k27/m16/m26/m36 oscillator cell with enable and feedback resistor switching characteristics phsoscm26 (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, cl: capacitive load) (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, sl: standard load) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t r 4.379 0.612 + 0.075*cl 0.479 + 0.078*cl 0.361 + 0.080*cl t f 4.598 0.829 + 0.075*cl 0.659 + 0.079*cl 0.508 + 0.081*cl t plh 3.419 1.540 + 0.038*cl 1.553 + 0.037*cl 1.550 + 0.037*cl t phl 3.732 1.588 + 0.043*cl 1.620 + 0.042*cl 1.623 + 0.042*cl e to pady t r 4.297 0.372 + 0.078*cl 0.312 + 0.080*cl 0.265 + 0.080*cl t f 4.466 0.504 + 0.079*cl 0.423 + 0.081*cl 0.358 + 0.082*cl t plh 3.463 1.570 + 0.038*cl 1.585 + 0.038*cl 1.589 + 0.038*cl t phl 3.970 1.826 + 0.043*cl 1.851 + 0.042*cl 1.856 + 0.042*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t r 0.109 0.096 + 0.006*sl 0.095 + 0.007*sl 0.093 + 0.007*sl t f 0.095 0.082 + 0.007*sl 0.082 + 0.007*sl 0.081 + 0.007*sl t plh 1.725 1.718 + 0.004*sl 1.719 + 0.003*sl 1.724 + 0.003*sl t phl 1.440 1.432 + 0.004*sl 1.434 + 0.004*sl 1.440 + 0.003*sl e to yn t r 0.109 0.096 + 0.006*sl 0.095 + 0.007*sl 0.094 + 0.007*sl t f 0.095 0.081 + 0.007*sl 0.082 + 0.007*sl 0.081 + 0.007*sl t plh 1.867 1.860 + 0.004*sl 1.861 + 0.003*sl 1.866 + 0.003*sl t phl 1.826 1.818 + 0.004*sl 1.820 + 0.004*sl 1.826 + 0.003*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
samsung asic 4-81 STD111 phsosck17/k27/m16/m26/m36 oscillator cell with enable and feedback resistor switching characteristics phsoscm36 (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, cl: capacitive load) (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, sl: standard load) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t r 2.542 0.991 + 0.031*cl 0.980 + 0.031*cl 1.262 + 0.027*cl t f 2.837 1.210 + 0.033*cl 1.305 + 0.031*cl 1.221 + 0.032*cl t plh 3.238 2.222 + 0.020*cl 2.339 + 0.018*cl 2.440 + 0.017*cl t phl 3.357 2.147 + 0.024*cl 2.296 + 0.021*cl 2.419 + 0.020*cl e to pady t r 2.482 1.095 + 0.028*cl 0.589 + 0.038*cl 1.624 + 0.024*cl t f 2.797 1.165 + 0.033*cl 1.216 + 0.032*cl 1.349 + 0.030*cl t plh 3.437 2.415 + 0.020*cl 2.533 + 0.018*cl 2.633 + 0.017*cl t phl 4.373 3.160 + 0.024*cl 3.310 + 0.021*cl 3.443 + 0.019*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t r 0.093 0.086 + 0.003*sl 0.086 + 0.003*sl 0.084 + 0.004*sl t f 0.074 0.067 + 0.003*sl 0.067 + 0.003*sl 0.066 + 0.004*sl t plh 2.582 2.577 + 0.002*sl 2.579 + 0.002*sl 2.586 + 0.002*sl t phl 2.207 2.202 + 0.002*sl 2.204 + 0.002*sl 2.211 + 0.002*sl e to yn t r 0.093 0.087 + 0.003*sl 0.085 + 0.003*sl 0.084 + 0.004*sl t f 0.074 0.067 + 0.003*sl 0.066 + 0.004*sl 0.066 + 0.004*sl t plh 2.764 2.760 + 0.002*sl 2.761 + 0.002*sl 2.769 + 0.002*sl t phl 3.207 3.202 + 0.002*sl 3.204 + 0.002*sl 3.211 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
STD111 4-82 samsung asic psosck1/k2/m1/m2 oscillator cell with enable logic symbol truth table cell data e pada pady yn pi po 000001 000011 010001 010011 101101 101110 110001 110011 input load (sl) i/o sizes psosck1/k2 psoscm1/m2 psosck1/k2 psoscm1/m2 ee 3.49 3.49 2 i/o slots 2 i/o slots e pa da pa dy yn po pi
samsung asic 4-83 STD111 psosck1/k2/m1/m2 oscillator cell with enable switching characteristics psosck1 (typical process, 25 c, 2.5v, t r /t f = 3.00ns, cl: capacitive load) (typical process, 25 c, 2.5v, t r /t f = 3.00ns, sl: standard load) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t r 2059.600 79.600 + 39.600*cl 79.400 + 39.604*cl 79.400 + 39.604*cl t f 1941.400 72.400 + 37.380*cl 72.400 + 37.380*cl 72.100 + 37.384*cl t plh 885.410 33.110 + 17.046*cl 33.030 + 17.048*cl 33.300 + 17.044*cl t phl 872.610 36.035 + 16.732*cl 36.030 + 16.732*cl 36.000 + 16.732*cl e to pady t r 2059.600 79.600 + 39.600*cl 79.400 + 39.604*cl 79.400 + 39.604*cl t f 1941.400 72.400 + 37.380*cl 72.400 + 37.380*cl 72.100 + 37.384*cl t plh 884.940 32.615 + 17.047*cl 32.620 + 17.046*cl 32.800 + 17.044*cl t phl 872.030 35.455 + 16.732*cl 35.490 + 16.731*cl 35.400 + 16.732*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t r 0.179 0.164 + 0.008*sl 0.167 + 0.007*sl 0.161 + 0.007*sl t f 0.169 0.153 + 0.008*sl 0.158 + 0.006*sl 0.160 + 0.006*sl t plh 9.684 9.674 + 0.005*sl 9.678 + 0.004*sl 9.702 + 0.003*sl t phl 9.212 9.201 + 0.005*sl 9.205 + 0.004*sl 9.234 + 0.003*sl e to yn t r 0.179 0.162 + 0.009*sl 0.168 + 0.007*sl 0.162 + 0.007*sl t f 0.169 0.153 + 0.008*sl 0.158 + 0.006*sl 0.160 + 0.006*sl t plh 8.619 8.609 + 0.005*sl 8.613 + 0.004*sl 8.637 + 0.003*sl t phl 8.790 8.779 + 0.005*sl 8.783 + 0.004*sl 8.812 + 0.003*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
STD111 4-84 samsung asic psosck1/k2/m1/m2 oscillator cell with enable switching characteristics psosck2 (typical process, 25 c, 2.5v, t r /t f = 3.00ns, cl: capacitive load) (typical process, 25 c, 2.5v, t r /t f = 3.00ns, sl: standard load) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t r 312.740 12.140 + 6.012*cl 12.160 + 6.012*cl 12.160 + 6.012*cl t f 302.800 11.250 + 5.831*cl 11.260 + 5.831*cl 11.230 + 5.831*cl t plh 113.550 4.822 + 2.175*cl 4.830 + 2.174*cl 4.830 + 2.174*cl t phl 126.860 5.765 + 2.422*cl 5.760 + 2.422*cl 5.760 + 2.422*cl e to pady t r 312.730 12.155 + 6.012*cl 12.130 + 6.012*cl 12.160 + 6.012*cl t f 302.800 11.250 + 5.831*cl 11.260 + 5.831*cl 11.230 + 5.831*cl t plh 113.090 4.375 + 2.174*cl 4.350 + 2.175*cl 4.380 + 2.174*cl t phl 126.470 5.363 + 2.422*cl 5.370 + 2.422*cl 5.370 + 2.422*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t r 0.183 0.168 + 0.008*sl 0.171 + 0.007*sl 0.165 + 0.007*sl t f 0.174 0.159 + 0.007*sl 0.163 + 0.006*sl 0.165 + 0.006*sl t plh 1.034 1.024 + 0.005*sl 1.028 + 0.004*sl 1.052 + 0.003*sl t phl 0.984 0.973 + 0.005*sl 0.977 + 0.004*sl 1.006 + 0.003*sl e to yn t r 0.173 0.156 + 0.008*sl 0.161 + 0.007*sl 0.156 + 0.007*sl t f 0.162 0.147 + 0.008*sl 0.151 + 0.006*sl 0.154 + 0.006*sl t plh 0.760 0.750 + 0.005*sl 0.754 + 0.004*sl 0.777 + 0.003*sl t phl 0.737 0.726 + 0.005*sl 0.731 + 0.004*sl 0.758 + 0.003*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
samsung asic 4-85 STD111 psosck1/k2/m1/m2 oscillator cell with enable switching characteristics psoscm1 (typical process, 25 c, 2.5v, t r /t f = 3.00ns, cl: capacitive load) (typical process, 25 c, 2.5v, t r /t f = 3.00ns, sl: standard load) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t r 17.123 0.623 + 0.330*cl 0.771 + 0.327*cl 0.726 + 0.328*cl t f 14.433 0.838 + 0.272*cl 0.601 + 0.277*cl 0.520 + 0.278*cl t plh 8.392 1.252 + 0.143*cl 1.187 + 0.144*cl 1.210 + 0.144*cl t phl 7.916 1.254 + 0.133*cl 1.215 + 0.134*cl 1.264 + 0.133*cl e to pady t r 17.057 0.557 + 0.330*cl 0.597 + 0.329*cl 0.738 + 0.327*cl t f 14.461 0.695 + 0.275*cl 0.651 + 0.276*cl 0.576 + 0.277*cl t plh 8.003 0.780 + 0.144*cl 0.823 + 0.144*cl 0.826 + 0.144*cl t phl 7.640 0.925 + 0.134*cl 0.937 + 0.134*cl 0.986 + 0.133*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t r 0.259 0.229 + 0.015*sl 0.224 + 0.016*sl 0.192 + 0.017*sl t f 0.235 0.198 + 0.018*sl 0.200 + 0.018*sl 0.179 + 0.018*sl t plh 1.022 1.003 + 0.009*sl 1.008 + 0.008*sl 1.021 + 0.008*sl t phl 1.065 1.043 + 0.011*sl 1.048 + 0.010*sl 1.065 + 0.009*sl e to yn t r 0.252 0.222 + 0.015*sl 0.217 + 0.017*sl 0.188 + 0.017*sl t f 0.228 0.192 + 0.018*sl 0.192 + 0.018*sl 0.174 + 0.018*sl t plh 0.825 0.807 + 0.009*sl 0.811 + 0.008*sl 0.823 + 0.008*sl t phl 0.989 0.966 + 0.011*sl 0.971 + 0.010*sl 0.986 + 0.009*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
STD111 4-86 samsung asic psosck1/k2/m1/m2 oscillator cell with enable switching characteristics psoscm2 (typical process, 25 c, 2.5v, t r /t f = 3.00ns, cl: capacitive load) (typical process, 25 c, 2.5v, t r /t f = 3.00ns, sl: standard load) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t r 4.764 0.945 + 0.076*cl 1.199 + 0.071*cl 0.774 + 0.077*cl t f 4.163 1.162 + 0.060*cl 0.909 + 0.065*cl 0.914 + 0.065*cl t plh 3.306 1.509 + 0.036*cl 1.509 + 0.036*cl 1.556 + 0.035*cl t phl 3.235 1.479 + 0.035*cl 1.541 + 0.034*cl 1.581 + 0.033*cl e to pady t r 4.631 0.496 + 0.083*cl 0.768 + 0.077*cl 0.667 + 0.079*cl t f 3.953 0.486 + 0.069*cl 0.520 + 0.069*cl 0.462 + 0.069*cl t plh 2.971 1.152 + 0.036*cl 1.177 + 0.036*cl 1.139 + 0.036*cl t phl 3.245 1.505 + 0.035*cl 1.565 + 0.034*cl 1.577 + 0.033*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t r 0.094 0.083 + 0.005*sl 0.083 + 0.005*sl 0.078 + 0.005*sl t f 0.097 0.087 + 0.005*sl 0.085 + 0.005*sl 0.079 + 0.006*sl t plh 1.123 1.117 + 0.003*sl 1.118 + 0.003*sl 1.122 + 0.002*sl t phl 1.082 1.074 + 0.004*sl 1.076 + 0.003*sl 1.083 + 0.003*sl e to yn t r 0.086 0.075 + 0.005*sl 0.075 + 0.005*sl 0.074 + 0.005*sl t f 0.088 0.077 + 0.006*sl 0.077 + 0.006*sl 0.072 + 0.006*sl t plh 0.928 0.922 + 0.003*sl 0.923 + 0.003*sl 0.926 + 0.002*sl t phl 1.263 1.255 + 0.004*sl 1.257 + 0.003*sl 1.262 + 0.003*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
samsung asic 4-87 STD111 pci buffers overview pci buffers are designed for pci local bus application which is intended for high-performance 32-bit or 64-bit bus architecture. sec supports pci input, output and bi-directional buffers for 3.3v and 5v signaling environment. features 0.24 m, low-power, high performance cmos technology input, output, and bi-directional pci buffers pci local bus speci?ation rev2.1 compliant operating at up to 66mhz, including 33mhz electrically compliant interface in 3.3v and 5v bus environments description these pci buffers are designed for 3.3v and 5v environments. these buffers are compliant with the pci local bus speci?ation rev2.1. the pci buffers for 66mhz can be available in 33mhz interface, but require more power pads due to their fast and noisy characteristics. the 5v tolerant pci buffers can be used for 33mhz, 5v environment. these tolerant pci buffers require 5v power for bulk of pmos driver for 5v bus environment or 3.3v power for 3.3v environment. the 5v tolerant pci drivers support 5v environment while en5v is low. although tolerant pci buffers support 5v environment, they do not drive 5v. note: if you want to use pci buffers, please contact sec. cell list note1: 3.3v signaling conditions: en5v=high, vio=3.3v, 5v tolerant is not supported. 5v signaling conditions: en5v=low, vio=5v, and 5v tolerant is supported. note2: in 3.3v signaling, vio is 3.3v, which is provided through the vdd5o_pci power cell. in 5v signaling, vio is 5v, which is provided through the vdd5o_pci power cell. cell name description operating frequency operating voltage ptbpci bi-direction up to 33mhz at 5v signaling (note1) up to 66mhz at 3.3v signaling 3.3v ptopci driver up to 33mhz at 5v signaling up to 66mhz at 3.3v signaling ptipci receiver up to 33mhz at 5v signaling up to 66mhz at 3.3v signaling power cell name description vdd2i_pci 2.5v power cell for internal core and pci i/os vdd3op_pci 3.3v power cell for pci i/os vdd5o_pci vio(3.3v or 5v) power cell for pci i/os (note2) vssi_pci gnd power cell for internal core; not used for pci i/os vssop_pci gnd power cell for pci i/os
STD111 4-88 samsung asic pci buffers option (note3) note3: voltage detector circuit will automatically set the en5v pin either high or low according to vio voltage level. electrical characteristics dc characteristics ac characteristics cell name description vdet_111pci 3.3v or 5v voltage detector symbol parameter 3.3v signaling 5v signaling unit condition min max condition min max v cc supply voltage 3.0 3.6 3.0 3.6 v vio vdd5o voltage v cc 4.75 5.25 v v ih input high voltage 0.47v cc v cc +0.5 1.9 vio+0.5 v v il input low voltage ?0.5 0.33v cc ?0.5 0.9 v i i input leakage current 0 < v in < v cc ?0 10 0 < v in < vio ?0 70 a v oh output high voltage i out = ?00 a 0.9v cc ? out = ?ma 2.4 v v ol output low voltage i out = 1500 a 0.1v cc i out = 6ma 0.55 v symbol parameter 3.3v signaling 5v signaling unit condition min max condition min max i oh (ac) switching current high v out = 0.3v cc ?2v cc v out = 1.4v ?4 ma v out = 0.7v cc ?2v cc v out = 2.4v ?2.33 v out = 0.9v cc ?.71v cc v out = 3.0v ?142 i ol (ac) switching current low v out = 0.6v cc 16v cc v out = 2.2v 95 ma v out = 0.1v cc 2.67v cc v out = 0.55v 23.9 v out = 0.18v cc 38v cc v out = 0.71v 206 i cl low clamp current ?3 < v in ? ?5 + (v in +1)/ 0.015 ?5 < v in ? ?5 + (v in + 1) / 0.015 ma i ch high clamp current v cc +1 v in < v cc +4 25 + (v in ? cc ?) / 0.015 ma t r output rise time 0.3v cc to 0.6v cc 1.0 4.0 0.4v to 2.4v 1.0 5.0 v/ns t f output fall time 0.6v cc to 0.3v cc 1.0 4.0 2.4v to 0.4v 1.0 5.0 v/ns
samsung asic 4-89 STD111 ptipci 5v-tolerant pci input buffers logic symbol switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 3.00ns, sl: standard load) ptipci truth table input truth table pa d p i y p o 1110 0x01 1011 pa d y po pi path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.271 0.261 + 0.005*sl 0.261 + 0.005*sl 0.265 + 0.005*sl t f 0.135 0.131 + 0.002*sl 0.132 + 0.002*sl 0.143 + 0.001*sl t plh 0.322 0.318 + 0.002*sl 0.319 + 0.002*sl 0.326 + 0.002*sl t phl 0.798 0.793 + 0.002*sl 0.795 + 0.002*sl 0.818 + 0.001*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
STD111 4-90 samsung asic ptopci 5v-tolerant pci output buffers logic symbol switching characteristics (typical process, 25 c, 2.5v, 3.3v, t r /t f = 0.17ns, cl: capacitive load) ptopci pa d a tn en en5v note: en5v=low: enable the 5v signaling en5v=high: enable the 3.3v signaling path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 2.110 0.782 + 0.026*cl 0.764 + 0.027*cl 0.706 + 0.028*cl t f 2.513 0.718 + 0.035*cl 0.675 + 0.037*cl 0.611 + 0.038*cl t plh 2.452 1.374 + 0.024*cl 1.557 + 0.018*cl 1.663 + 0.016*cl t phl 2.087 0.994 + 0.022*cl 1.039 + 0.021*cl 1.069 + 0.020*cl tn to pad t r 2.111 0.792 + 0.026*cl 0.767 + 0.027*cl 0.707 + 0.028*cl t f 2.289 0.355 + 0.039*cl 0.349 + 0.039*cl 0.337 + 0.039*cl t plh 2.635 1.554 + 0.024*cl 1.739 + 0.018*cl 1.845 + 0.016*cl t phl 2.081 0.981 + 0.023*cl 1.035 + 0.021*cl 1.060 + 0.020*cl t plz 0.727 0.727 + 0.000*cl 0.727 + 0.000*cl 0.727 + 0.000*cl t phz 1.274 1.274 + 0.000*cl 1.273 + 0.000*cl 1.273 + 0.000*cl en to pad t r 2.111 0.792 + 0.026*cl 0.768 + 0.027*cl 0.707 + 0.028*cl t f 2.289 0.354 + 0.039*cl 0.349 + 0.039*cl 0.337 + 0.039*cl t plh 2.693 1.612 + 0.024*cl 1.798 + 0.018*cl 1.904 + 0.016*cl t phl 2.139 1.039 + 0.023*cl 1.094 + 0.021*cl 1.118 + 0.020*cl t plz 0.742 0.742 + 0.000*cl 0.742 + 0.000*cl 0.742 + 0.000*cl t phz 1.289 1.289 + 0.000*cl 1.288 + 0.000*cl 1.288 + 0.000*cl *group1 : cl < 30, *group2 : 30 cl < < = = 50, *group3 : 50 < cl truth table output truth table aentnpad 0010 1011 x 1 x hi-z x x 0 hi-z
samsung asic 4-91 STD111 ptbpci 5v-tolerant pci bidirectional buffer logic symbol option: logic symbol cell data cell name detecting voltage vdet_110pci 3.3v, 5v truth table input truth table output truth table pa d p i y p o 1110 0x01 1011 aentnpad 0010 1011 x 1 x hi-z x x 0 hi-z pa d a tn en y po pi en5v note: en5v=low: enable the 5v signaling en5v=high: enable the 3.3v signaling y pd a truth table input output apdy 3.3v 1 5v 0 x 0 last y x 1 last y
samsung asic 4-92 STD111 usb (universal serial bus) i/o buffers (under development) overview usb i/o buffer consists of a differential input receiver, a differential output driver, two single-ended receivers, and two pads. the differential input receiver has the 0.8v ~ 2.5v common mode input voltage range and both of the two single-ended receivers have 0.8v and 2.0v as their low and high input threshold voltages, v il , v ih , respectively. for low power consumption in a stand-by mode, the suspend pin (suspnd) of the receiver and the driver should be in the high state. the differential output drivers have a low/full speed control pin (speed) to select the operation speed and have output enable negative pin (oen) to achieve a bi-directional half duplex operation. features complies with universal serial bus speci?ation 1.0 supports 12mbps ?ull speed?and 1.5mbps ?ow speed?serial data transmission supports both ?ull speed?and ?ow speed?design kits supports both ?ull speed only?and ?ow speed only?cells to reduce silicon area electrical speci?ations dc electrical characteristics full speed output buffer electrical characteristics parameter symbol condition (notes 1, 2) min max unit supply current suspend device i ccs 10 a leakage current hi-z state input leakage i lo 0v < vin < 3.3v ?0 10 a input levels differential input sensitivity v di i (d+) ? (d-) i 0.2 v differential common mode range v cm includes v di range 0.8 2.5 single ended receiver threshold v se 0.8 2.0 output levels static output low v ol rl of 1.5k ? to 3.6v 0.3 v static output high v oh rl of 15k ? to gnd 2.8 3.6 capacitance transceiver capacitance c in pin to gnd 20 pf parameter symbol condition (notes 1, 2, 3) min max unit driver characteristics transition time rise time fall time t r t f notes 5 and figure 1 cl = 50pf cl = 50pf 4.0 4.0 20.0 20.0 ns rise/fall time matching t rfm (t r /t f ) 90 110 % output signal crossover voltage v crs 1.3 2.0 v drive output resistance z drv steady state drive 28 43 ?
STD111 4-93 samsung asic usb (universal serial bus) i/o buffers (under development) low speed output buffer electrical characteristics notes: 1. all voltages are measured from the local ground potential, unless otherwise speci?d. 2. all timings use a capacitive load (cl) to ground of 50pf, unless otherwise speci?d. 3. full speed timings have a 1.5k ? pull-up to 2.8v on the dp data line. 4. low speed timings have a 1.5k ? pull-up to 2.8v on the dn data line. 5. measured from 10% to 90% of the data signal. figure 1: data signal rise and fall time cell list parameter symbol condition (notes 1, 2, 4) min max unit driver characteristics transition time rise time fall time t r t f notes 5 and figure 1 cl = 50pf cl = 350pf cl = 50pf cl = 350pf 75 75 300 300 ns rise/fall time matching t rfm (t r /t f ) 80 120 % output signal crossover voltage v crs 1.3 2.0 v cell name function description pbusb/pbusb1 low/full speed usb buffer (1.5 mhz/12 mhz select) pbusb_ls low speed only usb buffer (1.5 mhz only, reduced cell size) pbusb_fs full speed only usb buffer (12 mhz only, reduced cell size) c l c l differential data lines 10% 90% 90% 10% rise time fall time t r t f full speed: 4 to 20ns at c l = 50pf low speed: 75ns at c l = 50pf, 300ns at c l = 350pf
STD111 4-94 samsung asic pbusb/pbusb1/pbusb_ls/pbusb_fs (under development) universal serial bus i/o buffer pbusb/pbusb1 symbol pin connection cell structure pbusb = piser + picdr + potls + potfs pbusb1 = piser + picdr + potls + potfs there only exists pbusb not pbusb1 in the physical db. the division of cell name (pbusb/pbusb1) is caused to notify their different working-mode. pbusb selects potls (speed=0) to work on the low speed mode. pbusb1 selects potfs (speed=1) to work on the full speed mode.in case that the physical area is critical, low speed only (pbusb_ls) or full speed only (pbusb_fs) usb io cell would be provided at the request of the customer, i.e. pbusb_ls = piser + picdr + potls pbusb_fs = piser + picdr + potfs input output bi-direction txdp txdn suspnd oen speed rxdp rxdn rxd dp dn rxdp rxdn rxd speed piser picdr potls potfs suspnd txdp oen txdn dp dn
samsung asic 4-95 STD111 pbusb/pbusb1/pbusb_ls/pbusb_fs (under development) universal serial bus i/o buffer pbusb_ls symbol pin connection input output bi-direction txdp txdn suspnd oen speed rxdp rxdn rxd dp dn rxdp rxdn rxd speed piser picdr potls suspnd txdp oen txdn dp dn
STD111 4-96 samsung asic pbusb/pbusb1/pbusb_ls/pbusb_fs (under development) universal serial bus i/o buffer pbusb_fs symbol pin connection input output bi-direction txdp txdn suspnd oen speed rxdp rxdn rxd dp dn rxdp rxdn rxd speed piser picdr potfs suspnd txdp oen txdn dp dn
samsung asic 4-97 STD111 pbusb/pbusb1/pbusb_ls/pbusb_fs (under development) universal serial bus i/o buffer piser single-ended receiver symbol switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.80ns, sl: standard load) piser pin connection truth table input output dp dn rxdp rxdn dp dn rxdp rxdn 0000 0101 1010 1111 rxdp rxdn dp dn path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* dp to rxdp t r 0.109 0.094 + 0.008*sl 0.092 + 0.008*sl 0.080 + 0.008*sl t f 0.103 0.086 + 0.008*sl 0.087 + 0.008*sl 0.076 + 0.008*sl t plh 0.598 0.587 + 0.005*sl 0.591 + 0.004*sl 0.599 + 0.004*sl t phl 0.585 0.573 + 0.006*sl 0.579 + 0.005*sl 0.595 + 0.004*sl dn to rxdn t r 0.109 0.094 + 0.008*sl 0.092 + 0.008*sl 0.080 + 0.008*sl t f 0.103 0.086 + 0.008*sl 0.087 + 0.008*sl 0.076 + 0.008*sl t plh 0.598 0.587 + 0.005*sl 0.591 + 0.004*sl 0.599 + 0.004*sl t phl 0.585 0.573 + 0.006*sl 0.579 + 0.005*sl 0.595 + 0.004*sl *group1 : sl < 4, *group2 : 4 sl 60, *group3 : 60 < sl < < = =
STD111 4-98 samsung asic pbusb/pbusb1/pbusb_ls/pbusb_fs (under development) universal serial bus i/o buffer picdr differential receiver symbol switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.80ns, sl: standard load) picdr rxd suspnd dp dn path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* dp to rxd t r 0.198 0.179 + 0.010*sl 0.186 + 0.008*sl 0.168 + 0.008*sl t f 0.188 0.167 + 0.010*sl 0.187 + 0.006*sl 0.252 + 0.005*sl t plh 9.606 9.588 + 0.009*sl 9.604 + 0.005*sl 9.656 + 0.004*sl t phl 8.896 8.876 + 0.010*sl 8.897 + 0.005*sl 9.013 + 0.003*sl dn to rxd t r 0.213 0.192 + 0.010*sl 0.203 + 0.008*sl 0.190 + 0.008*sl t f 0.219 0.195 + 0.012*sl 0.219 + 0.006*sl 0.303 + 0.005*sl t plh 3.600 3.578 + 0.011*sl 3.602 + 0.006*sl 3.677 + 0.004*sl t phl 4.510 4.487 + 0.011*sl 4.510 + 0.006*sl 4.647 + 0.004*sl suspnd to rxd t r 0.168 0.150 + 0.009*sl 0.154 + 0.008*sl 0.133 + 0.008*sl t f 0.226 0.200 + 0.013*sl 0.226 + 0.007*sl 0.337 + 0.005*sl t plh 1.360 1.344 + 0.008*sl 1.358 + 0.005*sl 1.404 + 0.004*sl t phl 1.628 1.604 + 0.012*sl 1.628 + 0.007*sl 1.779 + 0.004*sl *group1 : sl < 4, *group2 : 4 sl 60, *group3 : 60 < sl < < = = pin connection truth table input output dp dn suspnd rxd dp dn suspnd rxd 0000 0100 1001 110x xx10
samsung asic 4-99 STD111 pbusb/pbusb1/pbusb_ls/pbusb_fs (under development) universal serial bus i/o buffer po tls tri-state output buffer with low speed symbol truth table note: suspnd is the suspend mode control signal for the output driver. suspnd=1 or oen=1, both low speed driver and full speed driver are suspended. speed is the low/full speed output mode selecting signal, speed=0, suspnd=0, oen=0 low speed mode transmitting. txdp txdn suspnd oen speed dp dn 0000000 0100001 1000010 1100011 x x 1 x x hi-z hi-z x x x 1 x hi-z hi-z x x x x 1 hi-z hi-z speed suspnd txdp oen txdn dp dn pin connection input output txdp txdn speed suspnd oen dp dn
STD111 4-100 samsung asic pbusb/pbusb1/pbusb_ls/pbusb_fs (under development) universal serial bus i/o buffer switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.80ns, cl: capacitive load) potls path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* txdp to dp t r 116.330 115.030 + 0.026*cl 120.870 + 0.000*cl 122.130 + 0.000*cl t f 135.200 135.200 + 0.000*cl 122.110 + 0.053*cl 135.790 + 0.000*cl t plh 111.850 111.850 + 0.000*cl 105.020 + 0.078*cl 104.630 + 0.083*cl t phl 112.920 108.320 + 0.092*cl 119.180 + 0.000*cl 109.490 + 0.004*cl oen to dp t r 114.230 114.230 + 0.000*cl 113.240 + 0.009*cl 113.210 + 0.009*cl t f 129.430 129.430 + 0.000*cl 131.350 + 0.000*cl 127.390 + 0.000*cl t plh 79.258 79.258 + 0.000*cl 77.803 + 0.028*cl 73.459 + 0.086*cl t phl 113.000 108.925 + 0.081*cl 110.840 + 0.043*cl 119.360 + 0.000*cl t plz 2.272 2.272 + 0.000*cl 2.272 + 0.000*cl 2.272 + 0.000*cl t phz 2.474 2.474 + 0.000*cl 2.473 + 0.000*cl 2.474 + 0.000*cl speed to dp t r 114.230 114.230 + 0.000*cl 113.220 + 0.009*cl 113.190 + 0.010*cl t f 129.355 129.355 + 0.000*cl 131.370 + 0.000*cl 127.380 + 0.000*cl t plh 79.233 79.233 + 0.000*cl 77.772 + 0.028*cl 73.473 + 0.086*cl t phl 113.010 108.910 + 0.082*cl 110.990 + 0.040*cl 119.270 + 0.000*cl t plz 2.261 2.261 + 0.000*cl 2.261 + 0.000*cl 2.261 + 0.000*cl t phz 2.455 2.455 + 0.000*cl 2.458 + 0.000*cl 2.454 + 0.000*cl suspnd to dp t r 114.230 114.230 + 0.000*cl 113.220 + 0.009*cl 113.190 + 0.010*cl t f 129.395 129.395 + 0.000*cl 131.340 + 0.000*cl 127.380 + 0.000*cl t plh 79.047 79.047 + 0.000*cl 77.598 + 0.028*cl 73.290 + 0.086*cl t phl 112.830 108.730 + 0.082*cl 110.830 + 0.040*cl 119.050 + 0.000*cl t plz 2.084 2.084 + 0.000*cl 2.084 + 0.000*cl 2.084 + 0.000*cl t phz 2.284 2.283 + 0.000*cl 2.285 + 0.000*cl 2.284 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl 75, *group3 : 75 < cl < < = =
samsung asic 4-101 STD111 pbusb/pbusb1/pbusb_ls/pbusb_fs (under development) universal serial bus i/o buffer po tfs tri-state output buffer with full speed symbol truth table note: suspnd is the suspend mode control signal for the output driver. suspnd=1 or oen=1, both low speed driver and full speed driver are suspended. speed is the low/full speed output mode selecting signal, speed=1, suspnd=0, oen=0 low speed mode transmitting. txdp txdn suspnd oen speed dp dn 0000100 0100101 1000110 1100111 x x 1 x x hi-z hi-z x x x 1 x hi-z hi-z x x x x 0 hi-z hi-z speed suspnd txdp oen txdn dp dn pin connection input output txdp txdn speed suspnd oen dp dn
STD111 4-102 samsung asic pbusb/pbusb1/pbusb_ls/pbusb_fs (under development) universal serial bus i/o buffer switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load) potfs path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* txdp to dp t r 7.537 4.664 + 0.057*cl 5.798 + 0.035*cl 5.770 + 0.035*cl t f 7.794 4.733 + 0.061*cl 5.879 + 0.038*cl 5.900 + 0.038*cl t plh 7.961 5.205 + 0.055*cl 6.073 + 0.038*cl 5.998 + 0.039*cl t phl 7.565 5.466 + 0.042*cl 5.457 + 0.042*cl 6.008 + 0.035*cl oen to dp t r 7.878 5.429 + 0.049*cl 5.129 + 0.055*cl 5.407 + 0.051*cl t f 7.602 4.896 + 0.054*cl 4.948 + 0.053*cl 5.180 + 0.050*cl t plh 7.628 5.244 + 0.048*cl 4.558 + 0.061*cl 5.973 + 0.043*cl t phl 7.809 5.049 + 0.055*cl 5.525 + 0.046*cl 4.734 + 0.056*cl t plz 1.251 1.251 + 0.000*cl 1.251 + 0.000*cl 1.248 + 0.000*cl t phz 1.851 1.850 + 0.000*cl 1.851 + 0.000*cl 1.851 + 0.000*cl speed to dp t r 7.678 3.979 + 0.074*cl 5.169 + 0.050*cl 5.687 + 0.043*cl t f 7.842 3.786 + 0.081*cl 5.228 + 0.052*cl 5.699 + 0.046*cl t plh 7.969 5.082 + 0.058*cl 5.499 + 0.049*cl 5.714 + 0.047*cl t phl 7.830 5.117 + 0.054*cl 5.686 + 0.043*cl 5.014 + 0.052*cl suspnd to dp t r 7.578 5.329 + 0.045*cl 5.629 + 0.039*cl 5.906 + 0.035*cl t f 7.882 5.476 + 0.048*cl 5.788 + 0.042*cl 6.080 + 0.038*cl t plh 7.940 5.053 + 0.058*cl 5.470 + 0.049*cl 5.985 + 0.043*cl t phl 7.621 4.605 + 0.060*cl 5.257 + 0.047*cl 5.309 + 0.047*cl t plz 1.046 1.046 + 0.000*cl 1.045 + 0.000*cl 1.046 + 0.000*cl t phz 1.646 1.646 + 0.000*cl 1.646 + 0.000*cl 1.646 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-103 samsung asic power pads cell list cell name function description vdd power pads vss power pads vdd2i vss2i 2.5v internal vdd2p vss2p 2.5v pre-driver vdd2o vss2o 2.5v output-driver vdd2ip vss2ip 2.5v internal and pre-driver vdd2op vss2op 2.5v output-driver and pre-driver vdd2t vss2t 2.5v total vdd3p vss3p 3.3v pre-driver vdd3o vss3o 3.3v output-driver vdd3op vss3op 3.3v output-driver and pre-driver logic symbol cell name function description vdd power pads vss power pads vdd2i_abb vss2i_abb 2.5v internal with separate bulk bias vdd2op_abb vss2op_abb 2.5v pre-driver and output-driver with separate bulk bias vdd2t_abb vss2t_abb 2.5v total with separate bulk bias vbb_abb bulk bias power pad vssbb_abb bulk bias and vss power pad logic symbol
samsung asic 4-104 STD111 analog interface analog input analog output cell name function description pic_abb analog cmos level input buffer separate bulk-bias picc_abb analog cmos level input buffer separate bulk-bias and without nand-tree picen_abb analog cmos level input buffer with enable port and separate bulk-bias cell name function description pot1_abb analog tri-state output buffer with separate bulk bias, 1ma drive pot2_abb analog tri-state output buffer with separate bulk bias, 2ma drive pot4_abb analog tri-state output buffer with separate bulk bias, 4ma drive pot8_abb analog tri-state output buffer with separate bulk bias, 8ma drive
samsung asic 4-105 STD111 pic_abb analog cmos level input buffers with separate bulk-bias logic symbol switching characteristics (typical process, 25 c, 2.5v, t r /t f = 3.00ns, sl: standard load) pic_abb truth table standard load (sl) pa d p i y p o 1110 0x01 1011 cell name pi pic_abb 3.620 y po pi pa d path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.205 0.186 + 0.010*sl 0.186 + 0.010*sl 0.166 + 0.010*sl t f 0.149 0.136 + 0.006*sl 0.138 + 0.006*sl 0.125 + 0.006*sl t plh 1.051 1.036 + 0.007*sl 1.042 + 0.005*sl 1.059 + 0.005*sl t phl 0.991 0.979 + 0.006*sl 0.986 + 0.004*sl 1.014 + 0.003*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
STD111 4-106 samsung asic picc_abb analog cmos level input buffers with separate bulk-bias logic symbol switching characteristics (typical process, 25 c, 2.5v, t r /t f = 3.00ns, sl: standard load) picc_abb truth table pa d y 00 11 y pa d path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.176 0.157 + 0.010*sl 0.157 + 0.009*sl 0.126 + 0.010*sl t f 0.127 0.112 + 0.007*sl 0.119 + 0.006*sl 0.106 + 0.006*sl t plh 1.027 1.010 + 0.008*sl 1.019 + 0.006*sl 1.044 + 0.005*sl t phl 0.973 0.960 + 0.007*sl 0.969 + 0.004*sl 1.003 + 0.003*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
samsung asic 4-107 STD111 picen_abb analog cmos level input buffers with enable port and separate bulk-bias logic symbol switching characteristics (typical process, 25 c, 2.5v, t r /t f = 3.00ns, sl: standard load) picen_abb truth table standard load (sl) pa d p i e n y p o 11110 0x101 10111 xx001 cell name pi en picen_abb 2.897 2.897 y po pi pa d en path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t r 0.231 0.211 + 0.010*sl 0.212 + 0.010*sl 0.198 + 0.010*sl t f 0.177 0.164 + 0.007*sl 0.167 + 0.006*sl 0.166 + 0.006*sl t plh 1.104 1.088 + 0.008*sl 1.096 + 0.006*sl 1.128 + 0.005*sl t phl 1.174 1.160 + 0.007*sl 1.169 + 0.004*sl 1.212 + 0.003*sl en to y t r 0.176 0.155 + 0.011*sl 0.156 + 0.010*sl 0.152 + 0.010*sl t f 0.131 0.117 + 0.007*sl 0.120 + 0.006*sl 0.121 + 0.006*sl t plh 0.315 0.301 + 0.007*sl 0.306 + 0.005*sl 0.323 + 0.005*sl t phl 0.329 0.318 + 0.006*sl 0.323 + 0.004*sl 0.352 + 0.003*sl *group1 : sl < 3, *group2 : 3 sl < < = = 45, *group3 : 45 < sl
STD111 4-108 samsung asic pot1/2/4/8_abb analog tri-state output buffers with enable port and separate bulk-bias logic symbol switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load) pot1_abb truth table standard load (sl) tn en a pad 100 0 101 1 x 1 x hi - z 0 x x hi - z cell name tn en a pot1_abb 2.898 2.916 3.023 pot2_abb 2.898 2.916 3.023 pot4_abb 2.898 2.916 3.023 pot8_abb 2.898 2.916 3.023 en pa d a tn path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 32.056 1.759 + 0.606*cl 1.758 + 0.606*cl 1.761 + 0.606*cl t f 33.870 1.873 + 0.640*cl 1.872 + 0.640*cl 1.872 + 0.640*cl t plh 16.015 1.507 + 0.290*cl 1.507 + 0.290*cl 1.507 + 0.290*cl t phl 17.839 1.729 + 0.322*cl 1.731 + 0.322*cl 1.731 + 0.322*cl tn to pad t r 32.056 1.759 + 0.606*cl 1.758 + 0.606*cl 1.761 + 0.606*cl t f 33.870 1.873 + 0.640*cl 1.872 + 0.640*cl 1.872 + 0.640*cl t plh 16.063 1.553 + 0.290*cl 1.557 + 0.290*cl 1.554 + 0.290*cl t phl 17.962 1.852 + 0.322*cl 1.854 + 0.322*cl 1.851 + 0.322*cl t plz 0.958 0.958 + 0.000*cl 0.958 + 0.000*cl 0.958 + 0.000*cl t phz 0.662 0.662 + 0.000*cl 0.662 + 0.000*cl 0.662 + 0.000*cl en to pad t r 32.056 1.759 + 0.606*cl 1.758 + 0.606*cl 1.761 + 0.606*cl t f 33.870 1.873 + 0.640*cl 1.872 + 0.640*cl 1.872 + 0.640*cl t plh 16.165 1.658 + 0.290*cl 1.657 + 0.290*cl 1.660 + 0.290*cl t phl 18.064 1.957 + 0.322*cl 1.954 + 0.322*cl 1.957 + 0.322*cl t plz 1.000 1.000 + 0.000*cl 1.000 + 0.000*cl 1.000 + 0.000*cl t phz 0.705 0.705 + 0.000*cl 0.705 + 0.000*cl 0.705 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-109 STD111 pot1/2/4/8_abb analog tri-state output buffers with enable port and separate bulk-bias switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load) pot2_abb switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load) pot4_abb path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 16.047 0.897 + 0.303*cl 0.899 + 0.303*cl 0.899 + 0.303*cl t f 18.535 1.010 + 0.350*cl 1.011 + 0.350*cl 1.011 + 0.350*cl t plh 8.431 1.177 + 0.145*cl 1.177 + 0.145*cl 1.177 + 0.145*cl t phl 10.353 1.235 + 0.182*cl 1.233 + 0.182*cl 1.236 + 0.182*cl tn to pad t r 16.047 0.897 + 0.303*cl 0.899 + 0.303*cl 0.899 + 0.303*cl t f 18.535 1.010 + 0.350*cl 1.011 + 0.350*cl 1.011 + 0.350*cl t plh 8.479 1.224 + 0.145*cl 1.224 + 0.145*cl 1.228 + 0.145*cl t phl 10.477 1.357 + 0.182*cl 1.357 + 0.182*cl 1.360 + 0.182*cl t plz 0.808 0.808 + 0.000*cl 0.808 + 0.000*cl 0.808 + 0.000*cl t phz 0.768 0.768 + 0.000*cl 0.768 + 0.000*cl 0.768 + 0.000*cl en to pad t r 16.047 0.897 + 0.303*cl 0.899 + 0.303*cl 0.899 + 0.303*cl t f 18.535 1.010 + 0.350*cl 1.011 + 0.350*cl 1.011 + 0.350*cl t plh 8.581 1.327 + 0.145*cl 1.327 + 0.145*cl 1.327 + 0.145*cl t phl 10.580 1.460 + 0.182*cl 1.462 + 0.182*cl 1.462 + 0.182*cl t plz 0.851 0.851 + 0.000*cl 0.851 + 0.000*cl 0.851 + 0.000*cl t phz 0.810 0.810 + 0.000*cl 0.810 + 0.000*cl 0.810 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 8.054 0.484 + 0.151*cl 0.480 + 0.151*cl 0.480 + 0.151*cl t f 9.284 0.522 + 0.175*cl 0.521 + 0.175*cl 0.522 + 0.175*cl t plh 4.795 1.167 + 0.073*cl 1.168 + 0.073*cl 1.168 + 0.073*cl t phl 5.607 1.048 + 0.091*cl 1.048 + 0.091*cl 1.048 + 0.091*cl tn to pad t r 8.054 0.484 + 0.151*cl 0.480 + 0.151*cl 0.480 + 0.151*cl t f 9.284 0.522 + 0.175*cl 0.521 + 0.175*cl 0.522 + 0.175*cl t plh 4.842 1.214 + 0.073*cl 1.215 + 0.073*cl 1.216 + 0.073*cl t phl 5.729 1.168 + 0.091*cl 1.169 + 0.091*cl 1.170 + 0.091*cl t plz 0.940 0.940 + 0.000*cl 0.940 + 0.000*cl 0.940 + 0.000*cl t phz 0.978 0.978 + 0.000*cl 0.978 + 0.000*cl 0.978 + 0.000*cl en to pad t r 8.054 0.484 + 0.151*cl 0.480 + 0.151*cl 0.480 + 0.151*cl t f 9.284 0.522 + 0.175*cl 0.521 + 0.175*cl 0.522 + 0.175*cl t plh 4.945 1.318 + 0.073*cl 1.318 + 0.073*cl 1.318 + 0.073*cl t phl 5.832 1.271 + 0.091*cl 1.272 + 0.091*cl 1.274 + 0.091*cl t plz 0.982 0.982 + 0.000*cl 0.982 + 0.000*cl 0.982 + 0.000*cl t phz 1.020 1.020 + 0.000*cl 1.020 + 0.000*cl 1.020 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
STD111 4-110 samsung asic pot1/2/4/8_abb analog tri-state output buffers with enable port and separate bulk-bias switching characteristics (typical process, 25 c, 2.5v, t r /t f = 0.17ns, cl: capacitive load) pot8_abb path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t r 4.117 0.414 + 0.074*cl 0.368 + 0.075*cl 0.336 + 0.075*cl t f 4.673 0.309 + 0.087*cl 0.297 + 0.088*cl 0.292 + 0.088*cl t plh 3.256 1.437 + 0.036*cl 1.441 + 0.036*cl 1.442 + 0.036*cl t phl 3.352 1.084 + 0.045*cl 1.078 + 0.045*cl 1.074 + 0.046*cl tn to pad t r 4.117 0.414 + 0.074*cl 0.368 + 0.075*cl 0.336 + 0.075*cl t f 4.672 0.307 + 0.087*cl 0.295 + 0.088*cl 0.290 + 0.088*cl t plh 3.304 1.484 + 0.036*cl 1.489 + 0.036*cl 1.490 + 0.036*cl t phl 3.464 1.180 + 0.046*cl 1.183 + 0.046*cl 1.184 + 0.046*cl t plz 1.195 1.195 + 0.000*cl 1.195 + 0.000*cl 1.195 + 0.000*cl t phz 1.397 1.397 + 0.000*cl 1.397 + 0.000*cl 1.397 + 0.000*cl en to pad t r 4.117 0.414 + 0.074*cl 0.369 + 0.075*cl 0.336 + 0.075*cl t f 4.672 0.307 + 0.087*cl 0.295 + 0.088*cl 0.291 + 0.088*cl t plh 3.406 1.588 + 0.036*cl 1.592 + 0.036*cl 1.592 + 0.036*cl t phl 3.567 1.284 + 0.046*cl 1.285 + 0.046*cl 1.287 + 0.046*cl t plz 1.238 1.238 + 0.000*cl 1.238 + 0.000*cl 1.238 + 0.000*cl t phz 1.439 1.439 + 0.000*cl 1.439 + 0.000*cl 1.439 + 0.000*cl *group1 : cl < 50, *group2 : 50 cl < < = = 75, *group3 : 75 < cl
samsung asic 4-111 STD111 esd slot cells cell list note: all of slot cells have no pad and can be added automatically by using sec utility cubicplan. cell name function description ev2i 2.5v internal esd protection ev2p 2.5v pre-driver esd protection ev2o 2.5v output-driver esd protection ev2ip 2.5v internal and pre-driver esd protection ev2op 2.5v output-driver and pre-driver esd protection ev2t 2.5v total esd protection ev3p 3.3v pre-driver esd protection ev3o 3.3v output-driver esd protection ev3op 3.3v output-driver and pre-driver esd protection ev2i_abb 2.5v internal esd protection with separated bulk-bias ev2op_abb 2.5v output-driver and pre-driver esd protection with separated bulk-bias ev2t_abb 2.5v total esd protection with separated bulk-bias
samsung asic 4-112 STD111 common slot cells cell list notes: 1. if cdl ring connected with bi-directional diode, esd protection level can be dropped. 2. if analog blocks have only one vbb power pad, metal connected vbb ring type should be used. 3. all of slot cells can be added automatically by using sec utility cubicplan, or by manual. cell name function description ec0c0 metal ring separator between different digital blocks ec0c0d 1 metal ring separator between different digital blocks for noise critical design ec0ca0 metal ring separator between digital to analog ec0ca0d 1 metal ring separator between digital to analog for noise critical design ec0c0_bb metal ring separator between different analog blocks with vbb ring separated ec0c0d_bb 1 metal ring separator between different analog blocks for noise critical design with vbb ring separated ec0c0_vbb 2 metal ring separator between different analog blocks with vbb ring connected ec0c0d_vbb 1,2 metal ring separator between different analog blocks for noise critical design with vbb ring connected
5 compiled macrocells
contents overview to compiled memory ............................................................................................ 5-1 compiled memory naming convention................................................................................ 5-1 characteristics for timing and power................................................................................... 5-2 built-in self test for compiled memory ................................................................................ 5-3 selection guide for compiled memory................................................................................. 5-4 high-density compiled memory spsram_hd high-density single-port synchronous sram ....................................... 5-7 spsrambw_hd high-density single-port synchronous sram with bit-write................. 5-17 dpsram_hd high-density dual-port synchronous sram.......................................... 5-27 sparam_hd high-density single-port asynchronous sram ..................................... 5-37 drom_hd high-density synchronous diffusion programmable rom .................... 5-48 mrom_hd high-density synchronous metal programmable rom.......................... 5-56 arfram_hd high-density multi-port asynchronous register file.............................. 5-64 fifo_hd high-density synchronous first-in first-out memory............................ 5-83 low-power compiled memory spsram_lp low power single-port synchronous sram .......................................... 5-95 dpsram_lp low power dual-port synchronous sram............................................. 5-105 sparam_lp low power single-port asynchronous sram ........................................ 5-115 drom_lp low power synchronous diffusion programmable rom ....................... 5-125 mrom_lp low power synchronous metal programmable rom............................. 5-133 overview to compiled datapath .......................................................................................... 5-141 compiled macrocell selection guide ................................................................................... 5-142 adder adder/subtracter..................................................................................... 5-143 bs barrel shifter........................................................................................... 5-148 mpy modi?ed booth multiplier ........................................................................ 5-153
compiled macrocells overview to compiled memory samsung asic 5-1 STD111 overview to compiled memory this section contains the overview of STD111 compiled memory. in STD111 compiled memory, we provide application-speci?c memory solution - high-density and low-power application. that is, two different library set of compiled memory are available in STD111 cell library. one is the high-density compiled memory, called STD111-hd compiled memory and the other is the low-power compiled memory, called STD111-lp compiled memory. the high-density compiled memories are suitable for high integration application with high-performance whereas the low-power compiled memories are suitable for portable applications. these are complete memories that are customized to satisfy the requirements of the circuit at hand. depending on the function to be generated, the ?nal memory will be implemented as a stand-alone, pitch-matched and customized leafcells. in addition, to implement optimized memory, we apply the state-of-the-art design architecture techniques. in STD111 cell library, the compiled memory is fully generated by a user-con?gurable compiler, called memory compiler. it allows you to con?gure a memory through memory-related speci?cation such as word depth, bit per word, column mux type and so on. the compiler allows you to select and customize any of memory to satisfy the speci?c circuit requirements. when the required speci?cations have been fully given, you may get any or all of the following items: area-optimized and speed-optimized layout blocks schematic netlist for simulation and veri?cation phantom cell to use in chip-level layout tabular model for timing and power characteristics automatic datasheet for a speci?c instance for more detailed information regarding to memory compiler, contact your local representative or headquarters. compiled memory naming convention the naming convention of compiled memory in this section will be shown as figure 5-1. the memory name consists of the following convention. figure 5-1. compiled memory naming convention the ?rst string, memory_code, means the name of memory type. in STD111 compiled memory, the available memory types are as follows: ? spsram : single-port synchronous sram ? spsrambw : single-port synchronous sram with bit-write ? dpsram : dual-port synchronous sram ? sparam : single-port asynchronous sram ? drom : synchronous diffusion-programmable rom ? mrom : synchronous metal-programmable rom ? arfram : multi-port asynchronous register file ? fifo : synchronous first-in first-out memory [memory_code]_[appl_code]_[opt_code]_[con?g_code]
characteristics for timing and power compiled macrocells STD111 5-2 samsung asic the second string, appl_code, means the speci?c application to suitably support the compiled memory and the application code is one of hd (high-density), lp (low-power) and hs (high-speed). in STD111 compiled memory, the high-speed compiled memory is not supported as another library set. instead, the high-density compiled memory can be applied for the high-performance application. the third string, opt_code, represents the number of read and write ports for multi-port memory and the option code is composed of the following convention: opt_code = rw currently this ?eld is only used for arfram, where n is the total number of read ports (1~2) and m is the total number of write ports (1~2). the last string, con?g_code, represents the con?guration of the memory to be speci?ed. this con?guration code is composed of the following convention: x m b here, word is the word depth, bpw is bit per word, ymux is the available column mux type and bank is the number of bank to be used. for example, spsram_hd_1024x32m16b2 refers to a high-density single-port synchronous sram with 1024 words, 32 bits, 16 column mux and 2 bank. second, arfram_hd_1r2w_32x32m2 refers to a high-density three-port (1 read/2 write) asynchronous register ?le with 32 word, 32 bits and 2 column mux and spsram_lp_1024x32m16b2 refers to a low-power single-port synchronous sram with 1024 words, 32 bits, 16 column mux and 2 bank. characteristics for timing and power STD111-hd compiled memory is only supported at 2.5v supply voltage whereas STD111-lp compiled memory is supported at both 2.5v supply voltage and 1.8v supply voltage. compiled memory in this section has been characterized using typical-case at 25 degree and 2.5v supply. the values of worst-case or best-case can be derived by using derating factors provided in chapter 1. for the timing characteristics, 2-dimensional table look-up model has been adopted to yield more accuracy. based on the combination of input slopes and output loads, the propagation delay is measured from the input crossing 50% vdd to the output crossing 50% vdd. the timing values reported in the tables are also taken from the same voltage level as the switching characteristics with 0.2ns for input slope and 10sl(standard load) for output load. for the power characteristics, the average power consumption is measured on the condition that input slope is 0.2ns and output load is 10sl. also, the power consumption depends on input switching activity. the power values reported in the tables are also taken from 50% input switching activity. for compiled memory macrocells, average read power consumption, average write power consumption and average standby power consumption are available, except that the standby power consumption is not available in arfram and fifo. average standby power consumption is measured on the condition that csn (chip select negative) is in disable mode and other signals are in normal operation mode. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while disabling csn signal, if possible. in dual-port memory, the average power consumption is measured on the condition that only one port is in active mode and the other port is isolated.
compiled macrocells built-in self test for compiled memory samsung asic 5-3 STD111 built-in self test for compiled memory sec provides engineering design services to support built-in self-test (bist) for the compiled memory macrocell. bist circuits are designed to detect a set of fault types, such as stuck-at faults, transition faults, coupling faults and address decoder faults that adversely impact the functionality of the memory block. as shown in figure 5-2, sec adopts bist architecture which is called soa (single ordered addressing) algorithm. figure 5-2. memory bist architecture from figure 5-2, although several memory macrocells of the same types or the different types exist together in a circuit, sec supports it as single bist architecture. for more detailed information regarding to the bist for compiled memory macrocells, please contact your local representative or headquarters. ram0 ramm rams bist logic test enable control signal clk bist_mode . . . diag errorb done ram1
selection guide for compiled memory compiled macrocells STD111 5-4 samsung asic selection guide for compiled memory STD111-hd (high-density) compiled memory application memory type description high-density with high- performance spsram_hd - high-density single-port synchronous static ram - positive-edge clock operation - dual bank available - flexible aspect ratio (ymux = 4, 8, 16, 32) spsrambw_hd - high-density single-port synchronous static ram with bit-write - positive-edge clock operation - dual bank available - flexible aspect ratio (ymux = 4, 8, 16, 32) dpsram_hd - high-density dual-port synchronous static ram - positive-edge clock operation - flexible aspect ratio (ymux = 2, 4, 8, 16) sparam_hd - high-density single-port asynchronous static ram - synchronous write operation / asynchronous read operation - dual bank available - flexible aspect ratio (ymux = 2, 4, 8, 16, 32) drom_hd - high-density synchronous diffusion programmable rom - diffusion programmable coded - positive-edge clock operation - dual bank available - flexible aspect ratio (ymux = 8, 16, 32) mrom_hd - high-density synchronous metal programmable rom - metal-2 programmable coded - positive-edge clock operation - dual bank available - flexible aspect ratio (ymux = 8, 16, 32) arfram_hd - high-density multi-port asynchronous register file - synchronous write operation / asynchronous read operation - 1-to-2 write ports / 1-to-2 read ports - flexible aspect ratio (ymux = 2,4,8) fifo_hd - high-density synchronous first-in first-out memory - positive-edge clock operation - reset and re-transmit operation available - flexible aspect ratio (ymux = 4, 8, 16, 32)
compiled macrocells selection guide for compiled memory samsung asic 5-5 STD111 STD111-lp (low-power) compiled memory application memory type description low-power spsram_lp - low-power single-port synchronous static ram - positive-edge clock operation - dual bank available - flexible aspect ratio (ymux = 4, 8, 16, 32) dpsram_lp - low-power dual-port synchronous static ram - positive-edge clock operation - flexible aspect ratio (ymux = 4, 8, 16, 32) sparam_lp - low-power single-port asynchronous static ram - synchronous write operation / asynchronous read operation - dual bank available - flexible aspect ratio (ymux = 4, 8, 16, 32) drom_lp - low-power synchronous diffusion programmable rom - diffusion programmable coded - positive-edge clock operation - dual bank available - flexible aspect ratio (ymux = 8, 16, 32) mrom_lp - low-power synchronous metal programmable rom - metal-2 programmable coded - positive-edge clock operation - dual bank available - flexible aspect ratio (ymux = 8, 16, 32)
STD111 5-6 samsung asic note
samsung asic 5-7 STD111 spsram_hd high density single-port synchronous static ram logic symbol function description spsram_hd is a single-port synchronous static ram which is provided as a compiler. spsram_hd is intended for use in high-density applications. on the rising edge of ck, the write cycle is initiated when wen is low and csn is low. the data on di[] is written into the memory location speci?ed on a[]. during the write cycle, dout[] remains stable. on the rising edge of ck, the read cycle is initiated when wen is high and csn is low. the data at dout[] become valid after a delay. while in standby mode that csn is high, data stored in the memory is retained and dout[] remains stable. when oen is high, dout[] is placed in a high-impedance state. parameter description spsram_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bits per word(b), column mux(y) and number of banks(ba). ck csn wen oen a di dout comment x x x h x x z unconditional tri-state output x h x l x x dout(t-1) de-selected (standby mode) - l l l valid valid dout(t-1) write cycle - l h l valid x mem(a) read cycle ck csn wen oen a [mC1:0] spsram_hd_xmb dout [bC1:0] di [bC1:0] notes: 1. words(w) is the number of words in spsram_hd. 2. bpw(b) is the number of bits per word. 3. ymux(y) is one of the column mux types. 4. banks(ba) is the number of banks. 5. m = log 2 w features ? suitable for high-density application ? separated data i/o ? synchronous operation ? duty-free clock cycle ? asynchronous tri-state output control ? latched inputs and outputs ? automatic power-down ? zero standby current ? low noise output optimization ? flexible aspect ratio ? dual-bank scheme available ? up to 256kbits capacity ? up to 16k number of words ? up to 128 number of bits per word
STD111 5-8 samsung asic spsram_hd high density single-port synchronous static ram pin descriptions pin capacitance unit: [sl] note: each pins capacitance is exactly same regardless of available mux types for same bank. parameters ymux = 4 ymux = 8 ymux = 16 ymux = 32 words (w) ba = 1 min 32 64 128 256 max 1024 2048 4096 8192 step 16 32 64 128 ba = 2 min 64 128 256 512 max 2048 4096 8192 16384 step 32 64 128 256 bpw (b) min 1 1 1 1 max 128 64 32 16 step 1 1 1 1 name i/o description ck clock clock input. csn, wen, a[] and di[] are latched into the ram on the rising edge of ck. if csn and wen are low on the rising edge of ck, the ram is in write mode. if csn is low and wen is high on the rising edge of ck, the ram is in read mode. csn chip enable chip enable input. the chip enable is active-low and is latched into the ram on the rising edge of ck. when csn is low, the ram is enabled for reading or writ- ing, depending on the state of wen. when csn is high, the ram goes to the standby mode and is disabled for reading or writing. dout remains previous data output. wen read/write enable read or write enable input. the read/write enable is latched into the ram on the rising edge of ck. when wen is low, data are written to the addressed location and dout remains stable. when wen is high, data from the addressed word are presented at dout. oen data output enable data output enable input. the data output enable is asynchronously operated regardless of the state of other inputs. when oen is high, dout is disabled and goes to high-impedance state. a [ ] address address input bus. the address is latched into the ram on the rising edge of ck. di [ ] data input data input bus. data are latched on the rising edge of ck. data input is written into the addressed location in write mode. dout [ ] data output data output bus. data output is valid after the rising edge of ck while the ram is in read mode. data output remains previous data output while the ram is in write mode. ck csn wen oen a di dout ba = 1 9.08 7.03 6.95 4.73 7.14 4.26 8.79 ba = 2 9.08 7.03 6.95 4.73 7.14 4.26 8.79
samsung asic 5-9 STD111 spsram_hd high density single-port synchronous static ram block diagrams spsram_hd has 2 different physical architectures due to the word depth. for a speci?c con?guration, only one of these architectures is generated from spsram_hd compiler. in dual bank, the bank selected by the address is only activated while the other bank is in idle mode. application notes 1. permitting over-the-cell routing. in chip-level layout, over-the-cell routing in spsram_hd is permitted only for metal-5 layer. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of spsram_hd. 4. power reduction during standby mode. the standby power is measured on the condition that only csn is in disable mode and other signals are in operation mode. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while standby mode. <1-bank> ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. i/o driver address & clock buffers i/o driver <2-bank> ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. y-dec & sense amp. control block y-dec & sense amp. ram core word-line decoder x-dec word-line decoder ram core i/o driver address & clock buffers i/o driver
STD111 5-10 samsung asic spsram_hd high density single-port synchronous static ram characteristics de?nition for ac timing (ns) symbol description symbol description t cyc clock cycle time t ckh clock pulse width high t ckl clock pulse width low t as address setup time t ah address hold time t cs csn setup time t ch csn hold time t ds data-in setup time t dh data-in hold time t ws wen setup time t wh wen hold time t acc data access time t da de-access time t dz dout drive to high-z time t zd dout high-z to drive time t od oen to valid output time de?nition for power consumption ( m w/mhz) power_read the dynamic average power consumption while in a read cycle power_write the dynamic average power consumption while in a write cycle power_standby the standby power consumption while csn is high de?nition for area ( m m) width the physical width in x-direction height the physical height in y-direction
samsung asic 5-11 STD111 spsram_hd high density single-port synchronous static ram reference table * for ymux=4 (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that csn is high and the others are in normal operation mode. parameters words 256 512 512 1024 768 1536 1024 2048 bpw 32 32 64 64 96 96 128 128 ba 12121212 timing (ns) t cyc 2.67 2.75 2.90 3.01 3.04 3.19 3.11 3.30 t ckl 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 t ckh 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.48 t as 0.45 0.48 0.50 0.51 0.53 0.58 0.54 0.68 t ah 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 t cs 0.29 0.29 0.29 0.29 0.29 0.29 0.29 0.29 t ch 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ds 0.35 0.35 0.30 0.30 0.27 0.26 0.26 0.25 t dh 0.16 0.16 0.24 0.25 0.34 0.34 0.44 0.44 t ws 0.55 0.56 0.50 0.51 0.48 0.50 0.50 0.53 t wh 0.44 0.44 0.44 0.44 0.44 0.44 0.44 0.44 t acc 2.14 2.21 2.34 2.45 2.48 2.61 2.54 2.70 t da 1.39 1.41 1.56 1.59 1.66 1.70 1.68 1.73 t dz 0.20 0.20 0.23 0.23 0.24 0.24 0.24 0.26 t zd 0.23 0.23 0.26 0.26 0.28 0.28 0.28 0.28 t od 0.72 0.72 0.81 0.81 0.92 0.92 1.03 1.03 power ( m w/mhz) power_read 241.57 268.41 442.37 488.18 644.43 713.65 847.72 944.82 power_write 291.60 322.60 584.59 641.00 921.25 1009.78 1301.57 1428.97 power_standby 57.06 73.89 106.31 141.11 155.35 216.27 204.19 299.40 area ( m m) width 1145.58 1145.58 2087.66 2087.66 3029.74 3029.74 3971.82 3971.82 height 247.02 444.94 375.54 701.97 504.05 959.01 632.57 1216.04
STD111 5-12 samsung asic spsram_hd high density single-port synchronous static ram reference table * for ymux=8 (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that csn is high and the others are in normal operation mode. parameters words 512 1024 1024 2048 1536 3072 2048 4096 bpw 16 16 32 32 48 48 64 64 ba 12121212 timing (ns) t cyc 2.67 2.75 2.90 3.02 3.05 3.20 3.11 3.30 t ckl 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 t ckh 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.48 t as 0.43 0.47 0.46 0.50 0.48 0.53 0.47 0.56 t ah 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 t cs 0.29 0.29 0.29 0.29 0.29 0.29 0.29 0.29 t ch 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ds 0.37 0.36 0.33 0.33 0.31 0.30 0.30 0.29 t dh 0.14 0.14 0.20 0.20 0.26 0.26 0.33 0.33 t ws 0.55 0.56 0.50 0.52 0.48 0.50 0.50 0.52 t wh 0.44 0.44 0.44 0.44 0.44 0.44 0.44 0.44 t acc 2.14 2.21 2.35 2.45 2.48 2.62 2.54 2.71 t da 1.39 1.41 1.56 1.59 1.66 1.70 1.69 1.73 t dz 0.19 0.19 0.21 0.21 0.22 0.22 0.23 0.23 t zd 0.22 0.22 0.24 0.24 0.26 0.26 0.26 0.26 t od 0.70 0.70 0.77 0.77 0.84 0.84 0.92 0.92 power ( m w/mhz) power_read 207.03 229.54 369.82 404.52 533.06 581.99 696.75 761.96 power_write 244.00 270.27 464.85 508.31 707.23 771.09 971.11 1058.63 power_standby 31.58 45.74 54.37 79.95 76.86 118.01 99.04 159.92 area ( m m) width 1145.58 1145.58 2087.66 2087.66 3029.74 3029.74 3971.82 3971.82 height 247.02 444.94 375.54 701.97 504.05 959.01 632.57 1216.04
samsung asic 5-13 STD111 spsram_hd high density single-port synchronous static ram reference table * for ymux=16 (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that csn is high and the others are in normal operation mode. parameters words 1024 2048 2048 4096 3072 6144 4096 8192 bpw 8 8 16 16 24 24 32 32 ba 12121212 timing (ns) t cyc 2.70 2.81 2.93 3.07 3.08 3.26 3.15 3.36 t ckl 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 t ckh 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.48 t as 0.57 0.61 0.60 0.65 0.63 0.68 0.66 0.72 t ah 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 t cs 0.29 0.29 0.29 0.29 0.29 0.29 0.29 0.29 t ch 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ds 0.37 0.37 0.34 0.35 0.32 0.35 0.31 0.35 t dh 0.13 0.13 0.17 0.17 0.23 0.23 0.28 0.28 t ws 0.55 0.56 0.50 0.52 0.48 0.50 0.50 0.52 t wh 0.44 0.44 0.44 0.44 0.44 0.44 0.44 0.44 t acc 2.17 2.26 2.38 2.50 2.51 2.67 2.57 2.76 t da 1.39 1.41 1.56 1.59 1.66 1.70 1.69 1.73 t dz 0.18 0.18 0.20 0.20 0.21 0.21 0.22 0.22 t zd 0.21 0.21 0.23 0.23 0.24 0.24 0.25 0.25 t od 0.69 0.69 0.75 0.75 0.80 0.80 0.86 0.86 power ( m w/mhz) power_read 189.69 211.57 335.71 368.00 481.75 525.63 627.82 684.07 power_write 220.81 245.81 408.49 447.98 606.72 662.40 815.51 889.07 power_standby 26.07 43.74 41.79 70.58 57.20 99.25 72.30 129.73 area ( m m) width 1145.58 1145.58 2087.66 2087.66 3029.74 3029.74 3971.82 3971.82 height 247.02 444.94 375.54 701.97 504.05 959.01 632.57 1216.04
STD111 5-14 samsung asic spsram_hd high density single-port synchronous static ram reference table * for ymux=32 (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that csn is high and the others are in normal operation mode. parameters words 2048 4096 4096 8192 6144 12288 8192 16384 bpw 448812121616 ba 12121212 timing (ns) t cyc 2.75 2.91 2.99 3.18 3.15 3.37 3.22 3.47 t ckl 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 t ckh 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.48 t as 0.56 0.59 0.57 0.61 0.57 0.63 0.58 0.64 t ah 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 t cs 0.29 0.29 0.29 0.29 0.29 0.29 0.29 0.29 t ch 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ds 0.37 0.60 0.35 0.60 0.33 0.62 0.32 0.64 t dh 0.12 0.12 0.17 0.17 0.21 0.21 0.25 0.25 t ws 0.56 0.57 0.50 0.52 0.48 0.50 0.50 0.52 t wh 0.44 0.44 0.44 0.44 0.44 0.44 0.44 0.44 t acc 2.21 2.35 2.43 2.60 2.57 2.77 2.63 2.86 t da 1.38 1.40 1.56 1.59 1.66 1.70 1.68 1.73 t dz 0.18 0.18 0.20 0.20 0.21 0.21 0.21 0.21 t zd 0.21 0.21 0.22 0.22 0.24 0.24 0.24 0.24 t od 0.69 0.69 0.74 0.74 0.78 0.78 0.83 0.83 power ( m w/mhz) power_read 180.53 201.95 318.87 350.17 456.78 498.53 594.26 647.71 power_write 207.22 231.24 378.35 415.74 554.34 605.89 735.19 801.71 power_standby 19.88 35.95 29.68 55.03 39.17 74.90 48.36 95.57 area ( m m) width 1145.58 1145.58 2087.66 2087.66 3029.74 3029.74 3971.82 3971.82 height 247.02 444.94 375.54 701.97 504.05 959.01 632.57 1216.04
samsung asic 5-15 STD111 spsram_hd high density single-port synchronous static ram read cycle write cycle t as a t ah (csn = low, oen = low, di = dont care) t acc wen t ws t wh t da dout t cyc ck t ckl t ckh a0 a2 valid m[a0] m[a1] m[a2] a1 t as a t ah (csn= low, oen = dont care) wen t ws t wh di t cyc ck t ckl t ckh a0 a2 a1 t ds t dh d0 d2 d1
STD111 5-16 samsung asic spsram_hd high density single-port synchronous static ram read cycle with csn controlled oen controlled output enable note: don't care means the condition that these pins are in normal operation mode. t as a t ah (oen = low, wen = high, di = dont care) csn t cs t ch dout t cyc ck t ckl t ckh a0 a2 a1 t da t acc m(a1) (ck, a, wen, di, csn = dont care) t od t dz hi-z valid oen dout hi-z t zd
samsung asic 5-17 STD111 spsrambw_hd high density single-port synchronous sram with bit-write logic symbol function description spsrambw_hd is a single-port synchronous static ram with bit-write capability which is provided as a compiler. spsrambw_hd is intended for use in high-density applications. basically, its functionality is exactly same as spsram_hd except a bit-write operation which is controlled by bwen[], named bit-write enable signal bus. each bit of bwen[] enables or disables the write operation of its corresponding bit in di[]. on the rising edge of ck, the write cycle is initiated when wen is low and csn is low. the data bits in di[], which their corresponding bit(s) in bwen[] are low, are written into the memory location speci?ed on a[]. when all bits of bwen[] are high, any data in di[] are not written into the memory location speci?ed on a[]. when all bits of bwen[] are low, the data in di[] are written into the memory location speci?ed on a[], which is exactly same as the write operation in spsram_hd. during the write cycle, dout[] remains stable. on the rising edge of ck, the read cycle is initiated when wen is high and csn is low. the data at dout[] become valid after a delay. while in standby mode that csn is high, data stored in the memory is retained and dout[] remains stable. when oen is high, dout[] is placed in a high-impedance state. spsrambw_hd function table ck csn wen oen a bwen di dout comment x x x h x x x z oen makes tri-state output x h x l x x x dout(t-1) de-selected (standby mode) - l l l valid all l valid dout(t-1) word-write cycle - l l l valid l valid dout(t-1) bit-write cycle - l l l valid all h valid dout(t-1) no operation - l h l valid x x mem(a) read cycle features ? suitable for high-density application ? bit-write capability ? separated data i/o ? synchronous operation ? duty-free clock cycle ? asynchronous tristate output ? latched inputs and outputs ? automatic power-down ? zero standby current ? low noise output optimization ? flexible aspect ratio ? dual-bank scheme available ? up to 256kbits capacity ? up to 16k number of words ? up to128 number of bit per word ck csn wen bwen [b-1:0] oen spsrambw_hd_xmb dout [b-1:0] a [m-1:0] notes: 1. words(w) is the number of words in spsrambw_hd 2. bpw(b) is the number of bits per word. 3. ymux(y) is one of the column mux types. 4. banks(ba) is the number of banks. di [b-1:0] 5. m = log 2 w
STD111 5-18 samsung asic spsrambw_hd high density single-port synchronous sram with bit-write parameter description spsrambw_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bits per word(b), column mux(y) and number of banks(ba) pin descriptions parameters ymux = 4 ymux = 8 ymux = 16 ymux = 32 words (w) ba = 1 min 32 64 128 256 max 1024 2048 4096 8192 step 16 32 64 128 ba = 2 min 64 128 256 512 max 2048 4096 8192 16384 step 32 64 128 256 bpw (b) min 2 2 2 2 max 128 64 32 16 step 1 1 1 1 name i/o description ck clock clock input. csn, wen, a[] and di[] are latched into the ram on the rising edge of ck. if csn and wen are low on the rising edge of ck, the ram is in write mode. if csn is low and wen is high on the rising edge of ck, the ram is in read mode. csn chip enable chip enable input. the chip enable is active-low and is latched into the ram on the rising edge of ck. when csn is low, the ram is enabled for reading or writ- ing, depending on the state of wen. when csn is high, the ram goes to the standby mode and is disabled for reading or writing. dout remains previous data output. wen read/write enable read or write enable input. the read/write enable is latched into the ram on the rising edge of ck. when wen is low, data are written to the addressed location and dout remains stable. when wen is high, data from the addressed word are presented at dout. bwen[] bit-write enable bit-write enable input bus. the bit-write enable is latched into the ram on the rising edge of ck. each bit of bwen[] enables/disables the write operation of corresponding data bit. bwen[i] corresponds to di[i] in bit-write. if wen and bwen[0] are low and bwen[1] is high, di[0] is written into the memory location speci?ed on a[], but di[1] is not written. oen data output enable data output enable input. the data output enable is asynchronously operated regardless of the state of other inputs. when oen is high, dout is disabled and goes to high-impedance state. a[] address address input bus. the address is latched into the ram on the rising edge of ck. di[] data input data input bus. data are latched on the rising edge of ck. data input is written into the addressed location in write mode. dout[] data output data output bus. data output is valid after the rising edge of ck while the ram is in read mode. data output remains previous data output while the ram is in write mode.
samsung asic 5-19 STD111 spsrambw_hd high density single-port synchronous sram with bit-write pin capacitance unit: [sl] note: each pins capacitance is exactly same regardless of available mux types for same bank. block diagrams spsrambw_hd has 2 different physical architectures due to the word depth. for a speci?c con?guration, only one of these architectures is generated from spsrambw_hd compiler. in dual bank, the bank selected by the address is only activated while the other bank is in idle mode. application notes 1. permitting over-the-cell routing in chip-level layout, over-the-cell routing in spsrambw_hd is permitted for only metal-5 layer. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of spsrambw_hd. 4. a byte-write or word-write operation will be supported with spsrambw_hd. please refer to the function table. in byte-write operation, the number of bwen[] signal bus should be divided by a byte (8) and eight bwen signals should be tied to a connection wire. in this case, di[] bus is controlled by a byte-wired bwen signal instead of each bwen bit. in word-write operation, the functionality is exactly same as spsram_hd. if all of bwen[] signal is tied to low state, di[] bus is only controlled by wen. 5. power reduction during standby mode. the standby power is measured on the condition that only csn is in disable mode and other signals are in operation mode. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while standby mode. ck csn wen bwen oen a di dout ba =1 9.08 7.03 6.95 4.26 4.73 7.14 4.26 8.79 ba = 2 9.08 7.03 6.95 4.26 4.73 7.14 4.26 8.79 <1-bank> ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. i/o driver address & clock buffers i/o driver <2-bank> ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. y-dec & sense amp. control block y-dec & sense amp. ram core word-line decoder x-dec word-line decoder ram core i/o driver address & clock buffers i/o driver
STD111 5-20 samsung asic spsrambw_hd high density single-port synchronous sram with bit-write characteristics de?nition for ac timing (ns) symbol description symbol description t cyc clock cycle time t ckh clock pulse width high t ckl clock pulse width low t as address setup time t ah address hold time t cs csn setup time t ch csn hold time t ds data-in setup time t dh data-in hold time t ws wen setup time t wh wen hold time t bws bwen setup time t bwh bwen hold time t acc data access time t da de-access time t dz dout drive to high-z time t zd dout high-z to drive time t od oen to valid output time de?nition for power consumption ( m w/mhz) power_read the dynamic average power consumption while in a read cycle power_write the dynamic average power consumption while in a write cycle power_standby the standby power consumption while csn is high de?nition for area ( m m) width the physical width in x-direction height the physical height in y-direction
samsung asic 5-21 STD111 spsrambw_hd high density single-port synchronous sram with bit-write reference table * for ymux=4 (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that csn is high and the others are in normal operation mode. parameters words 256 512 512 1024 768 1536 1024 2048 bpw 32 32 64 64 96 96 128 128 ba 12121212 timing (ns) t cyc 2.67 2.75 2.90 3.01 3.04 3.19 3.11 3.30 t ckl 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 t ckh 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.48 t as 0.45 0.48 0.50 0.51 0.53 0.58 0.54 0.68 t ah 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 t cs 0.29 0.29 0.29 0.29 0.29 0.29 0.29 0.29 t ch 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ds 0.35 0.35 0.30 0.30 0.27 0.26 0.26 0.25 t dh 0.16 0.16 0.24 0.25 0.34 0.34 0.44 0.44 t ws 0.55 0.56 0.50 0.51 0.48 0.50 0.50 0.53 t wh 0.44 0.44 0.44 0.44 0.44 0.44 0.44 0.44 t bws 0.42 0.45 0.38 0.44 0.35 0.44 0.33 0.45 t bwh 0.14 0.14 0.22 0.22 0.31 0.31 0.41 0.41 t acc 2.14 2.21 2.34 2.45 2.48 2.61 2.54 2.70 t da 1.39 1.41 1.56 1.59 1.66 1.70 1.68 1.73 t dz 0.20 0.20 0.23 0.23 0.24 0.24 0.24 0.24 t zd 0.23 0.23 0.26 0.26 0.28 0.28 0.28 0.28 t od 0.72 0.72 0.81 0.81 0.92 0.92 1.03 1.03 power ( m w/mhz) power_read 255.46 287.55 470.50 534.89 686.77 796.08 904.26 1071.12 power_write 304.34 337.62 610.64 671.87 960.30 1056.66 1353.31 1492.00 power_standby 69.94 89.11 132.72 172.39 195.27 263.75 257.60 363.18 area ( m m) width 1145.58 1145.58 2087.66 2087.66 3029.74 3029.74 3971.82 3971.82 height 247.02 444.94 375.54 701.97 504.05 959.01 632.57 1216.04
STD111 5-22 samsung asic spsrambw_hd high density single-port synchronous sram with bit-write reference table * for ymux=8 (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that csn is high and the others are in normal operation mode. parameters words 512 1024 1024 2048 1536 3072 2048 4096 bpw 16 16 32 32 48 48 64 64 ba 12121212 timing (ns) t cyc 2.67 2.75 2.90 3.02 3.05 3.20 3.11 3.30 t ckl 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 t ckh 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.48 t as 0.43 0.47 0.46 0.50 0.48 0.53 0.47 0.56 t ah 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 t cs 0.29 0.29 0.29 0.29 0.29 0.29 0.29 0.29 t ch 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ds 0.37 0.36 0.33 0.33 0.31 0.30 0.30 0.29 t dh 0.14 0.14 0.20 0.20 0.26 0.26 0.33 0.33 t ws 0.55 0.56 0.50 0.52 0.48 0.50 0.50 0.52 t wh 0.44 0.44 0.44 0.44 0.44 0.44 0.44 0.44 t bws 0.42 0.45 0.38 0.45 0.35 0.44 0.33 0.44 t bwh 0.12 0.12 0.18 0.18 0.24 0.24 0.31 0.31 t acc 2.14 2.21 2.35 2.45 2.48 2.62 2.54 2.71 t da 1.39 1.41 1.56 1.59 1.66 1.70 1.69 1.73 t dz 0.19 0.19 0.21 0.21 0.22 0.22 0.23 0.23 t zd 0.22 0.22 0.24 0.24 0.26 0.26 0.26 0.26 t od 0.70 0.70 0.77 0.77 0.84 0.84 0.92 0.92 power ( m w/mhz) power_read 214.55 239.49 385.13 428.85 556.10 624.86 727.48 827.51 power_write 250.40 279.24 478.61 526.86 728.29 799.36 999.45 1096.73 power_standby 38.12 54.83 68.24 98.86 98.06 146.85 127.56 198.79 area ( m m) width 1145.58 1145.58 2087.66 2087.66 3029.74 3029.74 3971.82 3971.82 height 247.02 444.94 375.54 701.97 504.05 959.01 632.57 1216.04
samsung asic 5-23 STD111 spsrambw_hd high density single-port synchronous sram with bit-write reference table * for ymux=16 (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that csn is high and the others are in normal operation mode. parameters words 1024 2048 2048 4096 3072 6144 4096 8192 bpw 8 8 16 16 24 24 32 32 ba 12121212 timing (ns) t cyc 2.70 2.81 2.93 3.07 3.08 3.26 3.15 3.36 t ckl 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 t ckh 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.48 t as 0.57 0.61 0.60 0.65 0.63 0.68 0.66 0.72 t ah 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 t cs 0.29 0.29 0.29 0.29 0.29 0.29 0.29 0.29 t ch 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ds 0.37 0.37 0.34 0.35 0.32 0.35 0.31 0.35 t dh 0.13 0.13 0.17 0.17 0.23 0.23 0.28 0.28 t ws 0.55 0.56 0.50 0.52 0.48 0.50 0.50 0.52 t wh 0.44 0.44 0.44 0.44 0.44 0.44 0.44 0.44 t bws 0.43 0.48 0.39 0.47 0.37 0.47 0.35 0.47 t bwh 0.11 0.11 0.16 0.16 0.21 0.21 0.26 0.26 t acc 2.17 2.26 2.38 2.50 2.51 2.67 2.57 2.76 t da 1.39 1.41 1.56 1.59 1.66 1.70 1.69 1.73 t dz 0.18 0.18 1.20 0.20 0.21 0.21 0.22 0.22 t zd 0.21 0.21 0.23 0.23 0.24 0.24 0.25 0.25 t od 0.69 0.69 0.75 0.75 0.80 0.80 0.86 0.86 power ( m w/mhz) power_read 194.40 217.74 345.29 382.79 496.26 551.18 647.29 722.90 power_write 224.02 251.54 415.78 460.27 618.19 681.30 831.26 914.62 power_standby 29.41 49.55 49.30 83.11 68.88 118.58 88.15 155.97 area ( m m) width 1145.58 1145.58 2087.66 2087.66 3029.74 3029.74 3971.82 3971.82 height 247.02 444.94 375.54 701.97 504.05 959.01 632.57 1216.04
STD111 5-24 samsung asic spsrambw_hd high density single-port synchronous sram with bit-write reference table * for ymux=32 (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that csn is high and the others are in normal operation mode. parameters words 2048 4096 4096 8192 6144 12288 8192 16384 bpw 448812121616 ba 12121212 timing (ns) t cyc 2.75 2.91 2.99 3.18 3.15 3.37 3.22 3.47 t ckl 0.72 0.72 0.72 0.72 0.72 0.72 0.72 0.72 t ckh 0.48 0.48 0.48 0.48 0.48 0.48 0.48 0.48 t as 0.56 0.59 0.57 0.61 0.57 0.63 0.58 0.64 t ah 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 t cs 0.29 0.29 0.29 0.29 0.29 0.29 0.29 0.29 t ch 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ds 0.37 0.60 0.35 0.60 0.33 0.62 0.32 0.64 t dh 0.12 0.12 0.17 0.17 0.21 0.21 0.25 0.25 t ws 0.56 0.57 0.50 0.52 0.48 0.50 0.50 0.52 t wh 0.44 0.44 0.44 0.44 0.44 0.44 0.44 0.44 t bws 0.46 0.52 0.42 0.52 0.39 0.53 0.37 0.54 t bwh 0.10 0.10 0.15 0.15 0.19 0.19 0.23 0.23 t acc 2.21 2.35 2.43 2.60 2.57 2.77 2.63 2.86 t da 1.38 1.40 1.56 1.59 1.66 1.70 1.68 1.73 t dz 0.18 0.18 0.20 0.20 0.21 0.21 0.21 0.21 t zd 0.21 0.21 0.22 0.22 0.24 0.24 0.24 0.24 t od 0.69 0.69 0.74 0.74 0.78 0.78 0.83 0.83 power ( m w/mhz) power_read 183.69 206.04 325.65 360.13 467.36 515.57 608.81 672.35 power_write 208.66 234.93 382.40 424.64 561.15 620.17 744.92 821.51 power_standby 21.53 39.89 33.97 64.20 46.10 89.42 57.93 115.55 area ( m m) width 1145.58 1144.58 2087.66 2087.66 3029.74 3029.74 3971.82 3971.82 height 247.02 444.94 375.54 701.97 504.05 959.01 632.57 1216.04
samsung asic 5-25 STD111 spsrambw_hd high density single-port synchronous sram with bit-write read cycle write cycle t as a t ah (csn = low, oen = low, bwen, di = dont care) t acc wen t ws t wh t da dout t cyc ck t ckl t ckh a0 a2 valid m[a0] m[a1] m[a2] a1 t as a t ah (csn= low, oen = dont care) wen t ws t wh di t cyc ck t ckl t ckh a0 a2 bw1 t ds t dh d0 d2 d1 t bws bwen t bwh bw0 bw2 a1
STD111 5-26 samsung asic spsrambw_hd high density single-port synchronous sram with bit-write read cycle with csn controlled oen controlled output enable note: don't care means the condition that these pins are in normal operation mode. t as a t ah (oen = low, wen = high, bwen, di = dont care) csn t cs t ch dout t cyc ck t ckl t ckh a0 a2 a1 t da t acc m(a1) m(a0) (csn, ck, a, wen, bwen, di = dont care) t od t dz hi-z valid oen dout hi-z t zd
samsung asic 5-27 STD111 dpsram_hd high-density dual-port synchronous static ram logic symbol function description dpsram_hd is a dual-port synchronous static ram which is provided as a compiler. dpsram_hd is intended for use in high-density applications. each port is fully independent. on the rising edge of ck1(ck2), the write cycle is initiated when wen1 (wen2) is low and csn1 (csn2) is low. the data on di1[] (di2[]) is written into the memory location speci?ed on a1[](a2[]). during the write cycle, dout1[] (dout2[]) remains stable. on the rising edge of ck1(ck2), the read cycle is initiated when wen1 (wen2) is high and csn1(csn2) is low. the data at dout1[] (dout2[]) become valid after a delay. while in standby mode that csn1(csn2) is high, di1[] (di2[]) are disabled, data stored in the memory is retained and dout1[] (dout2[]) remains stable. when oen1 (oen2) is high, dout1[] (dout2[]) is placed in a high-impedance state. dpsram_hd function table ck1 ck2 csn1 csn2 wen1 wen2 oen1 oen2 a1 a2 di1 di2 dout1 dout2 comment x x x h x x z unconditional tri-state output x h x l x x dout(t-1) de-selected (standby mode) - l l l valid valid dout(t-1) write cycle - l h l valid x mem(a) read cycle features ? suitable for high-density application ? separated data i/o ? synchronous operation ? duty-free clock cycle ? asynchronous tri-state output control ? latched inputs and outputs ? automatic power-down ? zero standby current ? low noise output optimization ? flexible aspect ratio ? dual-bank scheme available ? up to 128kbits capacity ? up to 8k number of words ? up to 128 number of bits per word notes: 1. words (w) is the number of words in dpsram_hd. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the column mux types. 4. m = log 2 w ck1 ck2 csn1 csn2 wen1 dpsram_hd_xm dout1 [b-1:0] wen2 oen1 oen2 a1 [m-1:0] a2 [m-1:0] di1 [b-1:0] di2 [b-1:0] dout2 [b-1:0]
STD111 5-28 samsung asic dpsram_hd high-density dual-port synchronous static ram parameter description dpsram_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bits per word(b) and column mux(y). pin descriptions pin capacitance (unit = sl) note: each pins capacitance is exactly same regardless of available mux types. parameters ymux = 2 ymux = 4 ymux = 8 ymux = 16 words (w) min 16 32 64 128 max 1024 2048 4096 8192 step 8 16 32 64 bpw (b) min 1111 max 128 64 32 16 step 1111 name type description ck1 ck2 clock clock input. csn, wen, a[] and di[] are latched into the ram on the rising edge of ck. if csn and wen are low on the rising edge of ck, the ram is in write mode. if wen is high on the rising edge of ck, the ram is in read mode. csn1 csn2 chip enable chip enable input. the chip enable is active-low and is latched into the ram on the rising edge of ck. when csn is low, the ram is enabled for reading or writing, depending on the state of wen. when csn is high, the ram goes to the standby mode and is disabled for reading or writing. dout remains previ- ous data output. wen1 wen2 read/write enable read or write enable input. the read/write enable is latched into the ram on the rising edge of ck. when wen is low, data are written to the addressed location and dout remains stable. when wen is high, data from the addressed word are presented at dout. oen1 oen2 data output enable data output enable input. the data output enable is asynchronously operated regardless of the state of other inputs. when oen is high, dout is disabled and goes to high-impedance state. a1 [ ] a2 [ ] address address input bus. the address is latched into the ram on the rising edge of ck. di1 [ ] di2 [ ] data input data input bus. data are latched on the rising edge of ck. data input is writ- ten into the addressed location in write mode. dout1 [ ] dout2 [ ] data output data output bus. data output is valid after the rising edge of ck while the ram is in read mode. data output remains previous data output while the ram is in write mode. ck csn wen oen a di dout 28.53 8.37 7.68 5.66 8.23 4.60 9.13
samsung asic 5-29 STD111 dpsram_hd high-density dual-port synchronous static ram block diagram application notes 1. permitting over-the-cell routing in chip-level layout, over-the-cell routing in dpsram_hd is permitted for only metal-5 layer. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of dpsram_hd. 4. contention mode in same address access in dpsram_hd, simultaneous operation by both ports on the same memory address, as write/write, write/read or read/write operation, causes a contention problem. simultaneous operation is de?ned as a state in which both ports are enabled, both address buses are equal at the rising edge of ck. dpsram_hd has no scheme preventing the contention. due to simultaneous operation, silicon will behave unpredictably. a write operation cannot end and data appearing at outputs may not be valid. please refer to the timing diagrams if you want to avoid the contention mode between both ports. in write/write operation, the data stored at the current address will be unpredictable. in write/read or read/write operation, the read port is invalid while the write port is still valid. if you want to avoid the contention mode, you have to give the value greater than tcc (clock-to-clock setup time). however, simultaneous read/read is allowable without any restrictions. 5. power reduction during standby mode. the standby power is measured on the condition that only csn is in disable mode and other signals are in operation mode. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while standby mode. i/o driver address & clock buffers i/o driver y-dec & sense amp. control block y-dec & sense amp. ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. i/o driver address & clock buffers i/o driver
STD111 5-30 samsung asic dpsram_hd high-density dual-port synchronous static ram characteristics de?nition for ac timing (ns) symbol description symbol description t cyc clock cycle time t ckl clock pulse width low t ckh clock pulse width high t cc clock to clock setup time t as address setup time t ah address hold time t cs csn setup time t ch csn hold time t ds data-in setup time t dh data-in hold time t ws wen setup time t wh wen hold time t acc data access time t da de-access time t dz dout drive to high-z time t zd dout high-z to drive time t od oen to valid output time de?nition for power consumption ( m w/mhz) power_read the dynamic average power consumption while in a read cycle power_write the dynamic average power consumption while in a write cycle power_standby the standby power consumption while csn is high de?nition for area ( m m) width the physical width in x-direction height the physical height in y-direction
samsung asic 5-31 STD111 dpsram_hd high-density dual-port synchronous static ram reference table * for ymux=2 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) notes: 1. in power consumption of dpsram_hd, only one port is measured and the other port is isolated. 2. standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 256 512 768 1024 bpw 32 64 96 128 timing (ns) t cyc 3.43 3.94 4.36 4.70 t ckl 0.88 0.86 0.86 0.86 t ckh 0.59 0.63 0.69 0.78 t cc 1.74 2.25 2.46 2.92 t as 0.41 0.40 0.40 0.39 t ah 0.27 0.27 0.27 0.27 t cs 0.36 0.35 0.36 0.36 t ch 0.27 0.27 0.27 0.27 t ds 0.26 0.26 0.26 0.26 t dh 0.56 0.64 0.70 0.77 t ws 0.38 0.38 0.38 0.38 t wh 0.27 0.27 0.27 0.27 t acc 2.81 3.29 3.64 3.88 t da 1.88 2.24 2.50 2.68 t dz 0.52 0.59 0.67 0.75 t zd 0.63 0.70 0.77 0.84 t od 0.73 0.80 0.87 0.96 power ( m w/mhz) power_read 252.60 467.66 715.73 996.83 power_write 330.45 661.87 1066.43 1544.15 power_standby 42.46 49.53 56.46 63.27 area ( m m) width 954.08 1645.28 2336.48 3027.68 height 541.34 839.85 1138.35 1436.86
STD111 5-32 samsung asic dpsram_hd high-density dual-port synchronous static ram reference table * for ymux=4 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) notes: 1. in power consumption of dpsram_hd, only one port is measured and the other port is isolated. 2. standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 512 1024 1536 2048 bpw 16 32 48 64 timing (ns) t cyc 3.19 3.66 4.13 4.60 t ckl 0.88 0.86 0.85 0.86 t ckh 0.59 0.59 0.61 0.63 t cc 1.74 2.25 2.64 2.92 t as 0.41 0.40 0.40 0.39 t ah 0.27 0.27 0.27 0.27 t cs 0.35 0.35 0.35 0.35 t ch 0.27 0.27 0.27 0.27 t ds 0.10 0.10 0.10 0.10 t dh 0.48 0.52 0.57 0.62 t ws 0.38 0.38 0.38 0.38 t wh 0.27 0.27 0.27 0.27 t acc 2.78 3.25 3.60 3.84 t da 1.85 2.21 2.47 2.64 t dz 0.50 0.54 0.59 0.64 t zd 0.60 0.65 0.70 0.74 t od 0.70 0.75 0.80 0.85 power ( m w/mhz) power_read 225.40 417.84 643.21 901.51 power_write 272.29 524.02 823.22 1169.90 power_standby 35.66 41.21 46.81 52.46 area ( m m) width 954.08 1645.28 2336.48 3027.68 height 541.34 839.85 1138.35 1436.86
samsung asic 5-33 STD111 dpsram_hd high-density dual-port synchronous static ram reference table * for ymux=8 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) notes: 1. in power consumption of dpsram_hd, only one port is measured and the other port is isolated. 2. standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 1024 2048 3072 4096 bpw 8 162432 timing (ns) t cyc 3.23 3.69 4.14 4.59 t ckl 0.91 0.91 0.92 0.94 t ckh 0.59 0.59 0.59 0.59 t cc 1.74 2.25 2.64 2.92 t as 0.53 0.54 0.55 0.57 t ah 0.27 0.27 0.27 0.27 t cs 0.36 0.35 0.36 0.36 t ch 0.27 0.27 0.27 0.27 t ds 0.10 0.10 0.10 0.10 t dh 0.47 0.50 0.53 0.57 t ws 0.38 0.38 0.38 0.38 t wh 0.27 0.27 0.27 0.27 t acc 2.81 3.28 3.63 3.87 t da 1.88 2.23 2.49 2.67 t dz 0.49 0.52 0.55 0.59 t zd 0.59 0.62 0.66 0.69 t od 0.69 0.72 0.76 0.80 power ( m w/mhz) power_read 217.93 400.88 616.43 864.59 power_write 236.82 438.10 674.19 945.08 power_standby 36.77 43.19 49.68 56.24 area ( m m) width 954.08 1645.28 2336.48 3027.68 height 541.34 839.85 1138.35 1436.86
STD111 5-34 samsung asic dpsram_hd high-density dual-port synchronous static ram reference table * for ymux=16 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) notes: 1. in power consumption of dpsram_hd, only one port is measured and the other port is isolated. 2. standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 2048 4096 6144 8192 bpw 4 8 12 16 timing (ns) t cyc 3.26 3.72 4.17 4.63 t ckl 0.90 0.90 0.91 0.93 t ckh 0.59 0.59 0.59 0.59 t cc 1.75 2.25 2.64 2.92 t as 0.53 0.53 0.53 0.55 t ah 0.27 0.27 0.27 0.27 t cs 0.36 0.35 0.36 0.36 t ch 0.27 0.27 0.27 0.27 t ds 0.10 0.10 0.10 0.10 t dh 0.46 0.48 0.51 0.54 t ws 0.38 0.38 0.38 0.38 t wh 0.27 0.27 0.27 0.27 t acc 2.85 3.31 3.67 3.91 t da 1.91 2.26 2.53 2.70 t dz 0.48 0.50 0.53 0.56 t zd 0.58 0.61 0.63 0.66 t od 0.69 0.71 0.74 0.77 power ( m w/mhz) power_read 215.68 391.61 599.53 839.42 power_write 220.61 395.55 598.37 829.10 power_standby 36.67 42.75 48.88 55.05 area ( m m) width 954.08 1645.28 2336.48 3027.68 height 541.34 839.85 1138.35 1436.86
samsung asic 5-35 STD111 dpsram_hd high-density dual-port synchronous static ram timing diagrams read cycle write cycle t as a t ah (csn = low, oen = low, di = dont care) t acc wen t ws t wh t da dout t cyc ck t ckl t ckh a0 a2 valid m[a0] m[a1] m[a2] a1 t as a t ah (csn= low, oen = dont care) wen t ws t wh di t cyc ck t ckl t ckh a0 a2 a1 t ds t dh d0 d2 d1
STD111 5-36 samsung asic dpsram_hd high-density dual-port synchronous static ram read cycle with csn controlled oen controlled output enable contention mode note: don't care means the condition that these pins are in normal operation mode. t as a t ah (oen = low, wen = high, di = dont care) csn t cs t ch dout t cyc ck t ckl t ckh a0 a2 a1 t da t acc m[a1] (ck, a, wen, di, csn = dont care) t od t dz hi-z valid oen dout hi-z t zd ck1 tcc ck2 (a1 = a2)
samsung asic 5-37 STD111 sparam_hd high-density single-port asynchronous static ram logic symbol function description sparam_hd is a single-port asynchronous static ram which is provided as a compiler. sparam_hd is intended for use in high-density applications. at the falling edge of wen, the write cycle is initiated. at the rising edge of wen, the write cycle is ended. during the write cycle, the data on di[] is written into the memory location speci?ed on a[]. the read cycle is initiated when wen is high and csn is low. the data at dout[] become valid after a delay whenever a[] transition is detected. while in standby mode that csn is high, a[] and di[] are disabled, data stored in the memory is retained and dout[] remains stable. when oen is high, dout[] is placed in a high-impedance state. sparam_hd function table csn wen oen a di dout comment x x h x x z unconditional tri-state output h x l x x dout(t-1) de-selected (standby mode) l l valid valid dout(t-1) write cycle starts l - l valid valid mem(a) write cycle ends and read cycle starts l l l stable valid dout(t-1) write cycle l h l toggle x mem(a) read cycle features ? suitable for high-density application ? standby (power down) mode available ? separated data i/o ? asynchronous operation ? asynchronous tri-state output ? address transition detector ? write-enable transition detector ? chip-select transition detector ? bank-select transition detector ? automatic power-down ? low noise output optimization ? zero standby current ? flexible aspect ratio ? dual bank scheme available ? up to 256kbits capacity ? up to 16k number of words ? up to 128 number of bit per word csn wen oen a [m-1:0] di [b-1:0] sparam_hd_xmb dout [b-1:0] notes: 1. words (w) is the number of words in sparam_hd. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the column mux types. 5. m = log 2 w 4. banks(ba) is the number of banks.
STD111 5-38 samsung asic sparam_hd high-density single-port asynchronous static ram parameter description sparam_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bit per word(b), column mux(y) and number of banks(ba). pin descriptions pin capacitance unit: [sl] note: each pins capacitance is exactly same regardless of available mux types for same bank. parameters ymux = 2 ymux = 4 ymux = 8 ymux = 16 ymux = 32 words(w) ba = 1 min 16 32 64 128 256 max 512 1024 2048 4096 8192 step 8 16 32 64 128 ba = 2 min 32 64 128 256 512 max 1024 2048 4096 8192 16384 step 16 32 64 128 256 bpw(b) min 11111 max 256 128 64 32 16 step 11111 name i/o description csn chip enable chip select input. the chip select signal acts as the memory enable signal for selections of multiple blocks. when csn is high, the memory goes to stand-by (power down) mode and no access to the memory can occur. conversely, if low, a read or write access can occur. when csn falls, an access is initiated. wen read/write enable write enable input. the write enable signal selects the type of memory access. the high state for a read access and the low state for a write access. upon the rising edge of wen, a write access completed and a read access initiated. oen data output enable output enable input. the output enable signal controls the output drivers from driven to tri-state condition unconditionally. a [ ] address address input bus. a[] should be stable when wen is low. the address selects the location to be accessed. when the address changes, the transi- tion is detected and the internal clock pulse is generated. di [ ] data input data input bus. the data input is written to the accessed location when wen is low. dout [ ] data output data output bus. the data output is data stored in the accessed location dur- ing a read access. data output driver has tri-state logic. when oen is low, the driver drives a certain value. otherwise, data output keeps hi-z state. during a write access, data on dout is predictable. csn wen oen a di dout ba = 1 1.87 1.87 1.87 3.91 1.87 7.12 ba = 2 1.87 1.87 1.87 3.91 1.87 7.12
samsung asic 5-39 STD111 sparam_hd high-density single-port asynchronous static ram block diagrams sparam_hd has 2 different physical architectures due to the word depth. optionally, one of these architectures is generated from sparam_hd compiler. in dual-bank, the bank selected by the address is only activated while the other bank is in idle mode. application notes 1. permitting over-the-cell routing in chip-level layout, over-the-cell routing in sparam_hd is permitted for only metal-5 layer. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of sparam_hd. 4. avoiding short transition on the address bus in sparam_hd, rather than the write operation which is synchronously performed by wen signal, the read operation is asynchronously performed whenever the address transition is occurred. in this case, if the short transition on the address, called a skew, is happened, since sparam_hd recognizes the short address transition as the stable address transition and do perform a read operation. at that time, while in the read operation, the data stored in the memory may be corrupted due to the short transition. to prevent such fail, the stable address cycle time (tcyc) is required. the essential requirement to recognize valid address transition is that at least minimum address period should be equal or greater than tacc (access time). 5. power reduction during standby mode. the standby power is measured on the condition that only csn is in disable mode and other signals are in operation mode. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while standby mode. <1-bank> ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. i/o driver address & clock buffers i/o driver <2-bank> ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. y-dec & sense amp. control block y-dec & sense amp. ram core word-line decoder x-dec word-line decoder ram core i/o driver address & clock buffers i/o driver
STD111 5-40 samsung asic sparam_hd high-density single-port asynchronous static ram characteristics de?nition for ac timing (ns) symbol description symbol description t cyc address cycle time t as address setup time t cas address setup time for csn rise t ah address hold time t wh wen hold time t cs csn setup time t ch csn hold time t ds data-in setup time t dh data-in hold time t wen wen pulse width low t acc data access time for read cycle t wacc data access time for wen rise t da de-access time t wda de-access time for wen rise t zd dout high-z to drive time t dz dout drive to high-z time t od oen to valid output time de?nition for power consumption ( m w/mhz) power_read the dynamic average power consumption while in a read cycle power_write the dynamic average power consumption while in a write cycle power_standby the standby power consumption while csn is high de?nition for area ( m m) width the physical width in x-direction height the physical height in y-direction
samsung asic 5-41 STD111 sparam_hd high-density single-port asynchronous static ram reference table * for ymux=2 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 128 256 256 512 384 768 512 1024 bpw 64 64 128 128 192 192 256 256 ba 12121212 timing (ns) t cyc 3.54 3.62 3.80 3.92 4.06 4.21 4.32 4.51 t as 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t cas 3.76 3.85 4.02 4.14 4.28 4.44 4.54 4.73 t ah 0.49 0.51 0.72 0.75 1.01 1.04 1.36 1.39 t wh 3.76 3.85 4.02 4.14 4.28 4.44 4.54 4.73 t ds 0.14 0.16 0.14 0.17 0.14 0.16 0.14 0.15 t dh 0.76 0.75 0.84 0.84 0.94 0.93 1.04 1.03 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.61 1.72 1.70 1.84 1.79 1.97 1.89 2.11 t wen 2.43 2.47 2.66 2.70 2.88 2.93 3.10 3.17 t acc 3.54 3.62 3.80 3.92 4.06 4.21 4.32 4.51 t da 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 1.39 1.49 1.47 1.62 1.57 1.74 1.67 1.88 t dz 0.51 0.51 0.55 0.55 0.58 0.58 0.61 0.61 t zd 0.33 0.33 0.36 0.36 0.40 0.40 0.43 0.43 t od 0.55 0.55 0.58 0.58 0.62 0.62 0.65 0.66 power ( m w/mhz) power_read 296.01 315.80 565.87 618.94 850.87 951.64 1151.00 1313.90 power_write 397.43 427.42 890.37 972.44 1513.74 1670.46 2267.53 2521.46 power_standby 31.21 75.63 56.71 147.15 82.31 227.53 107.99 316.78 area ( m m) width 1207.22 1207.22 2157.05 2157.05 3106.87 3106.87 4056.69 4056.69 height 342.44 646.60 471.08 903.88 599.72 1161.16 728.36 1418.44
STD111 5-42 samsung asic sparam_hd high-density single-port asynchronous static ram reference table * for ymux=4 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 256 512 512 1024 768 1536 1024 2048 bpw 32 32 64 64 96 96 128 128 ba 12121212 timing (ns) t cyc 3.51 3.59 3.74 3.86 3.97 4.13 4.20 4.40 t as 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t cas 3.74 3.82 3.97 4.09 4.20 4.35 4.43 4.62 t ah 0.52 0.54 0.75 0.78 1.04 1.07 1.39 1.43 t wh 3.74 3.82 3.97 4.09 4.20 4.35 4.43 4.62 t ds 0.15 0.16 0.15 0.16 0.15 0.16 0.15 0.14 t dh 0.74 0.73 0.80 0.78 0.86 0.84 0.91 0.91 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.59 1.69 1.65 1.79 1.71 1.88 1.77 1.98 t wen 2.45 2.49 2.67 2.72 2.90 2.95 3.12 3.18 t acc 3.51 3.59 3.74 3.86 3.97 4.13 4.20 4.40 t da 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 1.36 1.47 1.42 1.56 1.48 1.66 1.54 1.75 t dz 0.51 0.51 0.55 0.55 0.58 0.58 0.61 0.61 t zd 0.33 0.33 0.36 0.36 0.40 0.40 0.43 0.43 t od 0.55 0.55 0.59 0.58 0.62 0.62 0.66 0.65 power ( m w/mhz) power_read 237.40 247.96 447.05 474.50 669.40 721.00 904.45 987.49 power_write 294.56 309.83 627.93 669.30 1030.91 1109.77 1503.48 1631.23 power_standby 20.26 48.08 34.13 86.35 48.14 129.20 62.27 176.64 area ( m m) width 1207.22 1207.22 2157.05 2157.05 3106.87 3106.87 4056.69 4056.69 height 342.44 646.60 471.08 903.88 599.72 1161.16 728.36 1418.44
samsung asic 5-43 STD111 sparam_hd high-density single-port asynchronous static ram reference table * for ymux=8 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 512 1024 1024 2048 1536 3072 2048 4096 bpw 16 16 32 32 48 48 64 64 ba 12121212 timing (ns) t cyc 3.53 3.62 3.76 3.89 3.99 4.16 4.23 4.43 t as 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t cas 3.75 3.85 3.99 4.12 4.22 4.38 4.45 4.65 t ah 0.52 0.54 0.75 0.78 1.04 1.07 1.39 1.43 t wh 3.75 3.85 3.99 4.12 4.22 4.38 4.45 4.65 t ds 0.15 0.16 0.15 0.17 0.15 0.16 0.15 0.14 t dh 0.70 0.67 0.76 0.72 0.83 0.78 0.89 0.85 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.61 1.72 1.67 1.82 1.73 1.91 1.79 2.01 t wen 2.44 2.47 2.67 2.70 2.89 2.93 3.11 3.17 t acc 3.53 3.62 3.76 3.89 3.99 4.16 4.23 4.43 t da 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 1.38 1.50 1.44 1.59 1.50 1.69 1.56 1.78 t dz 0.51 0.51 0.55 0.54 0.58 0.58 0.61 0.61 t zd 0.33 0.33 0.36 0.36 0.40 0.40 0.43 0.43 t od 0.55 0.55 0.58 0.58 0.62 0.62 0.65 0.65 power ( m w/mhz) power_read 211.43 219.32 399.31 417.73 600.08 632.62 813.75 863.97 power_write 232.50 247.38 483.89 512.41 773.59 824.42 1104.59 1183.43 power_standby 17.12 41.09 27.84 69.75 38.67 100.88 49.61 134.50 area ( m m) width 1207.22 1207.22 2157.05 2175.05 3106.87 3106.87 4056.69 4056.69 height 342.44 646.60 471.08 903.88 599.72 1161.16 728.36 1418.44
STD111 5-44 samsung asic sparam_hd high-density single-port asynchronous static ram reference table * for ymux=16 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 1024 2048 2048 4096 3072 6144 4096 8192 bpw 8 8 16 16 24 24 32 32 ba 12121212 timing (ns) t cyc 3.56 3.68 3.80 3.95 4.03 4.21 4.27 4.48 t as 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t cas 3.78 3.91 4.02 4.18 4.25 4.45 4.49 4.72 t ah 0.52 0.54 0.75 0.78 1.04 1.07 1.39 1.43 t wh 3.78 3.91 4.02 4.18 4.25 4.45 4.49 4.72 t ds 0.16 0.16 0.17 0.19 0.16 0.20 0.14 0.17 t dh 0.65 0.56 0.71 0.62 0.77 0.68 0.84 0.75 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.64 1.79 1.70 1.88 1.76 1.98 1.82 2.07 t wen 2.43 2.44 2.65 2.67 2.87 2.90 3.10 3.13 t acc 3.56 3.68 3.80 3.95 4.03 4.21 4.27 4.48 t da 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 1.41 1.55 1.48 1.65 1.54 1.74 1.60 1.84 t dz 0.51 0.51 0.54 0.54 0.58 0.58 0.61 0.61 t zd 0.33 0.33 0.36 0.36 0.40 0.40 0.43 0.43 t od 0.55 0.55 0.58 0.58 0.62 0.62 0.65 0.65 power ( m w/mhz) power_read 194.95 201.50 373.63 387.64 565.45 588.69 770.41 804.65 power_write 203.19 215.26 410.81 434.92 645.75 684.69 908.00 964.57 power_standby 15.82 39.97 25.12 64.23 34.53 89.89 44.06 116.95 area ( m m) width 1207.22 1207.22 2157.05 2157.05 3106.87 3106.87 4056.69 4056.69 height 342.44 646.60 471.08 903.88 599.72 1161.16 728.36 1418.44
samsung asic 5-45 STD111 sparam_hd high-density single-port asynchronous static ram reference table * for ymux=32 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 2048 4096 4096 8192 6144 12288 8192 16384 bpw 448812121616 ba 12121212 timing (ns) t cyc 3.61 3.77 3.85 4.05 4.09 4.32 4.33 4.60 t as 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t cas 3.84 4.03 4.08 4.31 4.32 4.58 4.56 4.86 t ah 0.52 0.54 0.75 0.78 1.04 1.08 1.39 1.43 t wh 3.84 4.03 4.08 4.31 4.32 4.58 4.56 4.86 t ds 0.15 0.23 0.18 0.31 0.19 0.36 0.16 0.39 t dh 0.54 0.36 0.60 0.42 0.66 0.47 0.72 0.52 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.70 1.92 1.76 2.01 1.82 2.11 1.88 2.20 t wen 2.40 2.38 2.62 2.61 2.84 2.83 3.06 3.06 t acc 3.61 3.77 3.85 4.05 4.09 4.32 4.33 4.60 t da 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 1.47 1.66 1.53 1.75 1.59 1.85 1.66 1.94 t dz 0.51 0.51 0.54 0.54 0.58 0.58 0.61 0.61 t zd 0.33 0.33 0.36 0.36 0.40 0.40 0.43 0.43 t od 0.55 0.55 0.58 0.58 0.62 0.62 0.65 0.66 power ( m w/mhz) power_read 179.77 185.70 356.81 368.61 547.31 565.88 751.28 777.49 power_write 182.59 202.06 372.72 402.17 583.36 624.20 814.52 868.18 power_standby 16.11 48.56 24.84 71.16 33.67 94.59 42.61 118.85 area ( m m) width 1207.22 1207.22 2157.05 2157.05 3106.87 3106.87 4056.69 4056.69 height 342.44 646.60 471.08 903.88 599.72 1161.16 728.36 1418.44
STD111 5-46 samsung asic sparam_hd high-density single-port asynchronous static ram timing diagrams read cycle read cycle with csn-controlled basic write cycle a (wen = high, csn = low, oen = low, di = dont care) t acc t da dout t cyc m[a0] m[a1] m[a2] m[a3] a0 a1 a2 a3 a t acc t da dout t cyc valid m[a0] m[a2] a0 a1 a2 a3 t acc t da m[a1] t acc t da csn (oen = low, wen = high, di = dont care) t cas a t ah (csn = low, oen = dont care) wen t as t wen di a0 a1 a2 d1 d2 d0 t ds t dh t cyc
samsung asic 5-47 STD111 sparam_hd high-density single-port asynchronous static ram write cycle with csn controlled read-modi?ed-write cycle notes: 1. when the wen hold time after the last address bit transition is satisfied, d+ will toggle in response to a successful read of the initial contents of address a1. when the wen hold time after the last address bit transition is not satisfied, d+ will go to unknown state. 2. address bits are not allowed to change while wen is low. if they do change, then the data for one or more addresses in the memory array may be corrupted. oen controlled output enable note: don't care means the condition that these pins are in normal operation mode. a t ah (oen = dont care) wen t as t wen di a0 a1 a2 d1 d2 d0 t ds t dh csn t cs t ch t cyc a t acc t da dout t cyc m[a0] m[a2] a0 a1 a2 d+ t acc t wacc wen (csn = low, oen = low) di d1 d2 d0 t ds t dh t cyc t as t wen t ah d1 t da t wda t cyc (a, wen, di, csn = dont care) t od t dz hi-z valid oen dout hi-z t zd
STD111 5-48 samsung asic drom_hd high-density synchronous diffusion programmable rom logic symbol function description drom_hd is a synchronous diffusion programmable rom which is provided as a compiler. drom_hd is intended for use in high-density applications. the read cycle is initiated at the rising edge of ck. the data at dout[] become valid after a delay. while in standby mode that csn is high, dout[] remains stable. when oen is high, dout is placed in a high-impedance state. drom function table parameter description drom_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bits per word(b) and column mux(y) and number of banks(ba). ck csn oen a dout comment x x h x z unconditional tri-state output x h l x dout(t-1) de-selected (standby mode) - l l valid mem(a) read cycle features ? suitable for high-density applications ? diffusion-programmable code available ? synchronous operation ? duty-free clock cycle ? asynchronous tri-state output ? latched inputs and outputs ? automatic power-down ? low noise output optimization ? zero standby current ? flexible aspect ratio ? dual-bank scheme available ? up to 512kbits capacity ? up to 16k number of words ? up to 128 number of bits per word ck csn oen dout [bC1:0] drom_hd_xmb a [m-1:0] notes: 1. words (w) is the number of words in drom_hd. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the column mux types. 5. m = log 2 w 4. banks (ba) is the number of banks.
samsung asic 5-49 STD111 drom_hd high-density synchronous diffusion programmable rom pin descriptions pin capacitance (unit = sl) note: each pins capacitance is exactly same regardless of available mux types for same bank. parameters ymux = 8 ymux = 16 ymux = 32 words (w) ba = 1 min 64 128 256 max 2048 4096 8192 step 32 64 128 ba = 2 min 128 256 512 max 4096 8192 16384 step 64 128 256 bpw (b) min 2 2 2 max 128 64 32 step 1 1 1 name i/o description ck clock clock input. csn and a[] are latched into the rom on the rising edge of ck. if csn is low on the rising edge of ck, the rom is in read mode. csn chip enable chip enable input. the chip enable is active-low and is latched into the rom on the rising edge of ck. when csn is low, the rom is enabled for reading. when csn is high, the rom goes to the standby mode and is disabled for reading. dout remains previous data output. oen data output enable data output enable input. the data output enable is asynchronously operated regardless of any inputs. when oen is high, dout is disabled and goes to high-impedance state. a [ ] address address input bus. the address is latched into the rom on the rising edge of ck. dout [ ] data output data output bus. data output is valid after the rising edge of ck while the rom is in read mode. ck csn oen a dout ba = 1 8.74 6.626 3.724 7.248 9.408 ba = 2 5.336 4.904 3.736 4.880 9.436
STD111 5-50 samsung asic drom_hd high-density synchronous diffusion programmable rom block diagrams drom_hd has 2 different physical architectures due to the word depth. for a speci?c con?guration, only one of these architectures is generated from drom_hd compiler. power is consumed by the bank that is selected by the address whereas the other bank will be in idle mode. application notes 1. permitting over-the-cell routing in chip-level layout, over-the-cell routing in drom_hd is permitted for only metal-5 layer. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of drom_hd. 4. power reduction during standby mode. the standby power is measured on the condition that only csn is in disable mode and other signals are in operation mode. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while standby mode. <1-bank> rom core word-line decoder x-dec word-line decoder rom core y-dec & sense amp. control block y-dec & sense amp. output driver address buffers output driver <2-bank> rom core word-line decoder x-dec word-line decoder rom core y-dec & sense amp. control block y-dec & sense amp. y-dec & sense amp. control block y-dec & sense amp. rom core word-line decoder x-dec word-line decoder rom core output driver address buffers output driver
samsung asic 5-51 STD111 drom_hd high-density synchronous diffusion programmable rom characteristics de?nition for ac timing (ns) symbol description symbol description t cyc clock cycle time t ch csn hold time from ck rise t ckl clock pulse width low t acc data access time t ckh clock pulse width high t da de-access time t as address setup time t dz dout drive to high-z time t ah address hold time t zd dout high-z to drive time t cs csn setup time t od oen to valid output de?nition for power consumption ( m w/mhz) power_read the dynamic average power consumption while in a read cycle power_standby the standby power consumption while csn is high de?nition for area ( m m) width the physical width in x-direction height the physical height in y-direction
STD111 5-52 samsung asic drom_hd high-density synchronous diffusion programmable rom reference table * for ymux=8 (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 512 1024 1024 2048 1536 3072 2048 4096 bpw 32 32 64 64 96 96 128 128 ba 12121212 timing (ns) t cyc 4.05 4.29 4.46 4.72 4.86 5.15 5.26 5.58 t ckl 0.44 0.68 0.44 0.72 0.44 0.75 0.45 0.78 t ckh 1.12 1.35 1.12 1.38 1.12 1.41 1.12 1.44 t as 0.16 0.84 0.18 0.90 0.22 0.98 0.26 1.06 t ah 0.61 0.86 0.61 0.90 0.61 0.93 0.61 0.97 t cs 0.44 0.68 0.44 0.72 0.44 0.75 0.44 0.78 t ch 0.52 0.78 0.52 0.81 0.52 0.85 0.52 0.88 t acc 2.94 3.25 3.06 3.41 3.25 3.64 3.51 3.94 t da 2.49 2.74 2.71 2.99 2.93 3.25 3.16 3.51 t dz 0.75 0.75 0.89 0.88 1.03 1.03 1.19 1.19 t zd 0.87 0.87 1.00 1.00 1.13 1.13 1.28 1.27 t od 0.96 0.96 1.09 1.09 1.22 1.22 1.37 1.37 power ( m w/mhz) power_read 284.25 287.74 601.59 605.65 1003.35 1007.62 1489.53 1493.63 power_standby 32.63 79.37 52.54 121.27 72.61 163.47 92.83 205.98 area ( m m) width 611.11 611.11 983.51 983.51 1355.64 1355.64 1727.51 1727.51 height 222.56 427.50 303.20 588.78 383.84 750.06 464.48 911.34
samsung asic 5-53 STD111 drom_hd high-density synchronous diffusion programmable rom reference table * for ymux=16 (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode parameters words 1024 2048 2048 4096 3072 6144 4096 8192 bpw 16 16 32 32 48 48 64 64 ba 12121212 timing (ns) t cyc 4.05 4.29 4.46 4.72 4.86 5.15 5.26 5.58 t ckl 0.44 0.68 0.44 0.72 0.44 0.75 0.44 0.78 t ckh 1.12 1.35 1.12 1.38 1.12 1.41 1.12 1.44 t as 0.16 0.84 0.18 0.90 0.22 0.98 0.26 1.06 t ah 0.61 0.86 0.61 0.90 0.61 0.93 0.61 0.97 t cs 0.45 0.68 0.45 0.72 0.45 0.75 0.44 0.78 t ch 0.52 0.78 0.52 0.81 0.52 0.85 0.52 0.88 t acc 2.98 3.25 3.10 3.41 3.29 3.64 3.54 3.94 t da 2.50 2.75 2.72 3.01 2.94 3.26 3.17 3.52 t dz 0.72 0.71 0.80 0.80 0.88 0.88 0.96 0.96 t zd 0.84 0.84 0.92 0.91 0.99 0.99 1.07 1.07 t od 0.92 0.92 1.00 1.00 1.08 1.08 1.16 1.16 power ( m w/mhz) power_read 283.62 286.97 601.73 605.51 1003.47 1007.47 1488.83 1492.86 power_standby 32.61 79.35 52.51 121.20 72.57 163.36 92.79 205.83 area ( m m) width 610.82 610.82 983.44 983.44 1355.64 1355.64 1727.44 1727.44 height 222.56 427.50 303.20 588.78 383.84 750.06 464.48 911.34
STD111 5-54 samsung asic drom_hd high-density synchronous diffusion programmable rom reference table * for ymux=32 (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode parameters words 2048 4096 4096 8192 6144 12288 8192 16384 bpw 8 8 16 16 24 24 32 32 ba 12121212 timing (ns) t cyc 4.05 4.29 4.46 4.72 4.86 5.15 5.26 5.58 t ckl 0.44 0.68 0.44 0.72 0.45 0.75 0.45 0.78 t ckh 1.12 1.35 1.12 1.38 1.12 1.41 1.12 1.44 t as 0.17 0.84 0.19 0.90 0.22 0.98 0.26 1.06 t ah 0.61 0.86 0.61 0.90 0.61 0.93 0.61 0.96 t cs 0.45 0.68 0.45 0.72 0.45 0.75 0.45 0.78 t ch 0.52 0.78 0.52 0.81 0.52 0.84 0.52 0.88 t acc 3.06 3.46 3.17 3.62 3.36 3.84 3.61 4.14 t da 2.51 2.77 2.74 3.03 2.96 3.29 3.19 3.54 t dz 0.70 0.69 0.75 0.75 0.81 0.81 0.87 0.87 t zd 0.82 0.82 0.87 0.87 0.93 0.93 0.99 0.99 t od 0.91 0.90 0.96 0.96 1.02 1.02 1.08 1.08 power ( m w/mhz) power_read 281.73 284.99 601.01 604.96 1003.42 1007.94 1488.97 1493.94 power_standby 32.61 79.35 52.49 121.20 72.54 163.40 92.77 205.95 area ( m m) width 610.23 610.23 983.27 983.27 1355.64 1355.64 1727.34 1727.34 height 222.56 427.50 303.20 588.78 383.84 750.06 464.48 911.34
samsung asic 5-55 STD111 drom_hd high-density synchronous diffusion programmable rom timing diagrams read cycle read cycle with csn controlled oen controlled output enable note : dont care means the condition that these pins are in normal operation mode. t as a t ah (csn, oen = low) t acc t da dout t cyc ck t ckl t ckh a0 a2 valid m[a0] m[a1] m[a2] a1 (oen = low) t ch t cs csn dout a1 a2 a0 a t as t ah m[a1] t acc t da ck t ckl t ckh t cyc m[a0] (ck, a, csn = dont care) t od t dz hi-z valid oen dout hi-z t zd
STD111 5-56 samsung asic mrom_hd high-density synchronous metal programmable rom logic symbol function description mrom_hd is a synchronous metal-2 programmable rom which is provided as a compiler. mrom_hd is intended for use in high-density applications. the read cycle is initiated at the rising edge of ck. the data at dout[] become valid after a delay. while in standby mode that csn is high, dout[] remains stable. when oen is high, dout is placed in a high-impedance state. mrom function table ck csn oen a dout comment x x h x z unconditional tri-state output x h l x dout(t-1) de-selected (standby mode) - l l valid mem(a) read cycle features ? suitable for high-density applications ? metal-2 programmable code available ? synchronous operation ? duty-free clock cycle ? asynchronous tri-state output control ? latched inputs and outputs ? automatic power-down ? low noise output optimization ? zero standby current ? flexible aspect ratio ? dual-bank scheme available ? up to 512kbits capacity ? up to 16k number of words ? up to 128 number of bits per word ck csn mrom_hd_xmb dout [b-1:0] oen a [m-1:0] notes: 1. words (w) is the number of words in mrom_hd. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the column mux types. 5. m = log 2 w 4. banks (ba) is the number of banks.
samsung asic 5-57 STD111 mrom_hd high-density synchronous metal programmable rom parameter description mrom_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bits per word(b), column mux(y) and number of banks(ba). pin descriptions pin capacitance (unit = sl) note: each pins capacitance is exactly same regardless of available mux types for same bank. parameters ymux = 8 ymux = 16 ymux = 32 words (w) ba = 1 min 64 128 256 max 2048 4096 8192 step 32 64 128 ba = 2 min 128 256 512 max 4096 8192 16384 step 64 128 256 bpw (b) min 2 2 2 max 128 64 32 step 1 1 1 name i/o description ck clock clock input. csn and a[] are latched into the rom on the rising edge of ck. if csn is low on the rising edge of ck, the rom is in read mode. csn chip enable chip enable input. the chip enable is active-low and is latched into the rom on the rising edge of ck. when csn is low, the rom is enabled for reading. when csn is high, the rom goes to the standby mode and is disabled for reading. dout remains previous data output. oen data output enable data output enable input. the data output enable is asynchronously operated regardless of any inputs. when oen is high, dout is disabled and goes to high-impedance state. a [ ] address address input bus. the address is latched into the rom on the rising edge of ck. dout [ ] data output data output bus. data output is valid after the rising edge of ck while the rom is in read mode. ck csn oen a dout ba = 1 13.386 4.88 4.20 5.74 8.86 ba = 2 14.436 5.16 3.84 5.44 8.86
STD111 5-58 samsung asic mrom_hd high-density synchronous metal programmable rom block diagrams mrom_hd has 2 different physical architectures due to the word depth. for a speci?c con?guration, only one of these architectures is generated from mrom_hd compiler. power is consumed by the bank that is selected by the address whereas the other bank will be in idle mode. application notes 1. permitting over-the-cell routing in chip-level layout, over-the-cell routing in mrom_hd is permitted for only metal-5 layer. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of mrom_hd. 4. power reduction during standby mode. the standby power is measured on the condition that only csn is in disable mode and other signals are in operation mode. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while standby mode. <1-bank> rom core word-line decoder x-dec word-line decoder rom core y-dec & sense amp. control block y-dec & sense amp. output driver address buffers output driver <2-bank> rom core word-line decoder x-dec word-line decoder rom core y-dec & sense amp. control block y-dec & sense amp. y-dec & sense amp. control block y-dec & sense amp. rom core word-line decoder x-dec word-line decoder rom core output driver address buffers output driver
samsung asic 5-59 STD111 mrom_hd high-density synchronous metal programmable rom characteristics de?nition for ac timing (ns) symbol description symbol description t cyc clock cycle time t ch csn hold time from ck rise t ckl clock pulse width low t acc data access time t ckh clock pulse width high t da de-access time t as address setup time t dz dout drive to high-z time t ah address hold time t zd dout high-z to drive time t cs csn setup time t od oen to valid output de?nition for power consumption ( m w/mhz) power_read the dynamic average power consumption while in a read cycle power_standby the standby power consumption while csn is high de?nition for area ( m m) width the physical width in x-direction height the physical height in y-direction
STD111 5-60 samsung asic mrom_hd high-density synchronous metal programmable rom reference table * for ymux=8 (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 512 1024 1024 2048 1536 3072 2048 4096 bpw 32 32 64 64 96 96 128 128 ba 12121212 timing (ns) t cyc 4.17 4.44 4.77 5.09 5.34 5.71 5.90 6.31 t ckl 0.60 0.85 0.60 0.91 0.60 0.97 0.60 1.03 t ckh 1.18 1.45 1.18 1.50 1.18 1.55 1.18 1.60 t as 0.10 0.97 0.13 1.02 0.24 1.17 0.44 1.40 t ah 0.69 1.00 0.69 1.07 0.69 1.13 0.69 1.19 t cs 0.60 0.85 0.60 0.91 0.60 0.97 0.60 1.03 t ch 0.61 0.92 0.61 0.99 0.61 1.05 0.61 1.11 t acc 2.95 3.25 3.29 3.65 3.68 4.10 4.12 4.60 t da 2.52 2.81 2.93 3.28 3.33 3.73 3.72 4.17 t dz 0.64 0.64 0.74 0.73 0.83 0.83 0.92 0.92 t zd 0.76 0.75 0.85 0.84 0.93 0.93 1.02 1.01 t od 0.83 0.83 0.95 0.92 1.01 1.01 1.09 1.09 power ( m w/mhz) power_read 368.42 371.97 847.64 852.19 1498.81 1504.22 2321.92 2328.06 power_standby 38.49 88.04 61.32 137.55 85.20 188.99 110.04 242.36 area ( m m) width 567.93 567.93 997.77 997.77 1426.75 1426.75 1854.86 1854.86 height 285.40 555.34 428.76 842.06 572.12 1128.78 715.48 1415.50
samsung asic 5-61 STD111 mrom_hd high-density synchronous metal programmable rom reference table * for ymux=16 (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode parameters words 1024 2048 2048 4096 3072 6144 4096 8192 bpw 16 16 32 32 48 48 64 64 ba 12121212 timing (ns) t cyc 4.18 4.45 4.77 5.08 5.34 5.70 5.90 6.32 t ckl 0.60 0.85 0.60 0.91 0.60 0.97 0.60 1.03 t ckh 1.18 1.45 1.18 1.50 1.18 1.55 1.18 1.60 t as 0.10 0.97 0.13 1.03 0.24 1.17 0.44 1.40 t ah 0.69 1.00 0.69 1.07 0.69 1.13 0.69 1.19 t cs 0.60 0.85 0.60 0.91 0.60 0.97 0.60 1.03 t ch 0.61 0.92 0.61 0.99 0.61 1.05 0.61 1.11 t acc 2.95 3.32 3.29 3.72 3.68 4.17 4.12 4.67 t da 2.53 2.82 2.94 3.29 3.34 3.75 3.74 4.19 t dz 0.60 0.60 0.66 0.66 0.72 0.72 0.78 0.78 t zd 0.72 0.72 0.78 0.78 0.84 0.83 0.89 0.88 t od 0.80 0.79 0.85 0.85 0.91 0.91 0.96 0.96 power ( m w/mhz) power_read 367.69 371.16 847.48 852.11 1498.70 1504.41 2321.34 2328.06 power_standby 38.39 89.04 61.30 138.50 85.15 189.87 109.95 243.15 area ( m m) width 567.62 567.62 997.69 997.69 1426.75 1426.75 1854.80 1854.80 height 285.40 555.34 428.76 842.06 572.12 1128.78 715.48 1415.50
STD111 5-62 samsung asic mrom_hd high-density synchronous metal programmable rom reference table * for ymux=32 (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode parameters words 2048 4096 4096 8192 6144 12288 8192 16384 bpw 8 8 16 16 24 24 32 32 ba 12121212 timing (ns) t cyc 4.18 4.44 4.77 5.08 5.34 5.70 5.90 6.30 t ckl 0.60 0.85 0.60 0.91 0.60 0.97 0.60 1.02 t ckh 1.18 1.45 1.18 1.50 1.18 1.55 1.18 1.60 t as 0.10 0.97 0.13 1.03 0.24 1.17 0.44 1.40 t ah 0.69 1.00 0.69 1.07 0.69 1.13 0.69 1.19 t cs 0.60 0.85 0.60 0.91 0.60 0.96 0.60 1.02 t ch 0.61 0.92 0.61 0.99 0.61 1.05 0.61 1.11 t acc 3.03 3.47 3.36 3.72 3.75 4.29 4.19 4.78 t da 2.55 2.85 2.96 3.29 3.36 3.76 3.76 4.19 t dz 0.59 0.58 0.63 0.66 0.67 0.67 0.71 0.71 t zd 0.70 0.70 0.74 0.78 0.78 0.78 0.82 0.82 t od 0.78 0.77 0.82 0.85 0.86 0.85 0.90 0.89 power ( m w/mhz) power_read 365.71 369.21 846.96 852.11 1498.49 1504.40 2320.31 2327.77 power_standby 38.41 89.10 61.30 138.50 85.13 189.88 109.89 243.14 area ( m m) width 566.98 566.98 997.51 997.69 1426.75 1426.75 1854.71 1854.71 height 285.40 555.34 428.76 842.06 572.12 1128.78 715.48 1415.50
samsung asic 5-63 STD111 mrom_hd high-density synchronous metal programmable rom timing diagrams read cycle read cycle with csn controlled oen controlled output enable note : dont care means the condition that these pins are in normal operation mode. t as a t ah (csn, oen = low) t acc t da dout t cyc ck t ckl t ckh a0 a2 valid m[a0] m[a1] m[a2] a1 (oen = low) t ch t cs csn dout a1 a2 a0 a t as t ah m[a1] t acc t da ck t ckl t ckh t cyc m[a0] (ck, a, csn = dont care) t od t dz hi-z valid oen dout hi-z t zd
STD111 5-64 samsung asic arfram_hd high-density multi-port asynchronous register file logic symbol function description arfram_hd is a multi-port asynchronous register ?le which is provided as a compiler. arfram_hd is intended for use in high-density applications. it allows maximum 4 ports with con?gurable 1-to-2 read ports and 1-to-2 write ports. all read and write ports are fully independent. at the falling edge of wen, the write cycle is initiated. while wen is low, the data at di[] is written into the memory location speci?ed on wa[]. at the rising edge of wen, the write cycle ends. regardless of wen signal, the read cycle is always enabled. the data stored in the memory location speci?ed on ra[] becomes valid through dout[] after a delay. when oen is high, dout[] is placed in a high-impedance state. arfram_hd write function table arfram_hd read function table wen wa di comment h x x write disable mode valid x write cycle starts - x valid write cycle ends ra oen dout comment valid l mem (ra) read cycle x h z unconditional tri-state output features ? suitable for high-density applications ? separated data i/o ? fully independent ports ? synchronous write operation ? asynchronous read operation ? latched inputs and outputs ? asynchronous tri-state output control ? con?gurable 1-to-2 read ports ? con?gurable 1-to-2 write ports ? flexible aspect ratio ? up to 16kbits capacity ? up to 1024 number of words ? up to 64 number of bits per word wen oen wa[m-1:0] ra[m-1:0] di[bC1:0] arfram_hd_rw_xm dout[bC1:0] notes: 1. words (w) is the number of words in arfram_hd. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the column mux types. 4. writes (nw) is the number of write ports (1-to-2). 5. reads (nr) is the number of read ports (1-to-2). 6. m = log 2 w
samsung asic 5-65 STD111 arfram_hd high-density multi-port asynchronous register file parameter description arfram_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bit per word(b), column mux(y), number of read ports(nr) and number of write ports(nw). pin descriptions pin capacitance unit: [sl] note: each pins capacitance is exactly same regardless of available mux types. parameters ymux = 2 ymux = 4 ymux = 8 words (w) min 4 8 16 max 256 512 1024 step 2 4 8 bpw (b) min 1 1 1 max 64 32 16 step 1 1 1 write ports (nw) 1, 2 read ports (nr) 1, 2 name i/o description wen write enable write enable input on each write port. while it is high, it prevents a write-operation. the write-operation starts when it becomes low. at the rising edge of wen, write-operation completed at the memory location. wa[ ] write address write address bus on each write port. it speci?es the location that the data will be written in the write-operation. wa[] is latched at the falling edge of wen. di[ ] data input data input bus on each write port. it contains data values to be written into the memory during the write-cycle. di[] is latched at the rising edge of wen. oen data output enable output enable input on each read port. the output enable signal controls the output drivers from driven to tri-state condition unconditionally. ra[ ] read address read address bus on each read port. it speci?es the location to be read in the read-operation. dout[ ] data output data output bus on each read port. it presents the data word stored in the location speci?ed by ra[] address bus. data output is in the high-impedance state when oen is high. wen oen wa ra di dout 1 0.4 0.36 1.66 0.2 1.19
STD111 5-66 samsung asic arfram_hd high-density multi-port asynchronous register file block diagrams application notes 1. permitting over-the-cell routing in arfram_hd, the over-the-cell routing is permitted. while doing layout on the chip-level, any signals to be routed can be crossed over the area of register ?le generated by arfram_hd compiler. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of arfram_hd. 4. contention mode under same addresses (ra[]=wa[]). in arfram_hd, simultaneous operations by both ports on the same address (ra[]=wa[]) as read/write, write/read, write/write operation, cause a contention problem. simultaneous operation is de?ned as a state in which both ports are enabled, both address buses are equal. arfram_hd has no scheme preventing the contention. due to simultaneous operation, silicon will behave unpredictably. a write operation cannot complete and data appearing at outputs may not be valid. please refer to the timing diagrams if you want to avoid the contention mode between both ports. write decoder write buffer ram core read buffer read decoder write control block column mux read control block i/o driver
samsung asic 5-67 STD111 arfram_hd high-density multi-port asynchronous register file characteristics de?nition for ac timing (ns) symbol description t cyc minimum address cycle time for read cycle t as address setup time from wa[] to wen fall t ah address hold time from wen fall to wa[] t ds data-in setup time from di[] to wen rise t dh data-in hold time from wen rise to di[] t wen minimum wen pulse width low to guarantee write cycle t wenh minimum wen pulse width high to guarantee write cycle t wwc write-write contention time from one wa[] to the other wa[] t da de-access time from ra to dout t acc data access time for read cycle t wda de-access time from wen fall to dout t wacc data access time for wen rise t zd dout high-z to drive time t dz dout drive to high-z time t od oen to valid output time de?nition for power consumption ( m w/mhz) power_read the dynamic average power consumption while in a read cycle power_write the dynamic average power consumption while in a write cycle de?nition for area ( m m) width the physical width in x-direction height the physical height in y-direction
STD111 5-68 samsung asic arfram_hd high-density multi-port asynchronous register file reference table * for ymux=2 (nr=1, nw=1) (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) parameters words 32 64 128 256 bpw 8 16 32 64 timing (ns) t cyc 1.47 1.71 2.15 2.81 t as 0.45 0.57 0.79 1.20 t ah 0.58 0.65 0.79 1.08 t ds 0.50 0.49 0.47 0.43 t dh 0.12 0.13 0.15 0.19 t wen 1.15 1.25 1.45 1.85 t wenh 0.58 0.63 0.72 0.93 t acc 1.47 1.71 2.15 2.81 t da 0.30 0.30 0.30 0.30 t wacc 1.69 1.95 2.41 3.12 t wda 0.45 0.45 0.45 0.45 t dz 0.18 0.20 0.24 0.33 t zd 0.56 0.59 0.66 0.80 t od 1.36 1.39 1.45 1.59 power ( m w/mhz) power_read 15.17 32.57 75.86 196.42 power_write 53.36 121.72 316.18 936.13 area ( m m) width 215.33 315.42 515.58 915.91 height 228.40 342.57 570.91 1027.60
samsung asic 5-69 STD111 arfram_hd high-density multi-port asynchronous register file reference table * for ymux=4 (nr=1, nw=1) (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) parameters words 64 128 256 512 bpw 4 8 16 32 timing (ns) t cyc 1.53 1.77 2.20 2.91 t as 0.38 0.45 0.59 0.81 t ah 0.57 0.63 0.76 1.01 t ds 0.48 0.50 0.54 0.61 t dh 0.11 0.12 0.12 0.14 t wen 1.16 1.27 1.47 1.89 t wenh 0.58 0.63 0.74 0.95 t acc 1.53 1.77 2.20 2.91 t da 0.30 0.30 0.30 0.30 t wacc 1.75 1.98 2.42 3.14 t wda 0.45 0.45 0.45 0.45 t dz 0.18 0.20 0.25 0.34 t zd 0.56 0.60 0.67 0.82 t od 1.44 1.47 1.54 1.68 power ( m w/mhz) power_read 15.38 33.05 76.42 195.34 power_write 42.72 108.88 285.62 856.81 area ( m m) width 216.53 316.54 516.57 916.61 height 212.88 327.08 555.48 1012.30
STD111 5-70 samsung asic arfram_hd high-density multi-port asynchronous register file reference table * for ymux=8 (nr=1, nw=1) (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) parameters words 128 256 512 1024 bpw 2 4 8 16 timing (ns) t cyc 1.70 1.95 2.40 3.07 t as 0.36 0.40 0.49 0.61 t ah 0.57 0.63 0.74 0.98 t ds 0.56 0.61 0.71 0.91 t dh 0.11 0.11 0.12 0.13 t wen 1.26 1.38 1.62 2.12 t wenh 0.63 0.69 0.81 1.06 t acc 1.70 1.95 2.40 3.07 t da 0.30 0.30 0.30 0.30 t wacc 1.90 2.15 2.60 3.26 t wda 0.45 0.45 0.45 0.45 t dz 0.18 0.20 0.25 0.34 t zd 0.56 0.59 0.66 0.81 t od 1.60 1.63 1.70 1.83 power ( m w/mhz) power_read 16.36 34.81 78.97 196.35 power_write 46.03 103.92 273.24 826.00 area ( m m) width 216.94 316.62 515.99 914.72 height 212.06 326.29 554.75 1011.67
samsung asic 5-71 STD111 arfram_hd high-density multi-port asynchronous register file reference table * for ymux=2 (nr=1, nw=2) (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) parameters words 32 64 128 256 bpw 8 16 32 64 timing (ns) t cyc 1.56 1.81 2.23 2.78 t as 0.99 1.14 1.43 2.02 t ah 0.58 0.65 0.80 1.10 t ds 0.51 0.49 0.47 0.40 t dh 0.14 0.15 0.18 0.24 t wen 1.19 1.30 1.52 1.97 t wenh 0.60 0.65 0.76 0.99 t acc 1.56 1.81 2.23 2.78 t da 0.32 0.32 0.32 0.32 t wacc 1.83 2.11 2.61 3.32 t wda 0.46 0.46 0.46 0.46 t dz 0.20 0.25 0.35 0.56 t zd 0.60 0.67 0.83 1.15 t od 1.22 1.28 1.40 1.69 t wwc 1.19 1.30 1.52 1.97 power ( m w/mhz) power_read 20.58 43.05 96.84 239.84 power_write 57.96 132.63 348.16 1043.89 area ( m m) width 271.86 395.38 642.41 1136.49 height 276.38 399.91 646.98 1141.12
STD111 5-72 samsung asic arfram_hd high-density multi-port asynchronous register file reference table * for ymux=4 (nr=1, nw=2) (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) parameters words 64 128 256 512 bpw 4 8 16 32 timing (ns) t cyc 1.77 1.99 2.39 3.04 t as 0.42 0.51 0.69 1.01 t ah 0.57 0.64 0.77 1.05 t ds 0.50 0.51 0.53 0.58 t dh 0.12 0.13 0.14 0.17 t wen 1.20 1.32 1.54 2.00 t wenh 0.60 0.66 0.77 1.00 t acc 1.77 1.99 2.39 3.04 t da 0.32 0.32 0.32 0.32 t wacc 2.03 2.28 2.75 3.49 t wda 0.47 0.47 0.47 0.47 t dz 0.18 0.22 0.28 0.42 t zd 0.57 0.62 0.72 0.93 t od 1.31 1.35 1.43 1.58 t wwc 1.20 1.32 1.54 2.00 power ( m w/mhz) power_read 19.18 40.01 89.66 220.93 power_write 51.85 119.44 317.63 966.11 area ( m m) width 273.54 396.96 643.80 1137.47 height 276.70 400.23 647.43 1141.73
samsung asic 5-73 STD111 arfram_hd high-density multi-port asynchronous register file reference table * for ymux=8 (nr=1, nw=2) (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) parameters words 128 256 512 1024 bpw 2 4 8 16 timing (ns) t cyc 1.78 2.03 2.46 3.02 t as 0.41 0.47 0.58 0.76 t ah 0.57 0.63 0.75 1.01 t ds 0.75 0.81 0.91 1.10 t dh 0.12 0.12 0.12 0.13 t wen 1.52 1.65 1.91 2.45 t wenh 0.76 0.82 0.95 1.23 t acc 1.78 2.03 2.46 3.02 t da 0.32 0.32 0.32 0.32 t wacc 2.03 2.30 2.78 3.42 t wda 0.47 0.47 0.47 0.47 t dz 0.18 0.20 0.25 0.34 t zd 0.56 0.59 0.67 0.83 t od 1.41 1.44 1.49 1.60 t wwc 1.52 1.65 1.91 2.45 power ( m w/mhz) power_read 19.29 39.70 88.26 216.35 power_write 52.86 119.27 315.12 959.01 area ( m m) width 274.12 397.07 642.99 1134.81 height 275.60 399.21 646.44 1140.89
STD111 5-74 samsung asic arfram_hd high-density multi-port asynchronous register file reference table * for ymux=2 (nr=2, nw=1) (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) parameters words 32 64 128 256 bpw 8 16 32 64 timing (ns) t cyc 1.60 1.88 2.35 2.87 t as 0.78 0.92 1.20 1.76 t ah 0.57 0.64 0.77 1.05 t ds 0.50 0.49 0.46 0.44 t dh 0.12 0.13 0.15 0.19 t wen 1.17 1.27 1.47 1.90 t wenh 0.58 0.63 0.74 0.95 t acc 1.60 1.88 2.35 2.87 t da 0.32 0.32 0.32 0.32 t wacc 1.84 2.16 2.69 3.35 t wda 0.45 0.45 0.45 0.46 t dz 0.19 0.21 0.26 0.36 t zd 0.49 0.53 0.61 0.78 t od 1.18 1.21 1.28 1.41 power ( m w/mhz) power_read 18.94 40.44 92.85 235.25 power_write 56.79 130.16 341.79 1024.63 area ( m m) width 289.55 417.32 672.85 1183.92 height 255.39 380.63 631.11 1132.06
samsung asic 5-75 STD111 arfram_hd high-density multi-port asynchronous register file reference table * for ymux=4 (nr=2, nw=1) (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) parameters words 64 128 256 512 bpw 4 8 16 32 timing (ns) t cyc 1.87 2.12 2.57 3.20 t as 0.42 0.52 0.69 1.02 t ah 0.57 0.62 0.74 1.00 t ds 0.50 0.52 0.56 0.64 t dh 0.11 0.12 0.12 0.14 t wen 1.19 1.30 1.52 1.98 t wenh 0.59 0.65 0.76 0.99 t acc 1.87 2.12 2.57 3.20 t da 0.32 0.32 0.32 0.32 t wacc 2.11 2.38 2.88 3.62 t wda 0.47 0.47 0.47 0.47 t dz 0.18 0.21 0.26 0.35 t zd 0.49 0.53 0.61 0.76 t od 1.29 1.32 1.38 1.49 power ( m w/mhz) power_read 17.80 37.84 86.62 218.91 power_write 51.35 117.91 313.81 956.66 area ( m m) width 291.46 419.11 674.42 1185.03 height 255.79 381.09 631.67 1132.84
STD111 5-76 samsung asic arfram_hd high-density multi-port asynchronous register file reference table * for ymux=8 (nr=2, nw=1) (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) parameters words 128 256 512 1024 bpw 2 4 8 16 timing (ns) t cyc 1.96 2.25 2.72 3.24 t as 0.36 0.42 0.53 0.70 t ah 0.57 0.62 0.74 0.97 t ds 0.76 0.82 0.94 1.18 t dh 0.11 0.11 0.12 0.13 t wen 1.47 1.60 1.87 2.44 t wenh 0.74 0.80 0.94 1.22 t acc 1.96 2.25 2.72 3.24 t da 0.32 0.32 0.32 0.32 t wacc 2.19 2.50 3.01 3.62 t wda 0.47 0.47 0.47 0.47 t dz 0.18 0.21 0.25 0.35 t zd 0.49 0.53 0.60 0.76 t od 1.53 1.56 1.61 1.72 power ( m w/mhz) power_read 18.49 39.36 89.50 223.34 power_write 51.94 117.44 309.85 940.41 area ( m m) width 292.10 419.23 673.50 1182.02 height 254.40 379.74 630.42 1131.77
samsung asic 5-77 STD111 arfram_hd high-density multi-port asynchronous register file reference table * for ymux=2 (nr=2, nw=2) (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) parameters words 32 64 128 256 bpw 8 16 32 64 timing (ns) t cyc 1.57 1.82 2.24 2.77 t as 0.63 0.79 1.10 1.71 t ah 0.58 0.65 0.80 1.12 t ds 0.45 0.44 0.42 0.34 t dh 0.09 0.09 0.11 0.23 t wen 1.18 1.29 1.51 1.96 t wenh 0.59 0.65 0.76 0.98 t acc 1.57 1.82 2.24 2.77 t da 0.31 0.31 0.31 0.31 t wacc 1.83 2.12 2.61 3.29 t wda 0.45 0.45 0.45 0.45 t dz 0.20 0.24 0.34 0.55 t zd 0.59 0.67 0.82 1.14 t od 1.22 1.27 1.39 1.68 t wwc 1.18 1.29 1.51 1.96 power ( m w/mhz) power_read 20.09 43.55 100.05 251.39 power_write 58.58 137.61 371.51 1142.60 area ( m m) width 354.11 513.31 831.72 1468.54 height 263.96 387.98 636.02 1132.10
STD111 5-78 samsung asic arfram_hd high-density multi-port asynchronous register file reference table * for ymux=4 (nr=2, nw=2) (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) parameters words 64 128 256 512 bpw 4 8 16 32 timing (ns) t cyc 1.92 2.15 2.55 3.18 t as 0.39 0.48 0.66 1.00 t ah 0.57 0.64 0.77 1.05 t ds 0.49 0.50 0.52 0.57 t dh 0.10 0.10 0.10 0.14 t wen 1.20 1.31 1.53 1.98 t wenh 0.60 0.65 0.77 0.99 t acc 1.92 2.15 2.55 3.18 t da 0.31 0.31 0.31 0.31 t wacc 2.12 2.37 2.83 3.55 t wda 0.47 0.47 0.47 0.47 t dz 0.18 0.21 0.27 0.41 t zd 0.57 0.62 0.72 0.93 t od 1.31 1.35 1.43 1.58 t wwc 1.20 1.31 1.53 1.98 power ( m w/mhz) power_read 19.28 41.23 93.76 233.36 power_write 52.93 124.67 341.57 1069.11 area ( m m) width 356.51 515.57 833.69 1469.94 height 264.31 388.38 636.51 1132.77
samsung asic 5-79 STD111 arfram_hd high-density multi-port asynchronous register file reference table * for ymux=8 (nr=2, nw=2) (typical process, 2.5v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) parameters words 128 256 512 1024 bpw 2 4 8 16 timing (ns) t cyc 1.78 2.03 2.46 3.02 t as 0.36 0.41 0.52 0.74 t ah 0.57 0.63 0.75 1.01 t ds 0.75 0.81 0.92 1.12 t dh 0.10 0.10 0.10 0.10 t wen 1.52 1.63 1.87 2.42 t wenh 0.76 0.82 0.94 1.21 t acc 1.78 2.03 2.46 3.02 t da 0.31 0.31 0.31 0.31 t wacc 2.03 2.30 2.77 3.40 t wda 0.47 0.47 0.47 0.47 t dz 0.17 0.20 0.24 0.34 t zd 0.55 0.59 0.66 0.82 t od 1.41 1.43 1.48 1.60 t wwc 1.52 1.63 1.87 2.42 power ( m w/mhz) power_read 20.24 43.27 98.07 242.66 power_write 53.78 125.16 340.83 1063.80 area ( m m) width 357.32 515.72 832.53 1466.16 height 263.10 387.20 635.42 1131.84
STD111 5-80 samsung asic arfram_hd high-density multi-port asynchronous register file timing diagrams read cycle write cycle oen controlled output enable note: dont care means the condition that these pins are in normal operation mode. ra (oen = low, wen, di, wa = dont care) t acc t da dout t cyc m[a0] m[a1] m[a2] m[a3] a0 a1 a2 a3 wa t ah (oen, ra = dont care) wen t as t wen di a0 a1 a2 d1 d2 d0 t ds t dh t wenh (wen, di, wa, ra = dont care) t od t dz hi-z valid oen dout hi-z t zd
samsung asic 5-81 STD111 arfram_hd high-density multi-port asynchronous register file read-write contention note: if wen[] falls while wa[] is same as ra[], it is a read-write contention. while wen[] is low, dout[] is unknown and write data is valid. after twacc from the rising edge of wen, the read data (d1) is valid. write-read contention note: while wen is low, if read access begins by ra<>[] which is same as wa<>[] latched at the falling edge of wen, it is write-read contention. the read data is invalid whereas the write is still valid. after transition of ra[], dout[] is unknown and write is valid. after twacc from the rising edge of wen, dout[] is valid. wen di d1 d2 d0 t ds t dh ra a1 d1 m(a1) dout t wda t wacc wa t ah t as a0 a1 a2 t wen (wa = ra, oen = low) t wenh (wa = ra, oen = low) wen di d1 d2 d0 t ds t dh ra a3 d1 m(a3) dout t da t wacc wa t ah t as a0 a1 a2 t wen a1 t wenh
STD111 5-82 samsung asic arfram_hd high-density multi-port asynchronous register file write-write contention note: if address latched at the falling edge of write ports are same and t1 is smaller than or equal to twwc, it is write-write contention. the data stored at current address will be unpredictable. wa0 a0 a3 a1 wen0 (ra, oen = dont care) di0 d1 d2 d0 a3 wen1 t ah d3 d4 d5 a1 a2 wa1 di1 t ds t dh t ah t as t wen t wenh t 1 t wenh t da t dh t as
samsung asic 5-83 STD111 fifo_hd high-density synchronous first-in first-out memory logic symbol function description fifo_hd is a synchronous ?rst-in ?rst-out buffer memory which is provided as a compiler. fifo_hd is intended for use in high-density applications. after valid reset, on the rising of wck, the write cycle is initiated when wen is low, rst is high and ff is low. the data on di[] is written into the memory location speci?ed by the write pointer. during normal write operation, the rising edge of wck will reset ef if it is set. at the last available memory location, write operation will set ff. di[] and wen must satisfy the setup and hold requirements with respect to the rising edge of wck. on the rising edge of rck, the read cycle is initiated when ren is low, rst is high, rtm is high and ef is low. the data located in the memory speci?ed by the read pointer comes in dout[] after some delay. during normal read operation, the rising edge of rck will reset ff if it is set. at the last available memory location with available data, read operation will set ef. a valid dout[] will be possibly in some speci?ed time after the rising edge of rck, under that oen is low. and the output data will remain unchanged until the next read, reset, or retransmit mode come in. ren must satisfy the setup and hold requirements with respect to the rising edge of rck. when oen is high, dout[] is placed in a high-impedance state. in reset mode, a reset is globally initiated at the falling edge of rst. the reset operation will set ef and reset ff and make the data output zero.the reset operation will initiate the read pointer and the write pointer as 0. after reset operation, the status of ef will make rck inoperable. the valid write input signal will become operable as rst is high. the read input signal will remain inoperable until ef is reset by the ?rst read input signal valid write. in retransmit mode, a retransmit is initiated at the falling edge of rtm only if the total number of writes after a reset operation is less than the word size of the memory in fifo_hd and more than 0 (0 < total number of write < w). the retransmit operation will initiate the read pointer as 0 to allow the retransmission of data, make dout[] zero and make ef reset if it is set. the valid read input signal will become operable as rtm is high. features ? suitable for high-density applications ? over-read and over-write protection capability ? retransmit capability ? synchronous operation ? duty-free clock cycle ? asynchronous tri-state output control ? latched full and empty status ?ag output ? automatic power-down ? flexible aspect ratio ? up to 32kbits capacity ? up to 4k number of words ? up to 64 number of bits per word notes: 1. words (w) is the number of words in fifo_hd. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the column mux types. rck ren oen rst rtm fifo_hd_xm dout [b-1:0] wck wen di [b-1:0] ef ff
STD111 5-84 samsung asic fifo_hd high-density synchronous first-in first-out memory fifo_hd function table notes: 1. read is blocked when ren is high and the read port is in disable mode. 2. read is blocked when ef is high (overhead protection). 3. under that oen is high, dout[] goes to tri-state output mode. 4. write is blocked when wen is high and the write port is in disable mode. 5. write is blocked when ff is high (overwrite protection). parameter description fifo_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bit per word(b) and column mux(y). rst wen wck ren rck rtm oen ef ff di dout comment x x xxxx - x l reset mode hx x xx x x x l retransmit mode hx x l - hll x dout(t) read mode hl - xxxx l valid dout(t-1) write mode hx x l - hl - l x dout(t) read and empty mode hl - xxxxl - valid dout(t-1) write and full mode hx x h - h l x x x dout(t-1) note 1 hx x l - h l h x x dout(t-1) note 2 x x x x x x h x x x hi-z note 3 hh - xxxxxxv alid dout(t-1) note 4 hl - xxxxxhv alid dout(t-1) note 5 parameters ymux = 4 ymux = 8 ymux = 16 ymux = 32 words (w) min 32 64 128 256 max 512 1024 2048 4096 step 32 64 128 256 bpw (b) min 2 2 2 2 max 64 32 16 8 step 1 1 1 1
samsung asic 5-85 STD111 fifo_hd high-density synchronous first-in first-out memory pin descriptions pin capacitance unit: [sl] note: each pins capacitance is exactly same regardless of available mux types. name i/o description rck read clock read clock input. upon the rising edge of rck, it begins a read operation when ren is low, rst is high, rtm is high and ef is low. ren read enable read enable input. when ren is low, the read access occurs properly. conversely when ren is high, no read access can occur and the read port of the fifo_hd goes to power down mode. ren is latched at the rising edge of rck. oen data output enable output enable input. the data output enable is asynchronously operated regardless of the state of other inputs. when oen is high, dout is disabled and goes to high-impedance state. rst reset reset input. upon the falling edge of rst, the reset mode is initiated. rst resets the read and write pointer to their initial position. rst sets ef and resets ff. rst makes dout[] zero. rtm retransmit retransmit input. upon the falling edge of rtm, the retransmit mode is initi- ated, provided that rst is high. rtm resets the read pointer to its initial posi- tion. rtm makes dout[] zero. wck write clock write clock input. upon the rising edge of wck, it begins a write operation when we is low, rst is high and ff is low. wen write enable write enable input. when wen is low, a write access occurs properly. con- versely when wen is high, no write access can occur and the write port of the fifo_hd goes to power down mode. wen is latched at the rising edge of wck. di date in data input bus. di[] is latched on the rising edge of wck. data input is written into the addressed location in write mode. ef empty flag empty ?ag. if the memory has no data to be read, ef goes high. valid reset makes ef high and valid retransmit makes it low. ff full flag full ?ag. if the memory has no vacancy to write data, ff goes high. valid reset makes ff low. dout data out data output bus. data output is valid after the rising edge of rck while the fifo_hd is in read mode when oen is low. conversely when oen is high, dout[] goes to high-impedance state. by reset or retransmit operation. dout[] goes to 0. rst rtm wck rck oen wen ren di dout 7.3 4.3 7.7 4.8 3.5 2.2 1.3 1.2 6.2
STD111 5-86 samsung asic fifo_hd high-density synchronous first-in first-out memory block diagrams application notes 1. permitting over-the-cell routing. in chip-level layout, over-the-cell routing in fifo_hd is permitted for only metal-5 layer. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of fifo_hd. 4. fifo_hd must be reset before any operation performed. the reset operation initiates the read porter and the write pointer as 0. 5. fifo_hd should be reset again before resuming normal operation if abnormal operation is performed. abnormal operations are invalid retransmit operation, and read/write operation causing timing requirement violations. 6. the retransmit operation initiates the read pointer as 0. 7. the retransmit is useful only when the total number of writes after a reset is less than the total word capacity of the fifo_hd and more than 0. 8. outputs are not changed until the ?rst valid read after a reset or retransmit. ram core write word-line shift register x-dec read word-line shift register ram core y-dec & sense amp. control block y-dec & sense amp. i/o driver clock buffers & flag generator i/o driver
samsung asic 5-87 STD111 fifo_hd high-density synchronous first-in first-out memory characteristics de?nition for ac timing (ns) symbol description t rst min rst pulse width low t rtm min rtm pulse width low t rcyc read clock cycle time t rckh read clock pulse width high t rckl read clock pulse width low t wcyc write clock cycle time t wckh write clock pulse width high t wckl write clock pulse width low t rs ren setup to rck rising t rh ren hold from rck rising t ws wen setup to wck rising t wh wen hold from wck rising t wrcs wck setup to rck rising t rwcs rck setup to wck rising t ds di setup to wck rising t dh di hold from wck rising t rstw rst setup to wck rising t rtmr rtm setup to rck rising t rste delay from rst falling to ef rising t rstf delay from rst falling to ff falling t rstd delay from rst falling to dout zero t rstda output hold time from rst falling to dout t rtme delay from rtm falling to ef falling t rtmd delay from rtm falling to dout zero t rtmda output hold time from rtm falling to dout t we delay from wck rising to ef falling t wf delay from wck rising to ff rising t rf delay from rck rising to ff falling t re delay from rck rising to ef rising t acc data access time (delay from rck rising to dout[] transition) t da de-access time (output hold time from rck rising to dout[]) t dz dout drive to high-z time t zd dout high-z to drive time t od oen to valid output time de?nition for power consumption ( m w/mhz) power_read the dynamic average power consumption while in a read cycle power_write the dynamic average power consumption while in a write cycle de?nition for area ( m m) width the physical width in x-direction height the physical height in y-direction
STD111 5-88 samsung asic fifo_hd high-density synchronous first-in first-out memory reference table * for ymux=4 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa = 0.5) parameters words 128 256 384 512 bpw 16 32 48 64 timing (ns) t rst 2.73 2.98 3.22 3.47 t rtm 3.32 3.54 3.81 4.14 t rcyc 2.65 2.96 3.26 3.56 t rckl 0.76 0.76 0.76 0.76 t rckh 0.54 0.54 0.54 0.54 t wcyc 2.60 2.90 3.21 3.51 t wckl 1.09 1.13 1.17 1.21 t wckh 0.65 0.68 0.72 0.76 t rs 0.45 0.45 0.45 0.45 t rh 0.11 0.11 0.11 0.11 t ws 0.48 0.48 0.48 0.48 t wh 0.11 0.11 0.11 0.11 t ds 0.08 0.06 0.04 0.02 t dh 0.49 0.52 0.56 0.60 t rstw 0.60 0.60 0.60 0.60 t rtmr 0.70 0.70 0.70 0.70 t wrcs 1.22 1.22 1.22 1.22 t rwcs 1.26 1.32 1.42 1.55 t rstd 2.71 2.98 3.26 3.55 t rstda 0.32 0.32 0.32 0.32 t rste 2.72 2.96 3.21 3.45 t rstf 2.72 2.96 3.21 3.45 t rtmd 2.70 2.97 3.25 3.55 t rtmda 0.31 0.31 0.31 0.31 t rtme 3.35 3.57 3.85 4.17 t we 0.68 0.68 0.68 0.68 t wf 2.23 2.42 2.62 2.82 t re 2.08 2.27 2.46 2.67 t rf 0.69 0.69 0.70 0.70 t acc 2.15 2.37 2.61 2.85 t da 1.73 1.94 2.15 2.38 t dz 0.39 0.47 0.54 0.61 t zd 0.45 0.47 0.50 0.52 t od 0.70 0.75 0.80 0.85 power ( m w/mhz) power_read 173.60 303.03 440.99 587.45 power_write 169.14 299.42 439.63 589.78 area ( m m) width 577.92 969.60 1361.28 1752.96 height 367.20 541.92 716.64 891.36
samsung asic 5-89 STD111 fifo_hd high-density synchronous first-in first-out memory reference table * for ymux=8 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa = 0.5) parameters words 256 512 768 1024 bpw 8 162432 timing (ns) t rst 2.74 2.99 3.23 3.48 t rtm 3.33 3.55 3.82 4.15 t rcyc 2.67 2.98 3.28 3.57 t rckl 0.76 0.76 0.77 0.77 t rckh 0.54 0.54 0.54 0.54 t wcyc 2.61 2.91 3.21 3.52 t wckl 1.09 1.12 1.15 1.18 t wckh 0.66 0.69 0.72 0.75 t rs 0.45 0.45 0.45 0.45 t rh 0.11 0.11 0.11 0.11 t ws 0.48 0.48 0.48 0.48 t wh 0.11 0.11 0.11 0.11 t ds 0.09 0.07 0.05 0.04 t dh 0.48 0.51 0.54 0.58 t rstw 0.60 0.60 0.60 0.60 t rtmr 0.56 0.56 0.56 0.56 t wrcs 1.22 1.22 1.22 1.22 t rwcs 1.26 1.32 1.41 1.55 t rstd 2.80 3.07 3.35 3.64 t rstda 0.32 0.32 0.32 0.32 t rste 2.72 2.96 3.21 3.47 t rstf 2.72 2.96 3.21 3.47 t rtmd 2.79 3.06 3.34 3.63 t rtmda 0.31 0.31 0.30 0.30 t rtme 3.37 3.59 3.86 4.19 t we 0.68 0.68 0.68 0.68 t wf 2.23 2.41 2.61 2.81 t re 2.09 2.27 2.47 2.67 t rf 0.69 0.69 0.69 0.69 t acc 2.17 2.40 2.63 2.87 t da 1.71 1.92 2.14 2.37 t dz 0.38 0.43 0.49 0.55 t zd 0.45 0.47 0.49 0.51 t od 0.69 0.72 0.75 0.77 power ( m w/mhz) power_read 150.94 256.35 369.00 488.88 power_write 131.96 220.73 315.77 417.07 area ( m m) width 577.92 969.60 1361.28 1752.96 height 384.18 558.90 733.62 908.34
STD111 5-90 samsung asic fifo_hd high-density synchronous first-in first-out memory reference table * for ymux=16 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) parameters words 512 1024 1536 2048 bpw 4 8 12 16 timing (ns) t rst 2.74 2.99 3.23 3.48 t rtm 3.33 3.55 3.83 4.15 t rcyc 2.73 3.00 3.28 3.56 t rckl 0.76 0.76 0.77 0.77 t rckh 0.54 0.54 0.54 0.54 t wcyc 2.61 2.91 3.22 3.52 t wckl 1.08 1.11 1.14 1.17 t wckh 0.68 0.71 0.74 0.77 t rs 0.45 0.45 0.45 0.45 t rh 0.11 0.11 0.11 0.11 t ws 0.48 0.48 0.48 0.48 t wh 0.11 0.11 0.11 0.11 t ds 0.09 0.07 0.06 0.04 t dh 0.48 0.51 0.53 0.56 t rstw 0.60 0.60 0.60 0.60 t rtmr 0.56 0.56 0.56 0.56 t wrcs 1.22 1.22 1.22 1.22 t rwcs 1.26 1.32 1.41 1.55 t rstd 2.97 3.24 3.52 3.81 t rstda 0.32 0.32 0.32 0.32 t rste 2.71 2.95 3.20 3.46 t rstf 2.71 2.95 3.20 3.46 t rtmd 2.96 3.23 3.51 3.80 t rtmda 0.31 0.31 0.30 0.30 t rtme 3.37 3.59 3.86 4.19 t we 0.68 0.68 0.68 0.68 t wf 2.23 2.42 2.61 2.81 t re 2.08 2.27 2.47 2.67 t rf 0.69 0.69 0.69 0.69 t acc 2.22 2.45 2.68 2.92 t da 1.68 1.89 2.11 2.34 t dz 0.37 0.42 0.47 0.52 t zd 0.45 0.46 0.48 0.50 t od 0.69 0.71 0.74 0.76 power ( m w/mhz) power_read 135.27 226.91 326.22 433.20 power_write 110.48 178.15 250.39 327.19 area ( m m) width 577.92 969.60 1361.28 1752.96 height 388.10 562.82 737.54 912.26
samsung asic 5-91 STD111 fifo_hd high-density synchronous first-in first-out memory reference table * for ymux=32 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) parameters words 1024 2048 3072 4096 bpw 2468 timing (ns) t rst 2.74 2.99 3.24 3.49 t rtm 3.34 3.56 3.84 4.17 t rcyc 2.79 3.06 3.33 3.59 t rckl 0.76 0.76 0.77 0.77 t rckh 0.54 0.54 0.54 0.54 t wcyc 2.61 2.92 3.22 3.53 t wckl 1.08 1.11 1.14 1.16 t wckh 0.74 0.76 0.79 0.81 t rs 0.45 0.45 0.45 0.45 t rh 0.11 0.11 0.11 0.11 t ws 0.48 0.48 0.48 0.48 t wh 0.11 0.11 0.11 0.11 t ds 0.10 0.08 0.06 0.05 t dh 0.48 0.50 0.53 0.56 t rstw 0.60 0.60 0.60 0.60 t rtmr 0.56 0.56 0.56 0.56 t wrcs 1.22 1.22 1.22 1.22 t rwcs 1.26 1.32 1.41 1.55 t rstd 3.29 3.57 3.85 4.13 t rstda 0.32 0.32 0.32 0.32 t rste 2.71 2.96 3.21 3.47 t rstf 2.71 2.96 3.21 3.47 t rtmd 3.28 3.56 3.84 4.12 t rtmda 0.31 0.31 0.31 0.31 t rtme 3.37 3.60 3.87 4.21 t we 0.68 0.68 0.68 0.68 t wf 2.23 2.42 2.62 2.81 t re 2.08 2.27 2.46 2.66 t rf 0.69 0.69 0.69 0.69 t acc 2.30 2.53 2.76 3.00 t da 1.62 1.83 2.05 2.26 t dz 0.37 0.41 0.45 0.50 t zd 0.45 0.46 0.48 0.49 t od 0.69 0.71 0.73 0.75 power ( m w/mhz) power_read 126.21 208.85 299.06 396.82 power_write 97.58 154.68 215.62 280.39 area ( m m) width 577.92 969.60 1361.28 1752.96 height 405.36 580.08 754.80 929.52
STD111 5-92 samsung asic fifo_hd high-density synchronous first-in first-out memory timing diagrams read cycle notes: 1. read cycle is blocked during empty state (over-read protected) 2. twrcs is the timing related between first write on empty state and first subsequent read. if it is not satisfied, dout[i] will be unpredictable. 3. tre is the timing related to the read and empty mode. (rst, rtm = high, oen = low) t acc t da dout[i-1] dout[i] t rs t rh t rcyc rck t rckl t rckh t wrcs t re ren ff ef dout t rf wck
samsung asic 5-93 STD111 fifo_hd high-density synchronous first-in first-out memory write cycle notes: 1. write cycle is blocked during full state (over-write protected) 2. trwcs is the timing related between first read on full state and first subsequent write. if it is not satisfied, dout[i] (not shown) will be unpredictable. 3. twf is the timing related to the write and full mode. reset cycle note: read cycle and write cycle are blocked when rst is low. (rst = high) t dh di[i] t ws t wh t wcyc wck t wckl t wckh wen ff t we ef di t wf t ds t rwcs rck t rstd all 0s t rstw rst t rst t rste wck, rck ff t rstf ef dout * note dout[i-1] t rstda
STD111 5-94 samsung asic fifo_hd high-density synchronous first-in first-out memory retransmit cycle note: read cycle is blocked when rtm is low. oen controlled output enable all 0s t rtmr rtm t rst t rtme rck ef dout * note t rtmd dout[i-1] t rtmda t od t dz hi-z valid oen dout hi-z t zd
samsung asic 5-95 STD111 spsram_lp low-power single-port synchronous static ram logic symbol function description spsram_lp is a single-port synchronous static ram which is provided as a compiler. spsram_lp is intended for use in low-power applications. on the rising edge of ck, the write cycle is initiated when wen is low and csn is low. the data on di[] is written into the memory location speci?ed on a[]. during the write cycle, dout[] remains stable. on the rising edge of ck, the read cycle is initiated when wen is high and csn is low. the data at dout[] become valid after a delay. while in standby mode that csn is high, a[] and di[] are disabled, data stored in the memory is retained and dout[] remains stable. when oen is high, dout[] is placed in a high-impedance state. parameter description spsram_lp is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bit per word(b), column mux(y) and number of banks(ba). ck csn wen oen a di dout comment x x x h x x z unconditional tri-state output x h x l x x dout(t-1) de-selected (standby mode) - l l l valid valid dout(t-1) write cycle - l h l valid x mem(a) read cycle ck csn wen oen a [m-1:0] spsram_lp_xmb dout [bC1:0] di [bC1:0] notes: 1. words(w) is the number of words in spsram_lp. 2. bpw(b) is the number of bits per word. 3. ymux(y) is one of the lower address decoder types. 4. banks(ba) is the number of banks. 5. m = log 2 w features ? suitable for low-power application ? separated data i/o ? synchronous operation ? asynchronous tristate output ? latched inputs and outputs ? automatic power-down mode available ? self-controlled circuit available ? zero standby current ? low noise output optimization ? flexible aspect ratio ? dual-bank scheme available ? up to 256kbits capacity ? up to 16k number of words ? up to 128 number of bit per word
STD111 5-96 samsung asic spsram_lp low-power single-port synchronous static ram pin descriptions pin capacitance unit: [sl] note: each pins capacitance is exactly same regardless of available mux types for same bank. parameters ymux = 4 ymux = 8 ymux = 16 ymux = 32 words (w) ba = 1 min 32 64 128 256 max 1024 2048 4096 8192 step 16 32 64 128 ba = 2 min 64 128 256 512 max 2048 4096 8192 16384 step 32 64 128 256 bpw (b) min 1 1 1 1 max 128 64 32 16 step 1 1 1 1 name i/o description ck clock clock input. csn, wen, a[] and di[] are latched into the ram on the rising edge of ck. if csn and wen are low on the rising edge of ck, the ram is in write mode. if wen is high on the rising edge of ck, the ram is in read mode. upon the falling edge of ck, the ram is in a precharge state. csn chip enable chip enable input. the chip enable is active-low and is latched into the ram on the rising edge of ck. when csn is low, the ram is enabled for reading or writing, depending on the state of wen. when csn is high, the ram goes to the standby mode and is disabled for reading or writing. dout remains previous data output. wen read/write enable read or write enable input. the read/write enable is latched into the ram on the rising edge of ck. when wen is low, data are written to the addressed location and dout remains stable. when wen is high, data from the addressed word are present at dout. oen data output enable data output enable input. the data output enable is asynchronously operated regardless of the state of other input. when oen is high, dout is disabled and goes to high-impedance state. a [ ] address address input bus. the address is latched into the ram on the rising edge of ck. di [ ] data input data input bus. data are latched on the rising edge of ck. data input is written into the addressed location in write mode. dout [ ] data output data output bus. data output is valid after the rising edge of ck while the ram is in read mode. data output remains previous data output while the ram is in write mode. ck csn wen oen a di dout ba = 1 8.15 14.34 7.73 5.75 9.02 3.07 9.44 ba = 2 8.15 14.34 7.73 5.75 9.02 3.07 9.44
samsung asic 5-97 STD111 spsram_lp low-power single-port synchronous static ram block diagrams spsram_lp has 2 different physical architectures due to the word depth. for a speci?c con?guration, only one of these architectures is generated from spsram_lp compiler. power is only consumed by the bank that is selected by the address and the other bank will be in idle mode. application notes 1. permitting over-the-cell routing. in chip-level layout, over-the-cell routing in spsram_lp is permitted only for metal-5 layer. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of spsram_lp. 4. power reduction during standby mode. the standby power is measured on the condition that only csn is in disable mode and other signals are in operation mode. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore to reduce unnecessary power consumption, you should keep stable for all signals while standby mode. <1-bank> ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. i/o driver address & clock buffers i/o driver <2-bank> ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. y-dec & sense amp. control block y-dec & sense amp. ram core word-line decoder x-dec word-line decoder ram core i/o driver address & clock buffers i/o driver
STD111 5-98 samsung asic spsram_lp low-power single-port synchronous static ram characteristics de?nition for ac timing (ns) symbol description symbol description t cyc clock cycle time t ckh clock pulse width high t ckl clock pulse width low t as address setup time t ah address hold time t cs csn setup time t ch csn hold time t ds data-in setup time t dh data-in hold time t ws wen setup time t wh wen hold time t acc data access time t da de-access time t dz dout drive to high-z time t zd dout high-z to drive time t od oen to valid output time de?nition for power consumption ( m w/mhz) power_read the dynamic average power consumption while in a read cycle power_write the dynamic average power consumption while in a write cycle power_standby the standby power consumption while csn is high de?nition for area ( m m) width the physical width in x-direction height the physical height in y-direction
samsung asic 5-99 STD111 spsram_lp low-power single-port synchronous static ram reference table * for ymux=4 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on condition that csn is high and the others are in normal operation mode. parameters words 256 512 512 1024 768 1536 1024 2048 bpw 32 32 64 64 96 96 128 128 ba 12121212 timing (ns) t cyc 4.92 5.67 5.92 6.79 6.95 7.86 8.02 8.90 t ckl 1.48 1.84 1.59 2.03 1.71 2.21 1.84 2.38 t ckh 2.45 2.69 2.99 3.30 3.49 3.88 3.96 4.43 t as 0.61 0.87 0.64 0.94 0.74 1.02 0.90 1.09 t ah 0.81 1.00 0.84 1.10 0.86 1.19 0.87 1.26 t cs 1.21 1.69 1.34 1.91 1.46 2.11 1.58 2.30 t ch 0.39 0.63 0.39 0.71 0.39 0.79 0.39 0.87 t ds 0.52 0.66 0.52 0.75 0.52 0.84 0.52 0.93 t dh 0.93 1.34 1.02 1.51 1.10 1.67 1.16 1.81 t ws 0.86 1.10 0.92 1.20 0.96 1.28 0.96 1.34 t wh 0.81 1.00 0.84 1.10 0.86 1.19 0.87 1.26 t acc 3.31 3.63 3.98 4.42 4.62 5.18 5.23 5.92 t da 2.92 3.18 3.58 3.94 4.22 4.66 4.83 5.35 t dz 0.72 0.71 0.82 0.82 0.90 0.90 0.97 0.97 t zd 0.85 0.84 0.96 0.94 1.05 1.04 1.13 1.14 t od 0.99 0.99 1.10 1.10 1.19 1.19 1.27 1.27 power ( m w/mhz) power_read 143.46 163.94 281.99 335.50 432.10 537.16 593.77 768.90 power_write 172.57 186.29 376.58 406.40 629.80 684.41 932.24 1020.33 power_standby 0.99 4.15 1.12 5.11 1.14 5.95 1.04 6.65 area ( m m) width 700.90 700.90 1303.55 1303.55 1906.21 1906.21 2508.86 2508.86 height 483.42 927.14 807.26 1574.82 1131.10 2222.50 1454.94 2870.18
STD111 5-100 samsung asic spsram_lp low-power single-port synchronous static ram reference table * for ymux=8 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on condition that csn is high and the others are in normal operation mode. parameters words 512 1024 1024 2048 1536 3072 2048 4096 bpw 16 16 32 32 48 48 64 64 ba 12121212 timing (ns) t cyc 4.92 5.66 5.91 6.76 6.94 7.82 8.02 8.83 t ckl 1.48 1.84 1.55 2.03 1.62 2.21 1.69 2.39 t ckh 2.46 2.69 2.99 3.30 3.49 3.88 3.96 4.43 t as 0.62 0.87 0.62 0.94 0.67 1.02 0.76 1.09 t ah 0.81 1.00 0.84 1.09 0.86 1.18 0.87 1.28 t cs 1.20 1.68 1.28 1.88 1.35 2.07 1.39 2.25 t ch 0.39 0.63 0.39 0.71 0.39 0.79 0.39 0.87 t ds 0.52 0.66 0.52 0.75 0.52 0.84 0.52 0.93 t dh 0.92 1.31 0.99 1.46 1.05 1.62 1.10 1.76 t ws 0.86 1.10 0.92 1.18 0.96 1.27 0.96 1.35 t wh 0.81 1.00 0.84 1.09 0.86 1.18 0.87 1.28 t acc 3.35 3.68 4.02 4.47 4.65 5.23 5.26 5.96 t da 2.93 3.21 3.60 3.96 4.24 4.68 4.84 5.36 t dz 0.69 0.69 0.77 0.77 0.86 0.83 0.88 0.88 t zd 0.82 0.82 0.91 0.91 0.98 0.98 1.03 1.03 t od 0.96 0.96 1.05 1.05 1.12 1.12 1.17 1.17 power ( m w/mhz) power_read 101.97 118.37 188.68 225.33 281.29 347.48 379.81 484.83 power_write 119.22 130.03 243.99 264.23 395.25 429.37 573.01 625.45 power_standby 1.06 4.16 1.18 5.08 1.28 6.03 1.35 7.02 area ( m m) width 700.90 700.90 1303.55 1303.55 1906.21 1906.21 2508.86 2508.86 height 483.42 927.14 807.26 1574.82 1131.10 2222.50 1454.94 2870.18
samsung asic 5-101 STD111 spsram_lp low-power single-port synchronous static ram reference table * for ymux=16 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on condition that csn is high and the others are in normal operation mode. parameters words 1024 2048 2048 4096 3072 6144 4096 8192 bpw 8 8 16 16 24 24 32 32 ba 12121212 timing (ns) t cyc 4.92 5.65 5.90 6.75 6.94 7.80 8.03 8.80 t ckl 1.48 1.84 1.54 2.04 1.59 2.22 1.63 2.39 t ckh 2.46 2.70 2.99 3.30 3.49 3.88 3.96 4.42 t as 0.62 0.87 0.65 0.94 0.66 1.02 0.66 1.09 t ah 0.81 1.00 0.84 1.10 0.86 1.19 0.87 1.26 t cs 1.20 1.68 1.26 1.87 1.31 2.05 1.34 2.22 t ch 0.39 0.63 0.39 0.71 0.39 0.79 0.39 0.87 t ds 0.52 0.66 0.52 0.75 0.52 0.84 0.52 0.93 t dh 0.91 1.31 0.98 1.46 1.03 1.60 1.07 1.71 t ws 0.86 1.10 0.92 1.20 0.96 1.28 0.97 1.34 t wh 0.81 1.00 0.84 1.10 0.86 1.19 0.87 1.26 t acc 3.39 3.74 4.06 4.53 4.70 5.29 5.31 6.02 t da 2.96 3.23 3.61 3.98 4.25 4.69 4.86 5.37 t dz 0.68 0.68 0.74 0.74 0.80 0.80 0.83 0.84 t zd 0.81 0.80 0.88 0.87 0.94 0.93 0.98 0.99 t od 0.95 0.95 1.02 1.02 1.08 1.08 1.12 1.12 power ( m w/mhz) power_read 79.66 92.67 139.36 164.69 202.03 244.30 267.66 331.51 power_write 92.55 101.98 178.34 193.64 279.29 302.67 395.39 429.07 power_standby 1.03 4.20 1.13 5.18 1.20 6.13 1.24 7.04 area ( m m) width 700.90 700.90 1303.55 1303.55 1906.21 1906.21 2508.86 2508.86 height 483.42 927.14 807.26 1574.82 1131.10 2222.50 1454.94 2870.18
STD111 5-102 samsung asic spsram_lp low-power single-port synchronous static ram reference table * for ymux=32 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on condition that csn is high and the others are in normal operation mode. parameters words 2048 4096 4096 8192 6144 12288 8192 16384 bpw 448812121616 ba 12121212 timing (ns) t cyc 4.97 5.73 5.97 6.82 7.03 7.87 8.14 8.87 t ckl 1.45 1.84 1.51 2.04 1.57 2.22 1.61 2.39 t ckh 2.54 2.78 3.06 3.38 3.56 3.95 4.02 4.49 t as 0.62 0.87 0.64 0.94 0.64 1.02 0.63 1.09 t ah 0.80 1.00 0.84 1.10 0.86 1.19 0.87 1.26 t cs 1.18 1.68 1.24 1.87 1.29 2.05 1.31 2.22 t ch 0.39 0.63 0.39 0.71 0.39 0.79 0.39 0.87 t ds 0.52 0.66 0.52 0.75 0.52 0.84 0.52 0.93 t dh 0.92 1.31 0.99 1.47 1.04 1.60 1.07 1.71 t ws 0.84 1.10 0.91 1.20 0.95 1.28 0.97 1.33 t wh 0.80 1.00 0.84 1.10 0.86 1.19 0.87 1.26 t acc 3.57 3.94 4.24 4.74 4.89 5.50 5.50 6.24 t da 3.09 3.37 3.75 4.12 4.39 4.83 4.99 5.51 t dz 0.68 0.68 0.75 0.75 0.79 0.79 0.82 0.82 t zd 0.81 0.81 0.88 0.88 0.94 0.94 0.97 0.97 t od 0.95 0.95 1.02 1.03 1.08 1.08 1.11 1.11 power ( m w/mhz) power_read 69.74 80.33 118.40 137.56 168.63 198.70 220.43 263.75 power_write 80.77 88.55 149.52 161.64 227.80 245.38 315.63 339.75 power_standby 1.03 4.17 1.12 5.12 1.21 6.06 1.29 7.00 area ( m m) width 686.34 686.34 1295.06 1295.06 1903.78 1903.78 2512.50 2512.50 height 483.42 927.14 807.26 1574.82 1131.10 2222.50 1454.94 2870.18
samsung asic 5-103 STD111 spsram_lp low-power single-port synchronous static ram read cycle write cycle t as a t ah (csn = low, oen = low, di = dont care) t acc wen t ws t wh t da dout t cyc ck t ckl t ckh a0 a2 valid m[a0] m[a1] m[a2] a1 t as a t ah (csn = low, oen = dont care) wen t ws t wh di t cyc ck t ckl t ckh a0 a2 a1 t ds t dh d0 d2 d1
STD111 5-104 samsung asic spsram_lp low-power single-port synchronous static ram read cycle with csn controlled oen controlled output enable note: don't care means the condition that these pins are in normal operation mode. t as a t ah (oen = low, wen = high, di = dont care) csn t cs t ch dout t cyc ck t ckl t ckh a0 a2 a1 t da t acc m(a1) m(a0) (ck, a, wen, d, csn = dont care) t od t dz hi-z valid oen dout hi-z t zd
samsung asic 5-105 STD111 dpsram_lp low-power dual-port synchronous static ram logic symbol function description dpsram_lp is a dual-port synchronous static ram which is provided as a compiler. dpsram_lp is intended for use in low-power applications. each port is fully independent. on the rising edge of ck1 (ck), the write cycle is initiated when wen1 (wen2) is low and csn1 (csn2) is low. the data on di1[] (di2[]) is written into the memory location speci?ed on a1[](a2[]). during the write cycle, dout1[] (dout2[]) remains stable. on the rising edge of ck1 (ck2), the read cycle is initiated when wen1 (wen2) is high and csn1(csn2) is low. the data at dout1[] (dout2[]) become valid after a delay. while in standby mode that csn1(csn2) is high, a1[] (a2[]) and di1[] (di2[]) are disabled, data stored in the memory is retained and dout1[] (dout2[]) remains stable. when oen1 (oen2) is high, dout1[] (dout2[]) is placed in a high-impedance state. dpsram_lp function table ck1 ck2 csn1 csn2 wen1 wen2 oen1 oen2 a1 a2 di1 di2 dout1 dout2 comment x x x h x x z unconditional tri-state output x h x l x x dout(t-1) de-selected (standby mode) - l l l valid valid dout(t-1) write cycle - l h l valid x mem(a) read cycle features ? suitable for low-power applications ? synchronous operation ? automatic power-down mode available ? self-controlled circuit available ? asynchronous tristate output ? low noise output optimization ? separated data i/o ? flexible aspect ratio ? zero standby current ? latched inputs and outputs ? up to128kbits capacity ? up to 8k number of words ? up to 128 number of bit per word notes: 1. words (w) is the number of words in dpsram_lp. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the column mux types. 4. m = log 2 w ck1 ck2 csn1 csn2 wen1 dpsram_lp_xm dout1 [b-1:0] wen2 oen1 oen2 a1 [m-1:0] a2 [m-1:0] di1 [b-1:0] di2 [b-1:0] dout2 [b-1:0]
STD111 5-106 samsung asic dpsram_lp low-power dual-port synchronous static ram parameter description dpsram_lp is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bits per word(b) and column mux(y). pin descriptions pin capacitance (unit = sl) note: each pins capacitance is exactly same regardless of available mux types. parameters ymux = 4 ymux = 8 ymux = 16 ymux = 32 words (w) min 32 64 128 256 max 1024 2048 4096 8192 step 16 32 64 128 bpw (b) min 1111 max 128 64 32 16 step 1111 name type description ck1 ck2 clock clock input. csn, wen, a[] and di[] are latched into the ram on the rising edge of ck. if csn and wen are low on the rising edge of ck, the ram is in write mode. if wen is high on the rising edge of ck, the ram is in read mode. upon the falling edge of ck, the ram is in a precharge state. csn1 csn2 chip enable chip enable input. the chip enable is active-low and is latched into the ram on the rising edge of ck. when csn is low, the ram is enabled for reading or writing, depending on the state of wen. when csn is high, the ram goes to the standby mode and is disabled for reading or writing. dout remains previous data output. wen1 wen2 read/write enable read or write enable input. the read/write enable is latched into the ram on the rising edge of ck. when wen is low, data are written to the addressed location and dout remains stable. when wen is high, data from the addressed word are present at dout. oen1 oen2 data output enable data output enable input. the data output enable is asynchronously operated regardless of the state of other inputs. when oen is high, dout is disabled and goes to high-impedance state. a1 [ ] a2 [ ] address address input bus. the address is latched into the ram on the rising edge of ck. di1 [ ] di2 [ ] data input data input bus. data are latched on the rising edge of ck. data input is written into the addressed location in write mode. dout1 [ ] dout2 [ ] data output data output bus. data output is valid after the rising edge of ck while the ram is in read mode. data output remains previous data output while the ram is in write mode. ck csn wen oen a di dout 5.04 12.00 7.25 4.51 8.02 4.94 9.13
samsung asic 5-107 STD111 dpsram_lp low-power dual-port synchronous static ram block diagram application notes 1. permitting over-the-cell routing in chip-level layout, over-the-cell routing in dpsram_lp is permitted for only metal-5 layer. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of dpsram_lp. 4. contention mode in same address access in dpsram_lp, simultaneous operation by both ports on the same memory address, as write/write, write/read or read/write operation, causes a contention problem. simultaneous operation is de?ned as a state in which both ports are enabled, both address buses are equal at the rising edge of ck. dpsram_lp has no scheme preventing the contention. due to simultaneous operation, silicon will behave unpredictably. a write operation cannot end and data appearing at outputs may not be valid. please refer to the timing diagrams if you want to avoid the contention mode between both ports. in write/write operation, the data stored at the current address will be unpredictable. in write/read or read/write operation, the read port is invalid while the write port is still valid. if you want to avoid the contention mode, you have to give the value greater than tcc (clock-to-clock setup time). however, simultaneous read/read is allowable without any restrictions.power reduction during standby mode. 5. power reduction during standby mode the standby power is measured on the condition that only csn is in disable mode and other signals are in operation mode. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while standby mode. word-line decoder in port1 x-dec in port1 ram core x-dec in port2 word-line decoder in port2 y-dec & sense amp. in port1 control block y-dec & sense amp. in port1 address & clock buffers in port1 i/o driver address & clock buffers in port2
STD111 5-108 samsung asic dpsram_lp low-power dual-port synchronous static ram characteristics de?nition for ac timing (ns) symbol description symbol description t cyc clock cycle time t ckl clock pulse width low t ckh clock pulse width high t cc clock to clock setup time t as address setup time t ah address hold time t cs csn setup time t ch csn hold time t ds data-in setup time t dh data-in hold time t ws wen setup time t wh wen hold time t acc data access time t da de-access time t dz dout drive to high-z time t zd dout high-z to drive time t od oen to valid output time de?nition for power consumption ( m w/mhz) power_read the dynamic average power consumption while in a read cycle power_write the dynamic average power consumption while in a write cycle power_standby the standby power consumption while csn is high de?nition for area ( m m) width the physical width in x-direction height the physical height in y-direction
samsung asic 5-109 STD111 dpsram_lp low-power dual-port synchronous static ram reference table * for ymux=4 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) notes: 1. in power consumption of dpsram_lp, only one port is measured and the other port is isolated. 2. standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 256 512 768 1024 bpw 32 64 96 128 timing (ns) t cyc 5.16 6.79 8.59 10.58 t ckl 1.43 1.65 1.97 2.39 t ckh 2.43 3.29 4.25 5.32 t cc 2.17 3.02 3.96 4.99 t as 0.60 0.79 1.01 1.26 t ah 0.67 0.70 0.71 0.71 t cs 1.32 1.65 2.06 2.56 t ch 0.35 0.36 0.36 0.36 t ds 0.24 0.24 0.24 0.24 t dh 0.92 1.14 1.38 1.65 t ws 0.85 0.89 0.91 0.90 t wh 0.67 0.70 0.71 0.71 t acc 3.27 4.32 5.51 6.84 t da 2.87 3.93 5.12 6.45 t dz 0.80 1.02 1.27 1.54 t zd 0.93 1.16 1.41 1.67 t od 1.06 1.29 1.54 1.80 power ( m w/mhz) power_read 201.94 407.65 633.31 878.92 power_write 239.50 537.32 915.91 1375.29 power_standby 1.25 1.53 1.95 2.52 area ( m m) width 1063.71 2012.43 2961.15 3909.87 height 524.26 873.70 1223.14 1572.58
STD111 5-110 samsung asic dpsram_lp low-power dual-port synchronous static ram reference table * for ymux=8 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) notes: 1. in power consumption of dpsram_lp, only one port is measured and the other port is isolated. 2. standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 512 1024 1536 2048 bpw 16 32 48 64 timing (ns) t cyc 5.13 6.76 8.59 10.64 t ckl 1.41 1.64 2.00 2.49 t ckh 2.43 3.29 4.25 5.32 t cc 2.17 3.02 3.96 4.99 t as 0.64 0.88 1.15 1.44 t ah 0.67 0.70 0.71 0.71 t cs 1.27 1.59 2.04 2.63 t ch 0.36 0.36 0.36 0.36 t ds 0.24 0.24 0.24 0.24 t dh 0.89 1.06 1.25 1.46 t ws 0.85 0.89 0.91 0.90 t wh 0.67 0.70 0.71 0.71 t acc 3.32 4.38 5.58 6.90 t da 2.90 3.95 5.15 6.47 t dz 0.76 0.94 1.13 1.34 t zd 0.89 1.07 1.26 1.46 t od 1.02 1.20 1.40 1.60 power ( m w/mhz) power_read 143.73 276.51 419.61 573.02 power_write 166.62 353.80 584.54 858.84 power_standby 1.27 1.39 1.51 1.63 area ( m m) width 1063.71 2012.43 2961.15 3909.87 height 524.26 873.70 1223.14 1572.58
samsung asic 5-111 STD111 dpsram_lp low-power dual-port synchronous static ram reference table * for ymux=16 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) notes: 1. in power consumption of dpsram_lp, only one port is measured and the other port is isolated. 2. standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 1024 2048 3072 4096 bpw 8 162432 timing (ns) t cyc 5.18 6.92 8.74 10.62 t ckl 1.42 1.61 1.89 2.24 t ckh 2.44 3.29 4.25 5.32 t cc 2.17 3.02 3.96 5.00 t as 0.60 0.80 1.02 1.27 t ah 0.67 0.70 0.71 0.71 t cs 1.26 1.53 1.89 2.36 t ch 0.36 0.36 0.36 0.36 t ds 0.24 0.24 0.24 0.24 t dh 0.87 1.02 1.19 1.37 t ws 0.85 0.89 0.91 0.90 t wh 0.67 0.70 0.71 0.71 t acc 3.36 4.43 5.62 6.94 t da 2.91 3.97 5.16 6.94 t dz 0.74 0.89 1.06 1.24 t zd 0.87 1.03 1.20 1.36 t od 1.00 1.16 1.33 1.51 power ( m w/mhz) power_read 102.73 197.93 298.62 404.79 power_write 120.48 254.06 412.66 596.28 power_standby 1.28 1.37 1.49 1.62 area ( m m) width 1063.71 2012.43 2961.15 3909.87 height 524.26 873.70 1223.14 1572.58
STD111 5-112 samsung asic dpsram_lp low-power dual-port synchronous static ram reference table * for ymux=32 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) notes: 1. in power consumption of dpsram_lp, only one port is measured and the other port is isolated. 2. standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 2048 4096 6144 8192 bpw 4 8 12 16 timing (ns) t cyc 5.16 6.91 8.74 10.65 t ckl 1.43 1.67 1.93 2.19 t ckh 2.44 3.29 4.25 5.32 t cc 2.17 3.02 3.96 5.00 t as 0.59 0.79 1.01 1.26 t ah 0.67 0.70 0.71 0.71 t cs 1.27 1.59 1.93 2.28 t ch 0.36 0.36 0.36 0.36 t ds 0.24 0.24 0.24 0.24 t dh 0.86 1.00 1.16 1.33 t ws 0.85 0.89 0.91 0.91 t wh 0.67 0.70 0.71 0.71 t acc 3.43 4.52 5.71 7.03 t da 2.94 3.99 5.19 6.51 t dz 0.73 0.87 1.03 1.19 t zd 0.86 1.01 1.16 1.32 t od 0.99 1.14 1.29 1.46 power ( m w/mhz) power_read 88.33 165.78 246.32 329.93 power_write 103.72 212.70 337.55 478.29 power_standby 1.28 1.36 1.47 1.60 area ( m m) width 1063.71 2012.43 2961.15 3909.87 height 524.26 873.70 1223.14 1572.58
samsung asic 5-113 STD111 dpsram_lp low-power dual-port synchronous static ram timing diagrams read cycle write cycle t as a t ah (csn = low, oen = low, di = dont care) t acc wen t ws t wh t da dout t cyc ck t ckl t ckh a0 a2 valid m[a0] m[a1] m[a2] a1 t as a t ah (csn= low, oen = dont care) wen t ws t wh di t cyc ck t ckl t ckh a0 a2 a1 t ds t dh d0 d2 d1
STD111 5-114 samsung asic dpsram_lp low-power dual-port synchronous static ram read cycle with csn controlled oen controlled output enable contention mode note: don't care means the condition that these pins are in normal operation mode. t as a t ah (oen = low, wen = high, di = dont care) csn t cs t ch dout t cyc ck t ckl t ckh a0 a2 a1 t da t acc m[a1] m[a0] (ck, a, wen, di, csn = dont care) t od t dz hi-z valid oen dout hi-z t zd ck1 tcc ck2 (a1 = a2)
samsung asic 5-115 STD111 sparam_lp low-power single-port asynchronous static ram logic symbol function description sparam_lp is a single-port asynchronous static ram which is provided as a compiler. sparam_lp is intended for use in low-power applications. at the falling edge of wen, the write cycle is initiated. at the rising edge of wen, the write cycle is ended. during the write cycle, the data on di[] is written into the memory location speci?ed on a[]. the read cycle is initiated when wen is high and csn is low. the data at dout[] become valid after a delay whenever a[] transition is detected. while in standby mode that csn is high, a[] and di[] are disabled, data stored in the memory is retained and dout[] remains stable. when oen is high, dout[] is placed in a high-impedance state. sparam_lp function table csn wen oen a di dout comment x x h x x z unconditional tri-state output h x l x x dout(t-1) de-selected (standby mode) l l valid valid dout(t-1) write cycle starts l - l valid valid mem(a) write cycle ends and read cycle starts l l l stable valid dout(t-1) write cycle l h l toggle x mem(a) read cycle features ? suitable for low-power applications ? standby (power down) mode available ? separated data i/o ? asynchronous operation ? asynchronous tri-state output ? address transition detectors ? write enable transition detector ? chip select transition detector ? bank select transition detector ? automatic power-down mode ? low noise output optimization ? zero standby current ? flexible aspect ratio ? dual bank scheme available ? up to 256kbits capacity ? up to 16k number of words ? up to 128 number of bit per word csn wen oen a [m-1:0] di [b-1:0] sparam_lp_xmb dout [b-1:0] notes: 1. words (w) is the number of words in sparam_lp. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the column mux types. 5. m = log 2 w 4. banks(ba) is the number of banks.
STD111 5-116 samsung asic sparam_lp low-power single-port asynchronous static ram parameter description sparam_lp is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bit per word(b), column mux(y) and number of banks(ba). pin descriptions pin capacitance unit: [sl] note: each pins capacitance is exactly same regardless of available mux types for same bank. parameters ymux = 4 ymux = 8 ymux = 16 ymux = 32 words (w) ba = 1 min 32 64 128 256 max 1024 2048 4096 8192 step 16 32 64 128 ba = 2 min 64 128 256 512 max 2048 4096 8192 16384 step 32 64 128 256 bpw (b) min 1111 max 128 64 32 16 step 1111 name i/o description csn chip enable chip select input. the chip select signal acts as the memory enable signal for selections of multiple blocks. when csn is high, the memory goes to stand-by (power down) mode and no access to the memory can occur. conversely, if low, a read or write access can occur. when csn falls, an access is initiated. wen read/write enable write enable input. the write enable signal selects the type of memory access. the high state for a read access and the low state for a write access. upon the rising edge of wen, a write access completed and a read access initiated. oen data output enable output enable input. the output enable signal controls the output drivers from driven to tri-state condition unconditionally. a [ ] address address input bus. a[] should be stable when wen is low. the address selects the location to be accessed. when the address changes, the transition is detected and the internal clock pulse is generated. di [ ] data input data input bus. the data input is written to the accessed location when wen is low. dout [ ] data output data output bus. the data output is data stored in the accessed location during a read access. data output driver has tri-state logic. when oen is low, the driver drives a certain value. otherwise, data output keeps hi-z state. during a write access, data on dout is predictable. csn wen oen a di dout ba = 1 1.87 1.87 1.87 3.91 1.87 7.12 ba = 2 1.87 1.87 1.87 3.91 1.87 7.12
samsung asic 5-117 STD111 sparam_lp low-power single-port asynchronous static ram block diagrams sparam_lp has 2 different physical architectures due to the word depth. optionally, one of these architectures is generated from sparam_lp compiler. in dual-bank, the bank selected by the address is only activated while the other bank is in idle mode. application notes 1. permitting over-the-cell routing in chip-level layout, over-the-cell routing in sparam_lp is permitted for only metal-5 layer. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of sparam_lp. 4. avoiding short transition on the address bus in sparam_lp, rather than the write operation which is synchronously performed by wen signal, the read operation is asynchronously performed whenever the address transition is occurred. in this case, if the short transition on the address, called a skew, is happened, since sparam_lp recognizes the short address transition as the stable address transition and do perform a read operation. at that time, while in the read operation, the data stored in the memory may be corrupted due to the short transition. to prevent such fail, the stable address cycle time (tcyc) is required. the essential requirement to recognize valid address transition is that at least minimum address period should be equal or greater than tacc (access time). 5. power reduction during standby mode. the standby power is measured on the condition that only csn is in disable mode and other signals are in operation mode. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while standby mode. <1-bank> ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. i/o driver address buffers i/o driver <2-bank> ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. y-dec & sense amp. control block y-dec & sense amp. ram core word-line decoder x-dec word-line decoder ram core i/o driver address buffers i/o driver
STD111 5-118 samsung asic sparam_lp low-power single-port asynchronous static ram characteristics de?nition for ac timing (ns) symbol description symbol description t cyc address cycle time t as address setup time t cas address setup time for csn rise t ah address hold time t wh wen hold time t cs csn setup time t ch csn hold time t ds data-in setup time t dh data-in hold time t wen wen pulse width low t acc data access time for read cycle t wacc data access time for wen rise t da de-access time t wda de-access time for wen rise t zd dout high-z to drive time t dz dout drive to high-z time t od oen to valid output time de?nition for power consumption ( m w/mhz) power_read the dynamic average power consumption while in a read cycle power_write the dynamic average power consumption while in a write cycle power_standby the standby power consumption while csn is high de?nition for area ( m m) width the physical width in x-direction height the physical height in y-direction
samsung asic 5-119 STD111 sparam_lp low-power single-port asynchronous static ram reference table * for ymux=4 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 256 512 512 1024 768 1536 1024 2048 bpw 32 32 64 64 96 96 128 128 ba 12121212 timing (ns) t cyc 4.24 4.35 4.68 4.83 5.11 5.32 5.55 5.81 t as 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t cas 4.19 4.29 4.62 4.78 5.06 5.27 5.49 5.75 t ah 1.78 1.79 2.19 2.21 2.61 2.63 3.03 3.05 t wh 4.19 4.29 4.62 4.78 5.06 5.27 5.49 5.75 t ds 0.10 0.09 0.12 0.17 0.11 0.20 0.07 0.17 t dh 0.66 0.63 0.73 0.69 0.85 0.74 0.94 0.80 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.19 1.31 1.28 1.46 1.38 1.60 1.47 1.75 t wen 2.93 3.10 3.30 3.55 3.67 4.01 4.04 4.47 t acc 4.24 4.35 4.68 4.83 5.11 5.32 5.55 5.81 t da 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 1.24 1.36 1.33 1.51 1.43 1.65 1.52 1.80 t dz 0.34 0.35 0.42 0.42 0.49 0.49 0.56 0.56 t zd 0.29 0.29 0.37 0.36 0.44 0.44 0.52 0.52 t od 0.45 0.45 0.53 0.53 0.61 0.61 0.69 0.69 power ( m w/mhz) power_read 127.68 155.00 237.46 301.07 352.92 469.66 474.07 660.77 power_write 205.47 230.05 440.97 513.60 751.22 898.01 1136.22 1383.27 power_standby 17.01 27.91 31.03 53.82 45.17 84.92 59.44 121.20 area ( m m) width 831.84 831.84 1437.28 1437.28 2042.72 2042.72 2648.17 2648.17 height 529.32 1017.68 853.16 1665.36 1177.00 2313.04 1500.84 2960.72
STD111 5-120 samsung asic sparam_lp low-power single-port asynchronous static ram reference table * for ymux=8 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 512 1024 1024 2048 1536 3072 2048 4096 bpw 16 16 32 32 48 48 64 64 ba 12121212 timing (ns) t cyc 4.26 4.37 4.70. 4.86 5.13 5.35 5.56 5.83 t as 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t cas 4.21 4.32 4.64 4.81 5.08 5.29 5.51 5.78 t ah 1.78 1.79 2.19 2.21 2.61 2.63 3.03 3.05 t wh 4.21 4.32 4.64 4.81 5.08 5.29 5.51 5.78 t ds 0.10 0.18 0.13 0.27 0.12 0.30 0.07 0.28 t dh 0.64 0.58 0.73 0.63 0.83 0.69 0.92 0.75 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.21 1.34 1.30 1.49 1.40 1.64 1.49 1.79 t wen 2.96 3.16 3.33 3.62 3.70 4.07 4.07 4.53 t acc 4.26 4.37 4.70 4.86 5.13 5.35 5.56 5.83 t da 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 1.26 1.39 1.35 1.54 1.45 1.69 1.54 1.83 t dz 0.32 0.32 0.37 0.37 0.42 0.42 0.47 0.47 t zd 0.26 0.26 0.31 0.31 0.37 0.37 0.42 0.42 t od 0.42 0.42 0.48 0.48 0.53 0.53 0.58 0.58 power ( m w/mhz) power_read 89.72 112.08 154.81 200.04 222.74 299.30 293.53 409.88 power_write 136.41 153.87 261.39 306.79 423.69 510.31 623.29 764.42 power_standby 13.54 23.41 23.38 41.44 33.28 62.12 43.24 85.43 area ( m m) width 831.84 831.84 1437.28 1437.28 2042.72 2042.72 2648.17 2648.17 height 529.32 1017.68 853.16 1665.36 1177.00 2313.04 1500.84 2960.72
samsung asic 5-121 STD111 sparam_lp low-power single-port asynchronous static ram reference table * for ymux=16 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 1024 2048 2048 4096 3072 6144 4096 8192 bpw 8 8 16 16 24 24 32 32 ba 12121212 timing (ns) t cyc 4.30 4.43 4.73 4.92 5.16 5.40 5.60 5.89 t as 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t cas 4.24 4.38 4.68 4.86 5.11 5.35 5.55 5.83 t ah 1.78 1.79 2.20 2.21 2.61 2.63 3.03 3.05 t wh 4.24 4.38 4.68 4.86 5.11 5.35 5.55 5.83 t ds 0.09 0.12 0.14 0.24 0.14 0.30 0.10 0.30 t dh 0.59 0.48 0.68 0.53 0.77 0.59 0.87 0.64 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.25 1.40 1.34 1.55 1.43 1.69 1.53 1.84 t wen 3.02 3.28 3.40 3.74 3.77 4.19 4.14 4.65 t acc 4.30 4.43 4.73 4.92 5.16 5.40 5.60 5.89 t da 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 1.30 1.45 1.39 1.60 1.48 1.74 1.58 1.89 t dz 0.31 0.31 0.35 0.35 0.38 0.38 0.42 0.42 t zd 0.25 0.25 0.29 0.29 0.32 0.32 0.36 0.36 t od 0.40 0.40 0.44 0.44 0.48 0.48 0.52 0.52 power ( m w/mhz) power_read 69.37 89.23 112.69 148.76 157.46 213.99 203.68 284.91 power_write 101.53 117.46 171.73 205.67 260.59 319.18 368.11 457.99 power_standby 11.60 21.92 19.60 36.39 27.63 52.22 35.70 69.41 area ( m m) width 831.84 831.84 1437.28 1437.28 2042.72 2042.72 2648.17 2648.17 height 529.32 1017.68 853.16 1665.36 1177.00 2313.04 1500.84 2960.72
STD111 5-122 samsung asic sparam_lp low-power single-port asynchronous static ram reference table * for ymux=32 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 2048 4096 4096 8192 6144 12288 8192 16384 bpw 448812121616 ba 12121212 timing (ns) t cyc 4.39 4.58 4.81 5.06 5.23 5.53 5.65 6.01 t as 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t cas 4.34 4.52 4.76 5.00 5.18 5.47 5.60 5.95 t ah 1.77 1.78 2.19 2.21 2.61 2.63 3.03 3.06 t wh 4.34 4.52 4.76 5.00 5.18 5.47 5.60 5.95 t ds 0.11 0.26 0.18 0.38 0.19 0.48 0.15 0.55 t dh 0.49 0.29 0.58 0.34 0.67 0.38 0.77 0.43 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.31 1.51 1.40 1.66 1.49 1.81 1.58 4.96 t wen 3.16 3.53 3.53 3.98 3.89 4.42 4.25 4.87 t acc 4.39 4.58 4.81 5.06 5.23 5.53 5.65 6.01 t da 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 1.36 1.57 1.45 1.72 1.54 1.87 1.63 2.01 t dz 0.29 0.29 0.34 0.34 0.38 0.38 0.40 0.40 t zd 0.23 0.23 0.27 0.27 0.60 0.30 0.34 0.34 t od 0.38 0.38 0.44 0.44 0.48 0.48 0.51 0.51 power ( m w/mhz) power_read 57.70 75.79 90.74 121.92 124.49 170.91 158.97 222.74 power_write 84.02 106.24 127.80 163.74 180.92 233.92 243.37 316.77 power_standby 11.90 25.70 18.92 38.73 25.95 52.52 32.99 67.00 area ( m m) width 831.84 831.84 1437.28 1437.28 2042.72 2042.72 2648.17 2648.17 height 529.32 1017.68 853.16 1665.36 1177.00 2313.04 1500.84 2960.72
samsung asic 5-123 STD111 sparam_lp low-power single-port asynchronous static ram timing diagrams read cycle read cycle with csn-controlled basic write cycle a (wen = high, csn = low, oen = low, di = dont care) t acc t da dout t cyc m[a0] m[a1] m[a2] m[a3] a0 a1 a2 a3 a t acc t da dout t cyc valid m[a0] m[a2] a0 a1 a2 a3 t acc t da m[a1] t acc t da csn (oen = low, wen = high, di = dont care) t cas a t ah (csn = low, oen = dont care) wen t as t wen di a0 a1 a2 d1 d2 d0 t ds t dh
STD111 5-124 samsung asic sparam_lp low-power single-port asynchronous static ram write cycle with csn controlled read-modi?ed-write cycle notes: 1. when the wen hold time after the last address bit transition is satisfied, d+ will toggle in response to a successful read of the initial contents of address a1. when the wen hold time after the last address bit transition is not satisfied, d+ will go to unknown state. 2. address bits are not allowed to change while wen is low. if they do change, then the data for one or more addresses in the memory array may be corrupted. oen controlled output enable note: don't care means the condition that these pins are in normal operation mode. a t ah (oen = dont care) wen t as t wen di a0 a1 a2 d1 d2 d0 t ds t dh csn t cs t ch a t acc t da dout t cyc m[a0] m[a2] a0 a1 a2 d+ t acc t wacc wen (csn = low, oen = low) di d1 d2 d0 t ds t dh t cyc t as t wen t ah d1 t da t wda (a, wen, di, csn = dont care) t od t dz hi-z valid oen dout hi-z t zd
samsung asic 5-125 STD111 drom_lp low-power synchronous diffusion programmable rom logic symbol function description drom_lp is a synchronous diffusion programmable rom which is provided as a compiler. drom_lp is intended for use in low-power applications. the read cycle is initiated at the rising edge of ck. the data at dout[] become valid after a delay. while in standby mode that csn is high, a[] is disabled and dout[] remains stable. when oen is high, dout is placed in a high-impedance state. drom function table parameter description drom_lp is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bits per word(b) and column mux(y) and number of banks(ba). ck csn oen a dout comment x x h x z unconditional tri-state output x h l x dout(t-1) de-selected (standby mode) - l l valid mem(a) read cycle features ? suitable for low-power applications ? diffusion-programmable code available ? synchronous operation ? asynchronous tri-state output ? latched inputs and outputs ? automatic power-down mode available ? low noise output optimization ? zero standby current ? flexible aspect ratio ? dual-bank scheme available ? up to 512kbits capacity ? up to 16k number of words ? up to 128 number of bits per word ck csn oen dout [bC1:0] drom_lp_xmb a [m-1:0] notes: 1. words (w) is the number of words in drom_lp. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the column mux types. 5. m = log 2 w 4. banks (ba) is the number of banks.
STD111 5-126 samsung asic drom_lp low-power synchronous diffusion programmable rom pin descriptions pin capacitance (unit = sl) note: each pins capacitance is exactly same regardless of available mux types for same bank. parameters ymux = 8 ymux = 16 ymux = 32 words (w) ba = 1 min 64 128 256 max 2048 4096 8192 step 32 64 128 ba = 2 min 128 256 512 max 4096 8192 16384 step 64 128 256 bpw (b) min 2 2 2 max 128 64 32 step 1 1 1 name i/o description ck clock clock input. csn and a[] are latched into the rom on the rising edge of ck. if csn is low on the rising edge of ck, the rom is in read mode. csn chip enable chip enable input. the chip enable is active-low and is latched into the rom on the rising edge of ck. when csn is low, the rom is enabled for reading. when csn is high, the rom goes to the standby mode and is disabled for reading. dout remains previous data output. oen data output enable data output enable input. the data output enable is asynchronously operated regardless of any inputs. when oen is high, dout is disabled and goes to high-impedance state. a [ ] address address input bus. the address is latched into the rom on the rising edge of ck. dout [ ] data output data output bus. data output is valid after the rising edge of ck while the rom is in read mode. ck csn oen a dout ba = 1 4.581 5.336 3.799 5.623 8.015 ba = 2 4.392 4.322 3.050 4.512 8.189
samsung asic 5-127 STD111 drom_lp low-power synchronous diffusion programmable rom block diagrams drom_lp has 2 different physical architectures due to the word depth. for a speci?c con?guration, only one of these architectures is generated from drom_lp compiler. power is consumed by the bank that is selected by the address whereas the other bank will be in idle mode. application notes 1. permitting over-the-cell routing in chip-level layout, over-the-cell routing in drom_lp is permitted for only metal-5 layer. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of drom_lp. 4. power reduction during standby mode. the standby power is measured on the condition that only csn is in disable mode and other signals are in operation mode. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while standby mode. <1-bank> rom core word-line decoder x-dec word-line decoder rom core y-dec & sense amp. control block y-dec & sense amp. output driver address buffers output driver <2-bank> rom core word-line decoder x-dec word-line decoder rom core y-dec & sense amp. control block y-dec & sense amp. y-dec & sense amp. control block y-dec & sense amp. rom core word-line decoder x-dec word-line decoder rom core output driver address buffers output driver
STD111 5-128 samsung asic drom_lp low-power synchronous diffusion programmable rom characteristics de?nition for ac timing (ns) symbol description symbol description t cyc clock cycle time t ch csn hold time from ck rise t ckl clock pulse width low t acc data access time t ckh clock pulse width high t da de-access time t as address setup time t dz dout drive to high-z time t ah address hold time t zd dout high-z to drive time t cs csn setup time t od oen to valid output de?nition for power consumption ( m w/mhz) power_read the dynamic average power consumption while in a read cycle power_standby the standby power consumption while csn is high de?nition for area ( m m) width the physical width in x-direction height the physical height in y-direction
samsung asic 5-129 STD111 drom_lp low-power synchronous diffusion programmable rom reference table * for ymux=8 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 512 1024 1024 2048 1536 3072 2048 4096 bpw 32 32 64 64 96 96 128 128 ba 12 1 212 1 2 timing (ns) t cyc 4.79 4.98 6.17 6.39 7.78 8.03 9.64 9.91 t ckl 2.02 2.02 2.44 2.44 2.86 2.86 3.26 3.26 t ckh 2.11 2.30 2.56 2.78 3.04 3.29 3.54 3.82 t as 0.10 1.33 0.10 1.37 0.10 1.41 0.10 1.45 t ah 0.69 0.88 0.69 0.91 0.69 0.94 0.69 0.97 t cs 0.87 1.23 0.87 1.27 0.87 1.31 0.87 1.35 t ch 0.61 0.81 0.61 0.84 0.61 0.87 0.61 0.90 t acc 3.37 3.64 3.86 4.17 4.44 4.80 5.11 5.51 t da 2.89 3.09 3.47 3.72 4.10 4.37 4.76 5.07 t dz 0.67 0.65 0.75 0.74 0.84 0.83 0.92 0.92 t zd 0.77 0.76 0.85 0.84 0.93 0.92 1.01 0.99 t od 0.90 0.88 0.98 0.97 1.06 1.05 1.14 1.12 power ( m w/mhz) power_read 169.22 179.53 377.62 399.51 641.30 678.26 960.25 1015.80 power_standby 0.96 4.90 1.07 5.78 1.17 6.64 1.25 7.49 area ( m m) width 511.53 511.53 883.93 883.93 1256.06 1256.06 1627.93 1627.93 height 214.62 405.22 295.26 566.50 375.90 727.78 456.54 889.06
STD111 5-130 samsung asic drom_lp low-power synchronous diffusion programmable rom reference table * for ymux=16 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 1024 2048 2048 4096 3072 6144 4096 8192 bpw 16 16 32 32 48 48 64 64 ba 12 1 212 1 2 timing (ns) t cyc 4.80 4.99 6.17 6.39 7.78 8.03 9.63 9.91 t ckl 2.02 2.02 2.44 2.44 2.86 2.86 3.26 3.26 t ckh 2.11 2.31 2.56 2.78 3.04 3.29 3.54 3.82 t as 0.10 1.33 0.10 1.37 0.10 1.41 0.10 1.45 t ah 0.69 0.88 0.69 0.91 0.69 0.94 0.69 0.97 t cs 0.87 1.23 0.87 1.27 0.87 1.31 0.87 1.35 t ch 0.61 0.81 0.61 0.84 0.61 0.87 0.61 0.90 t acc 3.42 3.71 3.91 4.25 4.48 4.87 5.15 5.58 t da 2.90 3.11 3.48 3.73 4.11 4.39 4.77 5.08 t dz 0.63 0.63 0.70 0.69 0.76 0.75 0.82 0.81 t zd 0.74 0.73 0.80 0.79 0.86 0.84 0.91 0.90 t od 0.87 0.86 0.93 0.92 0.99 0.97 1.04 1.03 power ( m w/mhz) power_read 121.24 130.01 156.66 273.76 421.02 438.26 614.32 653.51 power_standby 0.96 4.89 1.05 5.75 1.14 6.61 1.21 7.46 area ( m m) width 511.24 511.24 883.86 883.86 1256.06 1256.06 1627.86 1627.86 height 214.62 405.22 295.26 566.50 375.90 727.78 456.54 889.06
samsung asic 5-131 STD111 drom_lp low-power synchronous diffusion programmable rom reference table * for ymux=32 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 2048 4096 4096 8192 6144 12288 8192 16384 bpw 8 8 16 16 24 24 32 32 ba 12 1 212 1 2 timing (ns) t cyc 4.80 4.99 6.17 6.39 7.78 8.03 9.64 9.92 t ckl 2.02 2.02 2.44 2.44 2.86 2.86 3.26 3.26 t ckh 2.12 2.31 2.56 2.78 3.04 3.29 3.55 3.82 t as 0.10 1.33 0.10 1.37 0.10 1.41 0.10 1.45 t ah 0.68 0.88 0.68 0.91 0.68 0.94 0.68 0.97 t cs 0.87 1.23 0.87 1.27 0.87 1.31 0.87 1.35 t ch 0.61 0.81 0.61 0.84 0.61 0.87 0.61 0.90 t acc 3.49 3.85 3.98 4.39 4.55 5.01 5.22 5.72 t da 2.91 3.13 3.50 3.75 4.12 4.41 4.78 5.10 t dz 0.62 0.61 0.67 0.66 0.72 0.71 0.76 0.75 t zd 0.73 0.72 0.77 0.76 0.82 0.81 0.86 0.85 t od 0.85 0.84 0.90 0.86 0.95 0.93 0.99 0.98 power ( m w/mhz) power_read 97.93 105.95 197.49 212.21 312.62 334.97 443.33 474.24 power_standby 0.95 4.89 1.04 5.76 1.12 6.63 1.19 7.50 area ( m m) width 510.65 510.65 883.69 883.69 1256.06 1256.06 1627.76 1627.76 height 214.61 405.22 295.26 566.50 375.90 727.78 456.54 889.06
STD111 5-132 samsung asic drom_lp low-power synchronous diffusion programmable rom timing diagrams read cycle read cycle with csn controlled oen controlled output enable note : dont care means the condition that these pins are in normal operation mode. t as a t ah (csn, oen = low) t acc t da dout t cyc ck t ckl t ckh a0 a2 valid m[a0] m[a1] m[a2] a1 (oen = low) t ch t cs csn dout a1 a2 a0 a t as t ah m[a1] t acc t da ck t ckl t ckh t cyc m[a0] (ck, a, csn = dont care) t od t dz hi-z valid oen dout hi-z t zd
samsung asic 5-133 STD111 mrom_lp low-power synchronous metal programmable rom logic symbol function description mrom_lp is a synchronous diffusion programmable rom which is provided as a compiler. mrom_lp is intended for use in low-power applications. the read cycle is initiated at the rising edge of ck. the data at dout[] become valid after a delay. while in standby mode that csn is high, a[] is disabled and dout[] remains stable. when oen is high, dout is placed in a high-impedance state. mrom function table ck csn oen a dout comment x x h x z unconditional tri-state output x h l x dout(t-1) de-selected (standby mode) - l l valid mem(a) read cycle features ? suitable for low-power applications ? metal-2 programmable code available ? synchronous operation ? asynchronous tri-state output ? latched inputs and outputs ? automatic power-down mode ? low noise output optimization ? zero standby current ? flexible aspect ratio ? dual-bank scheme available ? up to 512kbits capacity ? up to 16k number of words ? up to 128 number of bits per word ck csn mrom_lp_xmb dout [b-1:0] oen a [m-1:0] notes: 1. words (w) is the number of words in mrom_lp. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the column mux types. 5. m = log 2 w 4. banks (ba) is the number of banks.
STD111 5-134 samsung asic mrom_lp low-power synchronous metal programmable rom parameter description mrom_lp is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bits per word(b), column mux(y) and number of banks(ba). pin descriptions pin capacitance (unit = sl) note: each pins capacitance is exactly same regardless of available mux types for same bank. parameters ymux = 8 ymux = 16 ymux = 32 words (w) ba = 1 min 64 128 256 max 2048 4096 8192 step 32 64 128 ba = 2 min 128 256 512 max 4096 8192 16384 step 64 128 256 bpw (b) min 2 2 2 max 128 64 32 step 1 1 1 name i/o description ck clock clock input. csn and a[] are latched into the rom on the rising edge of ck. if csn is low on the rising edge of ck, the rom is in read mode. csn chip enable chip enable input. the chip enable is active-low and is latched into the rom on the rising edge of ck. when csn is low, the rom is enabled for reading. when csn is high, the rom goes to the standby mode and is disabled for reading. dout remains previous data output. oen data output enable data output enable input. the data output enable is asynchronously operated regardless of any inputs. when oen is high, dout is disabled and goes to high-impedance state. a [ ] address address input bus. the address is latched into the rom on the rising edge of ck. dout [ ] data output data output bus. data output is valid after the rising edge of ck while the rom is in read mode. ck csn oen a dout ba = 1 4.346 4.741 3.257 7.865 8.308 ba = 2 5.190 5.288 3.405 4.614 8.463
samsung asic 5-135 STD111 mrom_lp low-power synchronous metal programmable rom block diagrams mrom_lp has 2 different physical architectures due to the word depth. for a speci?c con?guration, only one of these architectures is generated from mrom_lp compiler. power is consumed by the bank that is selected by the address whereas the other bank will be in idle mode. application notes 1. permitting over-the-cell routing in chip-level layout, over-the-cell routing in mrom_lp is permitted for only metal-5 layer. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of mrom_lp. 4. power reduction during standby mode. the standby power is measured on the condition that only csn is in disable mode and other signals are in operation mode. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while standby mode. <1-bank> rom core word-line decoder x-dec word-line decoder rom core y-dec & sense amp. control block y-dec & sense amp. output driver address buffers output driver <2-bank> rom core word-line decoder x-dec word-line decoder rom core y-dec & sense amp. control block y-dec & sense amp. y-dec & sense amp. control block y-dec & sense amp. rom core word-line decoder x-dec word-line decoder rom core output driver address buffers output driver
STD111 5-136 samsung asic mrom_lp low-power synchronous metal programmable rom characteristics de?nition for ac timing (ns) symbol description symbol description t cyc clock cycle time t ch csn hold time from ck rise t ckl clock pulse width low t acc data access time t ckh clock pulse width high t da de-access time t as address setup time t dz dout drive to high-z time t ah address hold time t zd dout high-z to drive time t cs csn setup time t od oen to valid output de?nition for power consumption ( m w/mhz) power_read the dynamic average power consumption while in a read cycle power_standby the standby power consumption while csn is high de?nition for area ( m m) width the physical width in x-direction height the physical height in y-direction
samsung asic 5-137 STD111 mrom_lp low-power synchronous metal programmable rom reference table * for ymux=8 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 512 1024 1024 2048 1536 3072 2048 4096 bpw 32 32 64 64 96 96 128 128 ba 12 1 212 1 2 timing (ns) t cyc 5.73 5.95 8.43 8.71 11.31 11.64 14.36 14.74 t ckl 2.15 2.15 2.72 2.72 3.24 3.24 3.72 3.72 t ckh 2.27 2.49 2.87 3.15 3.53 3.86 4.23 4.62 t as 0.10 1.34 0.10 1.41 0.10 1.48 0.10 1.55 t ah 0.65 0.87 0.65 0.92 0.65 0.98 0.65 1.03 t cs 0.84 1.24 0.84 1.31 0.84 1.38 0.84 1.45 t ch 0.58 0.80 0.58 0.86 0.58 0.91 0.58 0.97 t acc 3.55 3.84 4.28 4.64 5.12 5.55 6.07 6.57 t da 3.11 3.34 3.93 4.22 4.80 5.16 5.73 6.14 t dz 0.63 0.63 0.72 0.72 0.81 0.81 0.89 0.90 t zd 0.74 0.74 0.82 0.83 0.90 0.91 0.98 0.99 t od 0.86 0.87 0.95 0.96 1.03 1.04 1.11 1.12 power ( m w/mhz) power_read 198.36 207.26 475.39 496.65 848.69 885.97 1318.24 1375.22 power_standby 0.97 5.58 1.07 7.17 1.17 8.77 1.25 10.36 area ( m m) width 484.49 484.49 876.09 876.09 1267.42 1267.42 1658.49 1658.49 height 275.80 529.46 419.16 816.18 562.52 1102.90 705.88 1389.62
STD111 5-138 samsung asic mrom_lp low-power synchronous metal programmable rom reference table * for ymux=16 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 1024 2048 2048 4096 3072 6144 4096 8192 bpw 16 16 32 32 48 48 64 64 ba 12 1 212 1 2 timing (ns) t cyc 5.74 5.96 8.43 8.71 11.31 11.64 14.36 14.75 t ckl 2.15 2.15 2.72 2.72 3.24 3.24 3.72 3.72 t ckh 2.27 2.49 2.87 3.15 3.53 3.86 4.23 4.62 t as 0.10 1.34 0.10 1.41 0.10 1.48 0.10 1.55 t ah 0.65 0.87 0.65 0.92 0.65 0.98 0.65 1.03 t cs 0.85 1.24 0.85 1.31 0.85 1.38 0.85 1.45 t ch 0.58 0.80 0.58 0.86 0.58 0.91 0.58 0.97 t acc 3.59 3.91 4.32 4.72 5.16 5.62 6.11 6.64 t da 3.12 3.36 3.94 4.24 4.81 5.17 5.74 6.16 t dz 0.60 0.60 0.66 0.67 0.72 0.73 0.78 0.79 t zd 0.71 0.71 0.77 0.77 0.82 0.83 0.88 0.89 t od 0.84 0.84 0.90 0.90 0.95 0.96 1.01 1.01 power ( m w/mhz) power_read 135.73 145.00 307.50 325.72 529.17 558.24 800.72 842.55 power_standby 0.96 5.57 1.05 7.15 1.13 8.73 1.20 10.30 area ( m m) width 484.20 484.20 876.02 876.02 1267.42 1267.42 1658.42 1658.42 height 275.80 529.46 419.16 816.18 562.52 1102.90 705.88 1389.62
samsung asic 5-139 STD111 mrom_lp low-power synchronous metal programmable rom reference table * for ymux=32 (typical process, 2.5v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode. parameters words 2048 4096 4096 8192 6144 12288 8192 16384 bpw 8 8 16 16 24 24 32 32 ba 12 1 212 1 2 timing (ns) t cyc 5.74 5.96 8.43 8.70 11.30 11.63 14.36 14.74 t ckl 2.15 2.15 2.72 2.71 3.24 3.23 3.72 3.71 t ckh 2.27 2.49 2.87 3.15 3.53 3.86 4.23 4.62 t as 0.10 1.34 0.10 1.41 0.10 1.48 0.10 1.55 t ah 0.65 0.87 0.65 0.92 0.65 0.98 0.65 1.04 t cs 0.85 1.24 0.85 1.31 0.85 1.38 0.85 1.45 t ch 0.58 0.80 0.58 0.86 0.58 0.91 0.58 0.97 t acc 3.67 4.05 4.40 4.85 5.24 5.76 6.18 6.77 t da 3.13 3.38 3.95 4.26 4.83 5.19 5.76 6.18 t dz 0.59 0.59 0.63 0.64 0.68 0.68 0.72 0.73 t zd 0.70 0.70 0.74 0.74 0.78 0.79 0.83 0.83 t od 0.82 0.83 0.87 0.87 0.91 0.92 0.95 0.96 power ( m w/mhz) power_read 106.53 115.07 226.29 242.14 372.56 396.68 545.33 578.71 power_standby 0.95 5.57 1.04 7.16 1.12 8.76 1.18 10.37 area ( m m) width 483.61 483.61 875.85 875.85 1267.42 1267.42 1658.32 1658.32 height 275.80 529.46 419.16 816.18 562.52 1102.90 705.88 1389.62
STD111 5-140 samsung asic mrom_lp low-power synchronous metal programmable rom timing diagrams read cycle read cycle with csn controlled oen controlled output enable note: dont care means the condition that these pins are in normal operation mode t as a t ah (csn, oen = low) t acc t da dout t cyc ck t ckl t ckh a0 a2 valid m[a0] m[a1] m[a2] a1 (oen = low) t ch t cs csn dout a1 a2 a0 a[ ] t as t ah m[a1] t acc t da ck t ckl t ckh t cyc m[a0] (ck, a = dont care, csn = low) t od t dz hi-z valid oen dout hi-z t zd
compiled macrocells compiled datapath macrocells samsung asic 5-141 STD111 compiled datapath macrocells datapath macro cell is a set of n-bit data operators that enables more efficient datapath module design and implementation. compiled datapath macro cell creates area-, speed- and power-optimized adders, subtracters, barrel shifters, and multipliers based on the user specified parameters. it creates a function mod- el, a timing information for simulation, and a verified hard macro layout. the followings are the summary of main features of compiled datapath macro cells: advanced design technique all of STD111 compiled datapath macro cells adopt very advanced design techniques to get optimized per- formances on the given parameters. some of those design techniques are as follows: hierarchical double carry select scheme to reduce carry-chain delay transmission gate multiplexing for data shifting allowing pipeline insertion in multiplication primitive standard cell compatible leaf cell layout allowing over-the-cell routing dense datapath module layout generation with topological regularity. flexible datapath macrocell design flow the implementation of datapath module is one of the most critical and important elements in the design of high performance systems; dsps, multimedia, graphics, microprocessors and so on. in these systems, the datapath modules are used much more than other designs and at the same time, datapath module affects the overall design performances. the macrocell generation flow is tightly integrated into apollo, avant! which is used as a main tool at a full chip layout step. by supporting an easy-to-use asic environment, achieving full custom-like density, per- formance, asic designers can expect improving productivity. in the design of datapath macro cell, the opti- mal module placement of leafcell is a key point to take advantage of inherent regularity in datapaths. an optimal datapath module placement can maximize density, minimize speed, bus line skew, power consump- tion and turn-around time in asic design. the design environment has been developed to support datapath macro cells as shown in below. this flow is tightly integrated from verilog, cadence, to apollo, avant!. with the pre-defined leafcell information and given parameters, the schematic generator gives a verilog structural netlist of datapath cell and the place- ment information of used leafcell instances. it enables the mapping of regularity from a logic design into a standard cell place-and-rout tool. you can get area- and performance-optimized layouts of datapath macro cells. figure 5-3 datapath instance generation flow leafcell parameter instance netilst instance place schematic apollo
compiled macrocell selection guide compiled macrocells STD111 5-142 samsung asic compiled macrocell selection guide type macrocell description datapath adder low-power/high-speed 4-to-64 bits addition/subtraction - double-carry select algorithm - 2's complement over?ow bs low-power/high-speed 4-to-64 bits barrel shifter - bi-directional shift and rotation - logical or arithmetic shift - external ?ller data is available mpy low-power/high-speed 6-to-64 bits modi?ed booth multiplier - 2's complement multiplication - 1-stage pipeline insertion is available
samsung asic 5-143 STD111 adder adder/subtracter function description the adder is an n -bit carry-select adder and subtracter which is provided as a compiler. the adder is intended to use in high-speed and low-power applications. it essentially adopts the double carry-select scheme which has hierarchically doubled carry-select groups of bits to allow the high-speed of addition/sub- traction operation. and in addition, the inside of each group is designed by a partial group-bypass scheme so as to acquire more high-speed. it performs a 2s complement addition/subtraction or unsigned-magnitude addition. the overflow flag shows the occurrence of overflow while adding two positive or two negative num- bers and it should be ignored while doing unsigned-magnitude operations. function table parameter description adder is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters. output function sout ain + bin + cin (addition) ain + ~bin + cin (subtraction) ovf (~sout [bitsC1]) ? (ain [bitsC1] ? bin [bitsC1]) + (sout [bitsC1]) ? (~ain [bitsC1]) ?(~ bin [bitsC1]) parameter name description range bits number of bits for the input data bus 4 to 64 sub 0: addition only; 1: addition/subtraction 0/1 ovf over?ow ?ag for signed operation 0/1 drv output drive strength 1/2 logic symbol features ? asynchronous operation ? 4 to 64 bit adder/subtracter ? high-speed/low-power operation ? 2s complement or unsigned-magnitude operation ? 2s complement overflow flag available ? sophisticated carry-select and group-bypass scheme ? two output drive strength available ain [bitsC1:0] sout [bitsC1:0] bin [bitsC1:0] cin sub (optional) cout ovf (optional) addsub__s_{_o_d

STD111 5-144 samsung asic adder adder/subtracter pin description pin capacitance [unit: pf ] block diagram name type description ain [ ] input augend in addition, minuend in subtraction bin [ ] addend in addition, subtrahend in subtraction cin carry-in in addition/subtraction it must be kept the high state in 2s complement subtraction. sub addition/subtraction ?ag (optional when the parameter sub = 1) sout[ ] output the result of addition/subtraction cout carry-out in addition/subtraction ovf the over?ow/under?ow of addition/subtraction (optional when the parameter ovf = 1) name case value ain[ ] all 0.0200 bin[ ] sub=0 sub=1 0.0200 0.0150 cin all 0.0349 sub sub=1 0.0143 bits add/sub selection carry generation p/g generation carry selection sum bin[ ] sub (optional) ain[ ] cout sout[ ] cin over?ow ovf(optional) generation block block block block block block

samsung asic 5-145 STD111 adder adder/subtracter timing diagram timing type de?nition timing type de?nition tphlas/tplhas propagation delay from ain[ ] to sout[ ] tphlbs/tplhbs propagation delay from bin[ ] to sout[ ] ttphlcs/tplhcs propagation delay from cin to sout [ ] tphlss/tplhss propagation delay from sub to sout [ ] tphlac/tplhac propagation delay from ain[ ] to cout tphlbc/tplhbc propagation delay from bin[ ] to cout tphlcc/tplhcc propagation delay from cin to cout tphlsc/tplhsc propagation delay from sub to cout tphlao/tplhao propagation delay from ain[ ] to ovf tphlbo/tplhbo propagation delay from bin[ ] to ovf tphlco/tplhco propagation delay from cin to ovf tphlso/tplhso propagation delay from sub to ovf tpdaas de-access time from ain[ ] to sout[ ] tpdabs de-access time from bin[ ] to sout[ ] tpdacs de-access time from cin to sout[ ] tpdass de-access time from sub to sout[ ] tplhas tphlas sout[ ] ain[ ] bin[ ] cin sub cout ovf tpdaas tplhbs tphlbs tpdabs tplhcs tphlcs tpdacs tplhss tphlss tpdass tplhac tphlac tplhbc tphlbc tplhcc tphlcc tplhsc tphlsc tplhao tphlao tplhbo tphlbo tplhco tphlco tplhso tphlso

STD111 5-146 samsung asic adder adder/subtracter characteristic reference table 1) timing characteristics [unit: ns] (typical process, 25 c, v dd =2.5v, c l =10, s=0.2, sa=0.5) symbol description unit symbol description unit b number of bits - s input slope ns v dd power supply voltage v sl standard load - c l output load sl sa input switching activity - type 8 24364864 case: sub=0, ovf=1, drv=1 tphlac/tplhac 0.98 0.90 1.44 1.47 1.72 1.80 1.93 2.06 2.12 2.27 tphlbc/tplhbc 0.95 0.90 1.42 1.47 1.69 1.80 1.91 2.05 2.09 2.27 tphlcc/tplhcc 0.67 0.77 1.13 1.33 1.41 1.66 1.62 1.92 1.81 2.13 tphlao/tplhao 1.08 1.38 1.74 1.96 2.15 2.33 2.49 2.64 2.84 2.97 tphlbo/tplhbo 1.09 1.36 1.74 1.94 2.15 2.30 2.49 2.61 2.85 2.94 tphlco/tplhco 0.95 1.07 1.60 1.65 2.01 2.02 2.36 2.33 2.71 2.66 tphlas/tplhas 1.14 1.29 1.73 1.80 2.09 2.12 2.38 2.37 2.66 2.63 tphlbs/tplhbs 1.14 1.26 1.73 1.77 2.09 2.09 2.38 2.35 2.65 2.60 tphlcs/tplhcs 1.00 0.98 1.59 1.49 1.95 1.80 2.24 2.06 2.52 2.32 tpdaas 0.35 0.35 0.35 0.35 0.35 tpdabs 0.35 0.35 0.35 0.35 0.35 tpdacs 0.25 0.25 0.25 0.25 0.25 case: sub=1, ovf=1, drv=1 tphlac/tplhac 0.98 0.90 1.45 1.48 1.73 1.82 1.73 1.82 2.14 2.30 tphlbc/tplhbc 1.27 1.09 1.74 1.66 2.02 2.00 2.02 2.00 2.44 2.48 tphlcc/tplhcc 0.67 0.76 1.14 1.34 1.42 1.68 1.42 1.68 1.83 2.16 tphlsc/tplhsc 1.01 1.19 1.07 1.89 1.11 2.30 1.11 2.30 1.13 2.88 tphlao/tplhao 1.08 1.37 1.78 1.99 2.19 2.37 2.19 2.37 2.80 2.94 tphlbo/tplhbo 1.27 1.67 1.96 2.29 2.37 2.66 2.37 2.66 2.98 3.24 tphlco/tplhco 0.96 1.06 1.64 1.69 2.05 2.06 2.05 2.06 2.66 2.63 tphlso/tplhso 1.54 1.53 1.60 2.35 1.64 2.84 1.64 2.84 1.75 3.58 tphlas/tplhas 1.14 1.29 1.76 1.83 2.14 2.16 2.14 2.16 2.69 2.67 tphlbs/tplhbs 1.33 1.58 1.95 2.12 2.32 2.45 2.32 2.45 2.88 2.96 tphlcs/tplhcs 1.00 0.98 1.63 1.52 2.00 1.85 2.00 1.85 2.56 2.36 tphlss/tplhss 1.41 1.32 2.15 2.06 2.59 2.50 2.59 2.50 3.27 3.17 tpdaas 0.35 0.35 0.35 0.35 0.35 tpdabs 0.62 0.62 0.62 0.62 0.62 tpdacs 0.25 0.25 0.25 0.25 0.25 tpdass 0.59 0.59 0.59 0.59 0.59

samsung asic 5-147 STD111 adder adder/subtracter characteristic reference table (continued) 2) power characteristics [unit: m w/mhz] (typical process, 25 c, v dd =2.5v, c l =10, s=0.2, sa=0.5) 3) size characteristics [unit: m m] case 8 24 36 48 64 sub=0 ovf=0 drv=1 6.46 20.24 30.35 40.27 53.20 drv=2 7.32 22.55 33.85 45.04 59.80 ovf=1 drv=1 6.86 20.35 30.47 40.59 54.09 drv=2 7.65 22.79 34.15 45.51 60.65 sub=1 ovf=0 drv=1 7.44 25.38 38.43 51.12 67.50 drv=2 8.30 28.26 42.73 56.78 74.87 ovf=1 drv=1 7.69 25.73 38.89 51.72 68.33 drv=2 8.59 28.62 43.19 57.38 75.69 type case 8 24 36 48 64 width sub=0 ovf=0 sub=0 ovf=1 64.79 66.13 66.65 66.75 67.26 66.95 67.22 66.94 66.13 66.58 sub=1 ovf=0 sub=1 ovf=1 76.79 78.13 78.65 78.75 79.26 78.95 79.22 78.94 78.13 78.58 height all 90.00 266.00 398.00 530.00 706.00

STD111 5-148 samsung asic bs barrel shifter function description the bs is an n-bit barrel shifter which is provided as a compiler. the bs is intended to use in high-speed and low-power applications. it performs a shifting or circular rotation operation and allows both arithmetic and log- ical shift operations. also, it can shift and rotate input data in either direction and the direction of the shift can be chosen between msb (left) and lsb (right) of the bit string. logical shifts fill vacant bits with zeros, and arithmetic shifts fill spaces with duplicates of the original msb. the vacant bits also can be filled with filler data input(fin). during a right shift, the fin data fills the vacant bits with data from the lsb of the shift data bus. during a left shift, the shift data bus fills the vacant bits with data from the msb of the shift data bus (essentially a circular shift). function table note: an x indicates a dont care condition. msh dir c1 c2 dout 0000 shift right and ?ll with zeros 0001 shift right and ?ll with msb of din[ ] 0010 shift right and ?ll with fin[ ] data 0011 rotate right 0100 shift left and ?ll with zeros 0101 shift left and ?ll with msb 0110 shift left and ?ll with fin[ ] data 0111 rotate left 1 x 0 0 all the bits are set to zero 1 x 0 1 all the bits are set to the msb of din[ ] 1 x 1 0 fin[ ] 1 x 1 1 din[ ] logic symbol features ? asynchronous operation ? 4 to 64 bit barrel shifter ? high speed, low power operation ? transmission gate mutiplexing scheme ? bi-directional shift or rotation ? fill with zero, msb, or filler data ? refresh flag ? two output drive strength available din [bitsC1:0] dout [bitsC1:0] sh [mC1:0] c1 c2 msh m= log 2 bits dir fin [bitsC1:0] bs___d

samsung asic 5-149 STD111 bs barrel shifter parameter description bs is the compiler that automatically generates symbol, netlist, timing model, power model and layout ac- cording to the following parameters. pin description pin capacitance [unit: pf ] block diagram parameter name description range bits number of bits for the input data bus 4 to 64 type direction of shift both/left/right drv drive strength 1/2 name type description din[ ] input data input bus fin[ ] filler data input dir specify the direction of the shift or rotation (left/right) (optional when the parameter type = both) c1, c2 specify the ?ller at the vacant bit (zero/msb/fin[ ]) sh[ ] shift amount (unsigned-magnitude binary) msh maximum shift ?ag. it refreshes all the bits of output data with ?ller according to c1 and c2. dout[ ] output data output bus name case value c1 all 0.0155 c2 all 0.0196 fin[ ] all 0.0071 msh type = both 0.0191 type = left/right 0.0263 din[ ] type = both 0.0171 type = left/right 0.0157 sh[ ] type = both -0.000003*bits*bits+0.000017*bits+0.0580 type = left/right -0.000002*bits*bits+0.000009*bits+0.0288 dir type = both 0.0127 din[ ] fin[ ] c1 c2 fill block sh[ ] direction block dout[ ] msh dir right shift block left shift block

STD111 5-150 samsung asic bs barrel shifter timing diagram timing type de?nition timing type de?nition tphldid/tplhdid propagation delay from din[ ] to dout[ ] tphl?d/tplh?d propagation delay from fin[ ] to dout[ ] tphlshd/tplhshd propagation delay from sh[ ] to dout[ ] tphldrd/tplhdrd propagation delay from dir to dout[ ] tphlc1d/tplhc1d propagation delay from c1 to dout[ ] tphlc2d/tplhc2d propagation delay from c2 to dout[ ] tphlmsd/tplhmsd propagation delay from msh to dout[ ] tpdadid de-access time from din[ ] to dout[ ] tpda?d de-access time from fin[ ] to dout[ ] tpdashd de-access time from sh[ ] to dout[ ] tpdadrd de-access time from dir to dout[ ] tpdac1d de-access time from c1 to dout[ ] tpdac2d de-access time from c2 to dout[ ] tpdamsd de-access time from msh to dout[ ] c1 sh[ ] dir msh din[ ] fin[ ] c2 tpdamsd tpxxmsd dout[ ] tpdac2d tpxxc2d tpdac1d tpxxc1d tpdadrd tpxxdrd tpdashd tpxxshd tpdafid tpxxfid tpdadid tpxxdid * tpxx means tphl or tplh.

samsung asic 5-151 STD111 bs barrel shifter characteristic reference tables 1) timing characteristics [unit: ns] (typical process, 25 c, v dd =2.5v, c l =10, s=0.2, sa=0.5) symbol description unit symbol description unit b number of bits - s input slope ns v dd power supply voltage v sl standard load - c l output load sl sa input switching activity - type 8 24364864 case: type=both, drv= 1 tphlc1d/tplhc1d 1.55 1.58 1.94 1.96 2.15 2.18 2.29 2.35 2.37 2.49 tphlc2d/tplhc2d 1.52 1.56 1.94 2.00 2.18 2.28 2.35 2.52 2.49 2.77 tphldid/tplhdid 1.56 1.48 1.96 1.84 2.19 2.04 2.36 2.17 2.49 2.26 tphlmsd/tplhmsd 0.71 0.73 0.82 0.86 0.90 0.96 0.98 1.06 1.08 1.19 tphlshd/tplhshd 0.98 0.90 1.13 1.16 1.24 1.36 1.35 1.56 1.51 1.82 tphl?d/tplh?d 1.23 1.22 1.52 1.52 1.65 1.66 1.72 1.72 1.71 1.70 tphldrd/tplhdrd 0.62 0.64 0.72 0.77 0.80 0.86 0.87 0.95 0.97 1.08 tpdac1d 1.12 1.28 1.39 1.50 1.66 tpdac2d 1.05 1.14 1.21 1.30 1.43 tpdadid 1.05 1.14 1.22 1.32 1.46 tpdamsd 0.55 0.66 0.74 0.82 0.93 tpdashd 0.76 0.75 0.74 0.73 0.73 tpda?d 0.52 0.61 0.68 0.75 0.85 tpdadrd 0.74 0.88 0.98 1.08 1.21 case: type=left, drv=1 tphlc1d/tplhc1d 1.50 1.52 1.89 1.90 2.10 2.12 2.24 2.27 2.31 2.38 tphlc2d/tplhc2d 1.47 1.51 1.87 1.95 2.11 2.22 2.28 2.45 2.43 2.69 tphldid/tplhdid 1.50 1.42 1.90 1.78 2.13 1.97 2.30 2.10 2.42 2.16 tphlmsd/tplhmsd 0.50 0.52 0.62 0.66 0.69 0.76 0.76 0.84 0.83 0.93 tphlshd/tplhshd 0.96 0.89 1.08 1.10 1.16 1.25 1.24 1.41 1.32 1.61 tphl?d/tplh?d 1.18 1.17 1.46 1.46 1.59 1.60 1.66 1.66 1.66 1.64 tpdac1d 1.09 1.24 1.35 1.46 1.61 tpdac2d 1.01 1.10 1.17 1.25 1.37 tpdadid 1.01 1.10 1.18 1.27 1.40 tpdamsd 0.72 0.70 0.69 0.70 0.71 tpdashd 0.43 0.52 0.58 0.63 0.70 tpda?d 0.71 0.91 1.02 1.11 1.18

STD111 5-152 samsung asic bs barrel shifter characteristic reference table (continued) 1) timing characteristics [unit: ns] (typical process, 25 c, v dd =2.5v, c l =10, s=0.2, sa=0.5) 2) power characteristics [unit: m w/mhz] (typical process, 25 c, v dd =2.5v, c l =10, s=0.2, sa=0.5, drv = 1) 3) size characteristics [unit: m m] type 8 24364864 case: type=right, drv=1 tphlc1d/tplhc1d 1.50 1.53 1.87 1.86 2.07 2.08 2.22 2.28 2.32 2.49 tphlc2d/tplhc2d 1.46 1.51 1.83 1.92 2.07 2.20 2.30 2.46 2.56 2.76 tphldid/tplhdid 1.50 1.43 1.89 1.77 2.12 1.96 2.29 2.09 2.45 2.19 tphlmsd/tplhmsd 0.49 0.52 0.61 0.66 0.69 0.76 0.75 0.84 0.82 0.92 tphlshd/tplhshd 0.96 0.89 1.09 1.10 1.17 1.25 1.23 1.41 1.30 1.62 tphl?d/tplh?d 1.19 1.17 1.45 1.46 1.58 1.60 1.65 1.66 1.65 1.64 tpdac1d 1.09 1.19 1.29 1.43 1.66 tpdac2d 1.00 1.09 1.16 1.25 1.39 tpdadid 1.00 1.09 1.17 1.27 1.42 tpdamsd 0.71 0.69 0.69 0.70 0.73 tpdashd 0.43 0.52 0.58 0.64 0.70 tpda?d 0.71 0.83 0.93 1.02 1.14 case 8 24 36 48 64 type=both 9.94 36.69 57.72 79.58 110.01 type=left 6.82 23.31 36.57 50.57 70.42 type=right 6.80 23.64 36.76 50.30 69.01 type case 8 24 36 48 64 width type=both 114.83 178.33 218.13 251.21 284.88 type=left 76.37 109.57 131.44 150.71 172.38 type=right 76.37 109.57 131.44 150.71 172.38 height all 112.00 288.00 420.00 552.00 728.00

samsung asic 5-153 STD111 mpy modi?ed booth multiplier function description the mpy is an nxm multiplier which is provided as a compiler. the mpy is intended to use in high-speed and low-power applications. it adopts the modified booths multiplication scheme to encode the multiplier bits by partitioning the bits into three bit groups, with one bit shared between groups and performs a signed mul- tiplication operation between two integers. it allows from 6-bit to 64-bit with a configurable size of output buffer and 1-stage pipeline scheme is available to improve the frequency of design. the partial products are summed up with two adders; the msb adder and the lsb adder. the msb adder is a fast group bypass adder. the lsb adder is programmable to insert 1-stage pipeline scheme and is, there- fore, the ripple carry adder. the clock to the pipeline controls the internal data change, so that the data is always stable throughout the clock period and there is no hold problem. parameter description mpy is the compiler that automatically generates symbol, netlist, timing model, power model and layout ac- cording to the following parameters. note: the xbits should be greater than or equal to the ybits (x 3 y). parameter name description range xbits multiplicand (xin) bits 6 to 64 (even) ybits multiplier (yin) bits 6 to 64 (even) pipes pipeline stage 0/1 drv output drive strength 1/2 logic symbol features ? asynchronous/synchronous operation ? 6 to 64 bit multiplication ? high speed/low power operation ? 2s complement signed multiplication ? modified booth algorithm ? 1-stage pipeline insertion available ? two drive strength available. mpy_x_p_d xin [xbitsC1:0] yin [ybitsC1:0] mckn (optional) rstn (optional) pout [pbits - 1:0] * pbits=xbits+ybits

STD111 5-154 samsung asic mpy modi?ed booth multiplier pin description pin capacitance [unit: pf ] block diagram pin name type description xin [ ] input data input bus C multiplicand yin [ ] data input bus C multiplier mckn clock input to the pipeline register. (optional when the parameter pipes = 1) rstn reset negative input to the pipeline register. (optional when the parameter pipes = 1). pout[ ] output data output bus C product result name case value xin[ ] all 0.0153 yin[ ] all 0.0293 mckn pipe=1 0.000018*x_width+0.001406*y_width - 0.000003*x_width*y_width+0.021955 rstn pipe=1 0.000041*x_width+0.003235*y_width - 0.000006*x_width*y_width+0.021454 xin[ ] mbe yin[ ] msb adder lsb adder output pout[ ] buffer array block block block block input buffer block msb adder lsb adder output pout[ ] rstn mckn buffer block mbe array block block block xin[ ] yin[ ] input buffer block

samsung asic 5-155 STD111 mpy modi?ed booth multiplier timing diagram timing type de?nition timing type de?nition tphlxp/tplhxp propagation delay from xin[ ] to pout[ ] tphlyp/tplhyp propagation delay from yin[ ] to pout[ ] tpdaxp de-access time from xin[ ] to pout[ ] tpdayp de-access time from yin[ ] to pout[ ] tphlxp pout[ ] xin[ ] yin[ ] tplhxp tpdaxp tphlyp tplhyp tpdayp

STD111 5-156 samsung asic mpy modi?ed booth multiplier timing diagram (continued) timing type de?nition timing type de?nition setupxck setup time for input xin[ ] to mckn setupyck setup time for input yin[ ] to mckn setuprck setup time for input rstn to mckn holdxck hold time for input xin[ ] to mckn holdyck hold time for input yin[ ] to mckn holdrck hold time for inptu rstn to mckn minhpck minimum clock pulse width high minlpck minimum clock pulse width low minlprn minimum clock pulse width rstn tphlckp/tplhckp propagation delay from mckn to pout[ ] tphlrnp/tplhrnp propagation delay from rstn to pout[ ] tpdackp de-access time from mckn to pout[ ] tpdarnp de-access time from rstn to pout[ ] setupxck minhpck setupyck minlpck holdxck holdyck setuprck holdrck rstn xin[ ] yin[ ] mckn pout[ ] tpdackp tpdackp tpdarnp minlprn tphlckp tplhckp tphlckp tplhckp tphlckp tplhckp asynchronous reset synchronous reset 0 0 0 0 0 0 0 0 0 0 0 0 0 * note: asynchronous reset: rstn goes to low state, when mckn is at high state. synchronous reset: rstn goes to low state, when mckn is at low state.

samsung asic 5-157 STD111 mpy modi?ed booth multiplier characteristic reference table 1) timing characteristics [unit: ns] (typical process, 25 c, v dd =2.5v, c l =10, s=0.2, sa=0.5) symbol description unit symbol description unit b number of bits - w number of yin[ ] bits - v dd power supply voltage v s input slope ns c l output load sl sa input switching activity - type 8x8 24x24 36x36 48x48 64x64 case: pipes=0,drv=1 tphlxp/tplhxp 2.72 / 2.68 5.78 / 5.65 8.01 / 7.87 10.17 / 10.10 12.96 / 13.06 tphlyp/tplhyp 2.37 / 2.22 4.56 / 4.46 6.20 / 6.13 7.84 / 7.81 10.02 / 10.05 tpdaxp 1.02 1.23 1.43 1.66 2.00 tpdayp 1.97 2.24 2.43 2.63 2.90 case: pipes=1,drv=1 holdrck 0.00 0.00 0.00 0.00 0.00 holdxck 0.00 0.00 0.00 0.00 0.00 holdyck 0.00 0.00 0.00 0.00 0.00 minhpck 0.57 0.71 0.81 0.90 1.04 minlpck 0.23 0.30 0.35 0.40 0.47 minlprn 0.67 1.09 1.47 1.91 2.59 setuprck 0.67 1.09 1.47 1.91 2.59 setupxck 1.66 3.04 4.09 5.13 6.52 setupyck 1.88 2.90 3.67 4.43 5.45 tphlckp 1.83 3.44 4.55 5.58 6.81 tphlrnp 1.72 2.07 2.32 2.58 2.92 tplhckp 1.47 3.06 4.19 5.28 6.65 tplhrnp 0.00 0.00 0.00 0.00 0.00 tpdackp 0.52 0.57 0.61 0.66 0.71 tpdarnp 0.61 0.69 0.75 0.81 0.89

STD111 5-158 samsung asic mpy modi?ed booth multiplier characteristic reference table (continued) 2) power characteristics [unit: m w/mhz] (typical process, 25 c, v dd =2.5v, c l =10, s=0.2, sa=0.5) 3) size characteristics [unit: m m] case 8x8 24x24 36x36 48x48 64x64 pipes=0, drv=1 62.32 385.23 1209.05 2531.42 5070.11 pipes=1, drv=1 85.17 328.68 964.13 1987.71 3956.24 type case 8x8 24x24 36x36 48x48 64x64 width pipes=0, drv=1 222.06 475.21 668.62 865.07 1131.74 pipes=1, drv=1 276.30 531.49 723.89 917.16 1176.21 height pipes=0, drv=1 112.00 288.00 420.00 552.00 728.00 pipes=1, drv=1 123.00 299.00 431.00 563.00 739.00

6 pll

contents pll2013x ....................................................................................................................... ..... 6-1

samsung asic 6-1 STD111 pll2013x block diagram figure 6-1 phase locked loop block diagram note: x-tal oscillator and lock detector are optional block. if customer concerns about this block - xtal buffer or lock detector, refer to optional block users guide (page 6-6). general description the pll2013x is a phase-locked loop (pll) frequency synthesizer constructed in cmos on single monolithic structure. the pll macrofunctions provide frequency multiplication capabilities. the output clock frequency fout is related to the input clock frequency fin (xtalin) by the following equation: fout = (m fin) / (p s). where, fout is the output clock frequency. fin is the input clock frequency. m, p and s are the values for programmable dividers. pll2013x consists of a phase/frequency detector (pfd), a charge pump, an external loop filter, a voltage controlled oscillator (vco), a 6-bit pre-divider, an 8-bit main divider and a 2-bit post scaler as shown in figure 6-1. features ? 0.25 m m cmos device technology ? 2.5v single power supply ? output frequency range: 20-170mhz ? jitter: 150 ps at 170mhz ? duty ratio: 45% to 55% (all tuned range) ? frequency changed by programmable dividers ? provision for 14.318mhz crystal oscillator buffer (option) ? lock detector (option) ? power down mode charge fout pump pre-divider p pfd vco post scaler s main divider m loop filter fin

pll2013x 20mhz-170mhz fspll STD111 6-2 samsung asic pin description figure 6-2 core con?guration name i/o type i/o pad pin description vdd25a2 digital power vdd2t_abb digital power supply vss25a2 digital ground vss2t_abb digital ground vdd25a1 analog power vdd2t_abb analog power supply vss25a1 analog ground vss2t_abb analog ground vbba analog sub bias /digital sub bias vbb_abb analog/digital sub bias fin digital input picc_abb reference frequency input filter analog output poar50_abb pump out is connected to ?lter. a capacitor is connected between the pin and analog ground. fout digital output pot8_abb 20mhz~170mhz clock output pwrdn digital input picc_abb fspll clock power down. - when pwrdn is high, pll do not operate. - if pwrdn is not used, it should be tied to vss. p[5:0] digital input picc_abb the values for 6bit programmable pre-divider. m[7:0] digital input picc_abb the values for 8bit programmable main divider. s[1:0] digital input picc_abb the values for 2bit programmable post scaler. fout filter m[7:0] fin pwrdn pll2013x m[0] m[1] m[2] m[3] m[4] m[5] m[6] m[7] p[5:0] p[0] p[1] p[2] p[3] p[4] p[5] s[1:0] s[0] s[1]

20mhz-170mhz fspll pll2013x samsung asic 6-3 STD111 recommended operating conditions note: it is strongly recommended that all the supply pins (vdd25a2, vdd25a1) be powered from the same operating supply voltage to avoid power latch-up. dc electrical characteristics ac electrical characteristics note: it is strongly recommended that input signal is not generated glitch, but if customer cannot help generating glitch, customer must carefully considerate the specification. characteristics symbol min typ max unit supply voltage vdd25a2 - vdd25a1 -0.1 +0.1 v oscillator frequency fosc 14.318 mhz external loop ?lter capacitance lf 820 pf operating temperature topr 0 70 c characteristics symbol min typ max unit operating voltage vdd25a2/vdd25a1 2.375 2.5 2.625 v digital input voltage high v ih 1.9 v digital input voltage low v il 0.5 v dynamic current idd 3 ma power down current ipd 50 m a characteristics symbol min typ max unit crystal frequency f xtal 14.318 mhz input frequency f in 2 40 mhz output clock frequency f out 20 170 mhz input clock duty cycle t id 40 60 % output clock duty cycle (at 170mhz) t od 45 55 % input glitch pulse width t igp 1ns locking time t lt 150 m s jitter, cycle to cycle t jcc -150 + 150 ps

pll2013x 20mhz-170mhz fspll STD111 6-4 samsung asic functional description a pll is the circuit synchronizing an output signal (generated by an vco) with a reference or input signal in frequency as well as in phase. in this application, it includes the following basic blocks. the voltage-controlled oscillator to generate the output frequency the divider p divides the input frequency by p the divider m divides the vco output frequency by m the divider s divides the vco output frequency by s the phase frequency detector detects the phase difference between the reference frequency and the output frequency (after division) and controls the charge pump voltage. the loop filter removes the high frequency components in charge pump voltage and gives smooth and clean control to vco the m, p, s values can be programmed by 16bit digital data from the external source. so the pll can be locked in the desired frequency. fout = (m fin) / (p s) where fin = 14.318mhz, m = m + 8, p = p + 2, s = 2 s table 6-1 digital data format notes: 1 . s[1]-s[0]: output frequency scaler 2. m[7]-m[0]: vco frequency divider 3. p[5]-p[0]: input frequency divider output frequency equation & table frequency equation: table 6-2 example of divider ratio main divider pre divider post scaler m7, m6, m5, m4, m3, m2, m1, m0 p5, p4, p3, p2, p1, p0 s1, s0 m7 m6 m5 m4 m3 m2 m1 m0 m m(m+8) s1 s0 2 s 0101010 1 85 93 001 p5 p4 p3 p2 p1 p0 p p(p+2) 1010104244 f out m8 + () p2 + () 2 s ------------------------------ f in =

20mhz-170mhz fspll pll2013x samsung asic 6-5 STD111 core evaluation guide for the embedded pll, we must consider the test circuits for the embedded pll core in multiple applications. hence the following requirements should be satisfied. the filter and fout pins must be bypassed for external test. for pll test (below 2 examples), it is needed to control the dividers - m[7:0], p[5:0] and s[1:0] - that generate multiple clocks. #1. registers can be used for easy control of divider values. #2. n sample bits of 16-bit divider pins can be bypassed for test using mux. figure 6-3 pll functional block diagram fout filter m[7:0] fin pwrdn pll2013x p[5:0] s[1:0] external clock source #1. 16-bit register block #2. mux select pin test pins of n sample bits internal divider signal line gnd 2.5v digital power gnd 2.5v analog power 820pf vss25a1 vdd25a2 vss25a2 vdd25a1 vss25a1 vbba : 10 m f electrolytic capacitor, unless otherwise speci?ed : 104 ceramic capacitor, unless otherwise speci?ed

pll2013x 20mhz-170mhz fspll STD111 6-6 samsung asic core layout guide the digital power (vdd25a2, vss25a2) and the analog power (vdd25a1, vss25a1) must be dedicated to pll only and separated. if the dedicated vdd25a2 and vss25a2 is not allowed that of the least power consuming block is shared with the pll. the poar50_abb pad is used as a filter pad that contains only esd production diodes with 50ohm resis- tors. the fout and filter pins must be placed far from the internal signals in order to avoid overlapping signal lines. the blocks having a large digital switching current must be located away from the pll core. for the fout pad, you can use a custom drive buffer or pot8_abb buffer considering the drive current. optional block users guide there are crystal driver cell options for the pll2013x core 1. if the crystal component not used, an external clock source is applied to the fin - if the crystal component not used, an external clock i/o buffer offered from samsungs STD111 library is recommended for use - when implementing an embedded pll block, the following pins must be bypassed externally for testing the pll locking function: ? without xtal-driver: fin, filter, fout, vdd25a1, vss25a1, vdd25a2 and vss25a2, vbba. 2. if the crystal componet and the lock detector used, please contact sec application engineer - when implementing an embedded pll block, the following pins must be bypassed externally for testing the pll locking function: ? with xtal-driver: xtalin, xtalout, ldout, filter, fout, vdd25a1, vss25a1, vdd25a2 and vss25a2, vbba figure 6-4 the example of pll block with crystal component and lock detector xtalin ldout fout xtalout glue logic filter mux xtal osc fin pfd p[5:0] lf divider m scaler s m[7:0] s[1:0] divider p vco ld & cp up down pwrdn * optional test pin *divider bus

20mhz-170mhz fspll pll2013x samsung asic 6-7 STD111 xtal buffer cell figure 6-5 xtal pad symbol - a xtal buffer cell for pll is supported STD111 databook of samsung. - the xtal must be located between pada and padb. enable pin (e) must be high in normal operation. - pi pin must be connected to vdd25a2 and the po pin floated. lock detector figure 6-6 lock detector block the built-in lock detector circuit will only work, when it is used in conjunction with pfd block output up/down signal. (refer to figure 6-6) we represent the output of lock detector in the timing diagram. (refer to figure 6-7) figure 6-7 lock detector timing diagram e pa da padb pi yn po internal up signal internal down signal ls ldout lo lock state detector up/down ldout lo lock unlock

pll2013x 20mhz-170mhz fspll STD111 6-8 samsung asic package configuration pll2013x 12 11 8 10 9 7 6 5 4 3 2 1 0.1 m f 10 m f 24 23 20 22 21 19 18 17 16 15 14 13 37 38 41 39 40 42 43 44 45 46 47 48 25 26 29 27 28 30 31 32 33 34 35 36 vssa vssa nc ldout nc nc nc tst3 tst2 tst1 p5 p4 nc fout vbb nc nc vbb pwrdn filter xtalout xtalin vdda vdda m0 m1 m4 m2 m3 m5 m6 m7 p0 p1 p2 p3 nc nc tst4 vsso vddo tst5 s1 s0 vssd vssd vddd vddd

20mhz-170mhz fspll pll2013x samsung asic 6-9 STD111 package pin description notes: 1. i/o type pp and pg denote pad power and pad ground respectively. 2. xtalin, xtalout, ldout is test pin for pll in samsung. name pin no. i/o type pin description vddd 35, 36 dp digital power supply vssd 33, 34 dg digital ground vbb 19, 20 ab/db analog / digital sub bias pwrdn 18 di fspll clock power down. - when pwrdn is high, pll do not operate. - if pwrdn is not used, it should be tied to vss. p[0]~p[5] 45~48, 1, 2 di pre-divider input vdda 13, 14 ap analog power supply vssa 11, 12 ag analog ground xtalin 15 ai xtal external input load cap: 25pf if customer dont use the xtal, use this pin to input port. xtalout 16 ao xtal external output load cap: 25pf if customer dont use the xtal, float this pin. fout 23 do 20mhz~170mhz clock output ldout 10 do lock detector output filter 17 ao pump out is connected to the ?lter. a 820pf capacitor is connected between the ?lter pin and analog ground pin s[0]~s[1] 32, 31 di post scaler input m[0]~m[7] 37~44 di 8-bit main divider input tst1, tst3 3, 5 di test pin, apply to analog vdda tst2, tst4, tst5 4, 29, 30 di test pin, apply to ground vddo 28 pp i/o pad power vsso 27 pg i/o pad ground

pll2013x 20mhz-170mhz fspll STD111 6-10 samsung asic design considerations the following design considerations apply: ? jitter is affected by the power noise, substrate noise, etc. it increases when the noise level increases. ? a cmos-level input reference clock is recommend for signal compatibility with the pll circuit. other levels such as ttl may degrade the tolerances. ? the used of two, or more plls requires special design considerations. please consult your application engineer for more information. ? the following apply to the noise level, which can be minimized by using good analog power and ground isolation techniques in the system: - use wide pcb traces for power (vdd25a2/vss25a2, vdd25a1/vss25a1, vbba) connections to the pll core. separate the traces from the chips vdd25a2/vss25a2, vdd25a1/vss25a1 supplies. - use proper vdd25a2/vss25a2, vdd25a1/vss25a1 de-coupling. - use good power and ground sources on the board. - use power vbba for minimize substrate noise. ? the pll core should be placed as close as possible to the dedicated loop ?lter and analog power and ground pins. ? it is inadvisable to locate noise-generating signals, such as data buses and high-current outputs, near the pll i/o cells. ? other related i/o signals should be placed near the pll i/o but do not have any pre-de?ned placement restriction.

20mhz-170mhz fspll pll2013x samsung asic 6-11 STD111 pll speci?cation we appreciate your interest in our products. if you have further questions, please specify in the attached form. thank you very much. ? do you need xtal driver buffer in pll core? - if you need it, what is the crystal frequency range? - if not, what is the input frequency range? ? do you need the lock detector? ? do you need the i/o cell of samsung? ? do you need the external pin for pll test? ? what is the main frequency and frequency range? ? how many fsplls do you use in your system? ? what is output loading? ? could you internal/external pin configurations as required? ? specially requested function list: parameter min typ max unit remarks supply voltage output frequency range input frequency range cycle-to-cycle jitter lock up time dynamic current standby current output clock duty ratio long term jitter output slew rate

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